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On Sat, 22 Feb 1997 02:00:58 -0500, Bill Harris <wmharris@cisco.com> wrote: >Lets talk about nonsense. Lets look at the Xilinx app note located at >http://www.xilinx.com/partinfo/3volt.pdf <snip of valid problems with 4000E driving 3.3V devices> Amen to all that. They also say it gets out of hand with industrial temp due to +/- 10% supply swing. IMHO It's a kludge to get them off the hook because 4000L is so comparatively slow. What (if I may be so bold) do you use? StuartArticle: 5526
On 20 Feb 1997 15:48:28 GMT, "Austin Franklin"
<#darkroom@ix.netcom.com#> wrote:
>Aaron,
< Snip >
>Austin Franklin
>..darkroom@ix.netcom.com.
>
Austin:
I'm the engineer that Aaron was referring to. Given your response to
his statements, I thought I would clarify the system and constraints
we were working with. The subsystem being implemented with the Xilinx
part performed the following functions:
900 ns A/D interface, 1.5 us Quad serial D/A interface and DMA engine
used to interface the A/D and D/A subsystems to a processor using two
memory resident table driven schedulers (Approx. 300 CLB's.)
6 center drive PWM modulators with anti-overlap, controlling 2
brushless DC motors. (Approx 200 CLB's)
The system target clock was 10 Mhz and the processors targeted were
the ADSP2181 and MC56301 (2 different DMA interfaces were developed
and simulated - The figures used are for the 56301 interface)
The FPGA design was entered as approx. 28 pages of schematic, which,
given the hierarchical and repetitive nature of the design would
expand to approx. 38 pages if flattened.
You would expect that this design would be fairly straight forward
and, that given the low clock speed, should have been fairly easy to
meet to design goals using a 4008A. It wasn't.
The principal problem with the XACT tools (Aside from being sloooow)
is that it's place and route stinks. To require ANY manual
intervention on a < 80% utilized design at 10 Mhz is absurd. The
Xilinx parts themselves are not bad, but the XACT tools are poor. By
my estimates, the job using the XACT + Orcad tools cost the job
approx. 2 mos. (over and above the expected learning curve).
Contrast the previous design with the current Altera design I am
doing: (BTW the Altera design took less than 3 mos. to design and
simulate, and was debugged and operating 3.5 weeks after power was
first applied)
The target chip is an 81500 (8K series because the customer didn't
have the 10K tools).
The design consists of:
16/20 bit micro coded special purpose processor for low level motor
control functions. (approx. 500 LE's)
Synch. serial communications interface (1Mb/sec) (speed limited by
opto interface) (approx. 100 LE's )
A/D interface and sequencer (approx. 100 LE's)
4x DAC interface (approx. 50 LE's)
Center drive PWM modulator, anti-overlap, and trap drive output decode
for three phase motor drive. (approx. 100 LE's)
This design is somewhat <Grin> bloated due to the Altera part's lack
of internal tri-state busses. This is exacerbated by the LE being
implemented as a 4 input LUT. This is fairly inefficient at
implementing the muxes (on the plus side it is helped by the cascade
logic chains) used to "emulate" the busses. The net effect of this is
to use approx. 25% of the logic to implement the busses. This lack
though, is more than made up by the tools WHICH SIMPLY WORK.
This design is approx. 42 pages of schematic and AHDL. At various
times in the design life this design reached 95% utilization (the
memory was being implemented on chip at the time). On a 100Mhz Pentium
W/40MB RAM this design compiles in approx. 15-20min and NEVER required
manual layout intervention to achieve >13Mhz performance. In spite of
the fact that the pins had been locked BEFORE the architecture was
completed, well before the design was even entered (required by the
parallel PWB generation). The Altera tools have their faults, the
parts have their limitations, but I spent <5% of my time fighting
Altera tool/part limitations V.S. >35% on the Xilinx tools (again,
exclusive of the learning curve).
From my point of view, in spite of the architectural advantages that
the Xilinx 4000 series has over the Altera 8K series (continued in the
4000EX /10K generation) the Altera tools are so much better than the
XACT tools that it is no contest.
Mark Adams
US017033@mindspring.com
BTW, I have been playing with the 10K parts, and without manual layout
intervention or tuning, I created a 24 bit shift and add 4 quadrant,
2's comp. parallel frac. multiplier in 123 LE's (including local seq.
control logic and operand latches) which clocks at 74Mhz with a -3
part (64Mhz with a -4 part). Pretty fast for something requiring a
long carry chain, busses, and conditional operations.)
Article: 5527Peter Alfke wrote: > Xilinx has a broader product offering in FPGAs or equivalent devices ( > XC2000, 3000, 3100, 4000, 4000EX, 5200, 6200 ) with more package options. > Many of these families are pin-compatible within the family and between > families. You can migrate a design without re-laying-out your pc-board. Altera are, far too late, getting a lot better at this. An 84-pin PLCC Xilinx device does get you a huge array of devices, if you can spare the space. (Altera lost a design to Xilinx based on this last year, (a network card with support for many, many line interfaces and protocols, where the gate count varied by a factor of over 100)) > Xilinx devices tolerate pin-locking better than Altera's, an obvious > result of the different interconnect architecture. This has not been my experience. An almost-full Xilinx device gets very sensitive to pin positioning, I find. So do Altera devices, but I've not been hit as hard (yet?) > As pc-board lead times exceed FPGA design times, this becomes a critical issue. I get my PCBs made on a 12-hour turn. Perhaps I'm a bit slow, but I rarely get an FPGA design completed that fast.... > Xilinx XC4000 and 4000EX offer BlockRAM, distributed RAM in the CLBs which > offer very fast, synchronous and even true dual-port RAM. ( Altera's 10K > offers a much smaller number of bigger and simpler RAMs ). I find the bigger blocks of RAM to be more convenient. That's probably just my take on it, though. >Xilinx has app > notes describing the use of these RAMs as very fast FIFOs, one of their > most popular applications. Bu I seem to remember that one ends up devoting a fair amount of the silicon to this? If I want fast FIFOs, I'll buy them and hang them outside, if my FPGA can't cut it. (I also tend to want much, much bigger FIFOs than will fit in any sane FPGA) > Xilinx power consumption is lower, everything else being equal. This is > the result of the different interconnect structure, and no marketing > posturing can defy the laws of physics. Yet I find Altera 8K devices running cooler than Xilinx 3k1 series, running the same VHDL at the same speed. It's no proof, just interesting. Maybe everything else isn't equal? > ( The Altera message that the "sum > of internal power is proportional to the percentage of blocks toggling at > the clock rate" is wrong. It's tough to respect people who publish this > kind of nonsense ). I've not cared enough about power consumption (yet?) to read either side's hype. > Xilinx interconnect can be significantly faster than Altera's, for the > same reason as above. It is true that a complicated concatenated > interconnect can get slow in a Xilinx device, but the user can influence > that by prescribing the max tolerable delay, and let the software do the > work. Yes, short runs of interconnect can be very fast in Xilinx devices. It's only when I get a few CLBs in series that the speed plummets. Modifying VHDL to put more and more pipeline stages in to cut the path length lost its appeal some time ago. For tiny, fast state machines, I'll take Xilinx (or a CPLD solution off-chip). Bigger state machines seem to run faster in Altera devices. I imagine the same effect cuts in for Altera when I spill out from a single LAB, but that's an easier constraint for me to meet. Try to capture 200-MHz data in an 8k or 10k device, but you can in > XC3100. Try to build a 50 MHz fully asynchronous FIFO in 10K, but you can > in XC4000E. The richness of the Xilinx interconnect structure offers extra > flexibility to achieve highest performance. But I _can't_ run a non-trivial machine at 200MHz in either architecture. Maybe I'm missing the point again. > Regarding software, it is no secret that Altera's compiles faster Yup. No argument >( that is an obvious result of their simpler interconnect structure), Does that somehow demean it? > and traditionally Altera's software has been easier to use. But on the other > hand, Altera's software can be extremely frustrating for the power user, > because certain things just cannot be done. ( "...when she was good, she > was really good, but when she was bad she was horrid..".). Xilinx software > has always given the user full access to all the device features. Many > users love that, others complain about the learning curve.... I'll admit, I like the Xilinx tools. I like the level of control I get. If I want to build tiny, tight machines, there's (currently?) no better environment. What I don't like is _having_ to use them at the lowest level. I spent 3 weeks trying to get a design working in a 3164a. It was a couple of k-lines of VHDL. Messing with the layout after each VHDL change became a nightmare. Perhaps it's an effect of the Xilinx-supplied VHDL tools, so that all node names change per-compile, and seem to consist soley of strings of the characters 1, l, i, I, $, 5 and S that made debugging such a pain, or perhaps I'm only supposed to take contracts from customers who never change the specs mid-project? After the third wasted weekend, I gave in, compiled the VHDL (with an afternoons worth of changes to the Xilinx-specific bits) into an Altera 8K, using a borrowed toolset. I never even bothered to take out the hacks I'd made to the source to get a better fit to the Xilinx archirecture, as the design was a) getting late and b) functional at full speed. The silicon was cheaper, too, but that was secondary. Result, delivery on-time. (just....), payment, continuation of livelihood and a certain amount of re-evaluation. > It is interesting to note that Xilinx software is becoming easier and more > user-friendly, and Altera's is becoming more complex, as time goes on... Yes. Perhaps they'll converge. It was very pleasant to be able to port VHDL between families as easily as I could. In a perfect world, I'll choose silicon per-project, without the tools worries. > Lastly, I invite every user to form his/her own opinion about the quality > of technical support and the level of "honesty in marketing" displayed by > the two companies. I am too close to that issue to be objective, but I > think it is very important. End of soapbox. I believe you pushed it rather hard, here. Neither company has perfect tools, silicon or marketing. When they do, I'll retire, as my customers will be able to communicate telepathically with the silicon and save me a lot of effort! > I hope I did not start a flame. Close, very close. (For the record, I am not associated with either of the above companies, except as a customer. I still use both manufacturers, making choices based on my imperfect knowledge of an imperfect world) Steve -- Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK Desk +44 1223 578524 (Fax 578524) Group +44 1223 578518 steve@sj.co.ukArticle: 5528
In article <330CCA1B.28FF@hns.com>, "Kevin D. Drucker" <kdrucker@hns.com> writes >Sorry about the psuedo-spam... > >I am looking for a tool to assist me in documenting state machines. >Something similar to Rational Rose (which is a C++ tool), but >specifically geard towards digital logic design. It would be nice if it >allowed you to show the diagrams either as a mealy or moore type >machine. > >Any one know of such a tool? If there is a shareware program out there >that'd be great. Windoze 95 or HP-UX... Try flowHDL from KBS. This is a great tool, runs on UNIX (Sun,HP,IBM). Produces VHDL or Verilog from the same diagram and has a built in simulator. Supports multiple state machines (parallel), sync/async resets, seperate control and datapath clocks. It also handles test benches graphically as well (splits them into seperate HDL files). Supports all of the main stream synthesis tools too. -- Steve BirdArticle: 5529
Graham Seaman wrote: > > Hi all, > > I'm trying to implement a cellular structure using Altera's > MaxPlus software; that is, I have a simple basic 'cell' of > about 10 gates which I need to replicate many times across > the FPGA (connections are mostly NEWS style; ie. to 4 nearest > neighbours of each cell). > If I was doing this in VHDL, I'd just use the 'generate' > statement in a nested for loop. But I don't have VHDL, only > AHDL, and can't work out a good way of doing this. Or am > I better off sticking to schematic entry (lots of cut-and-paste)? Graham, I don't know which version of Maxplus you have, but the latest versions have GENERATE capability in AHDL. Altera made some major additions to AHDL when they came out with LPM "megafunctions" a year or so ago (Version 6.0 I think). The additions were not documented very well at first, and the new functions were not listed the their AHDL book. They are in the on-line help for Version 7.0 however. Search for Generate keyword (AHDL) and there is a nice example of how to use it. If you have LPM support in your software, you can pull up the AHDL for one of their LPM designs, such as LPM_COUNTER, and see examples of how they use them in their own functions. If you don't have the latest version you can try the old fashioned way... Use the hierarchy of AHDL. Do an AHDL implementation of the logic that you want to replicate, as if it were a stand alone design. Create a top level design and declare your replicated logic design as a function. Now you can instantiate the function in the VARIABLES section of the top level design. You can make multiple instantiations in a single line such as: FRED[20..0] : MY_FUNCTION; In the body of the top level design, you can make common connections (i.e. a common clock, enable or reset) to all instantiations of your function in a single line such as: FRED[].clock = 25MHZ; FRED[].clear = SYSRESET; and so on.... You can make connections between instantiations like this: FRED[1].some_input = FRED[2].some_output; The ".name" is the name of the signal as you declared it in the function statement. It is more verbose than a VHDL generate statement, but a heck of a lot easier than schematics. Look at Maxplus help for more info, it is quite good, although you can get lost pretty easily. The "NEWS" interconnection is Xilinx speak, and doesn't serve well in the Altera architecture. It would be difficult, if not impossible, to force the interconnects exactly the way you want them. The "floorplanner" in Maxplus is really just a graphical placement viewer which allows you to manually make assignments if you wanted to. It does not provide a means of manual interconnect, ala the XACT tool. Beware, however, that you can make manual assignments to individual logic cells in such a way that you guarantee a no-fit situation. This is particularly bad if you also pre-assign the pinouts. If you want to constrain the placement, stick to assignments where logic is grouped into rows or LABs. It is really important to the router that it have the freedom to shuffle logic between the 8 logic cells in each LAB. If you overconstrain, you wind up in trouble very quickly. The best thing to start out with is without placement assignments, but assign timing requirements. Let the compiler do the hard work. Hope that helps some... Bill Harris Cisco SystemsArticle: 5530
>Reverse engineering is far more difficult. It is almost impossible to >deduce the FPGA design from the bitstream. Is this not what Neocad must obviously have done? Before Xilinx bought them, I mean :) Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5531
In article <5ema4m$bc1$1@news.pacifier.com>, szamos@pacifier.com (szamos) wrote: >Austin Franklin (#darkroom@ix.netcom.com#) wrote: >: >: The Altera design environment is not any industry standard. They have >: their own schematic capture and HDL. To me, this means the engineer has to >: learn 'yet another proprietary schematic capture and HDL' to get the job >: done. > >While they do have their own HDL, Max+Plus II also takes .edf which >can generated from Verilog, VHDL, etc. And Viewlogic, and OrCAD, and .............. WayneArticle: 5532
Stuart Clubb wrote: > > On Sat, 22 Feb 1997 02:00:58 -0500, Bill Harris <wmharris@cisco.com> > wrote: > > >Lets talk about nonsense. Lets look at the Xilinx app note located at > >http://www.xilinx.com/partinfo/3volt.pdf > > <snip of valid problems with 4000E driving 3.3V devices> > > Amen to all that. They also say it gets out of hand with industrial > temp due to +/- 10% supply swing. IMHO It's a kludge to get them off > the hook because 4000L is so comparatively slow. > > What (if I may be so bold) do you use? > > Stuart Stuart, I use whatever is the best device for the particular design in terms of suitability, price, performance, availability, etc. I have done several Xilinx 3K, 4K and 7300 designs (one board had all three families on the same board), and more Altera 5K, 7K and 8K designs than I care to remember. I have also done a couple of MACH parts and a few Lattice designs. I do have the luxury of having access to all the different vendor's tools, which most engineers at small companies do not have. I find that the Altera designs are generally the least troublesome with the smoothest development flow, but when things go bad, the Altera tools don't give you the flexibility to get into the part and really tweak it like the Xilinx tools do. Fortunately, those situations are few and far between these days. I recognize marketing hype when I see it, and consider the source when I see outrageous claims for any electronic component which are obviously not from the engineering group. When I see bad engineering recommendations coming from a companies' applications group, it does put some doubt in my mind about their products. Bill Harris Cisco Systems "My opinions are my own and do not necessarily reflect those of my employer"Article: 5533
The Lattice parts do not provide enough resources to do a PCI interface, except a simple target. If you want burst target or master functionality, the Xilinx parts are the only ones that can do it. Austin Franklin ..darkroom@ix.netcom.com.Article: 5534
Mark, In the original post, it was stated the problem was with the Orcad/Xilinx interface, in reading your e-mail, that doesn't sound like that was the problem at all. I'm glad you elaborated on what the problem was..... > To require ANY manual > intervention on a < 80% utilized design at 10 Mhz is absurd. The > Xilinx parts themselves are not bad, but the XACT tools are poor. It is always to your advantage to do manual placement if the design has any regular structures in it, i.e. registers, counters, tri-state busses (or even logic-muxed busses) etc. The 10MHz I agree with, should have been real easy, but not the %80 utilization, especially if you have regular structures. I have used both the Altera tools and the Xilinx tools, and the Xilinx tools have a much better router than the Altera tools. No tool set today for either FPGAs, ASICs or PCBs can do placement on regular structures anywhere near as well as we humans can. > By > my estimates, the job using the XACT + Orcad tools cost the job > approx. 2 mos. (over and above the expected learning curve). > > Contrast the previous design with the current Altera design I am > doing: (BTW the Altera design took less than 3 mos. to design and > simulate, and was debugged and operating 3.5 weeks after power was > first applied) It's always easier to do things faster and better the second time, so that data is not really relevant. > > The target chip is an 81500 (8K series because the customer didn't > have the 10K tools). > > The design consists of: > > 16/20 bit micro coded special purpose processor for low level motor > control functions. (approx. 500 LE's) > > Synch. serial communications interface (1Mb/sec) (speed limited by > opto interface) (approx. 100 LE's ) > > A/D interface and sequencer (approx. 100 LE's) > > 4x DAC interface (approx. 50 LE's) > > Center drive PWM modulator, anti-overlap, and trap drive output decode > for three phase motor drive. (approx. 100 LE's) > > This design is somewhat <Grin> bloated due to the Altera part's lack > of internal tri-state busses. Which, in a Xilinx, when placed (which is real easy to do...) take up no routing or logic resources. When not placed, they can really screw things up, which is what happened to you. If you spend a week doing placement on the design, it would have saved you weeks and weeks of frustration with routing. It also speeds up the routing from hours to minutes, so it pays for it self to expect to do this up front. The Xilinx tools also have a GUI for doing floorplanning which makes it really easy to floorplan the regular structures. I almost never floorplan the random logic, because the tools do a better job than I can with these in almost every case. I'm glad you got your stuff to work. It might have been in your best interest to hire a consultant who was knowlwdgeable with the tools/parts you were using, and ask them to either do the placement for you (which I have done for many satisfied customers ;-) ) or give you a short lesson on how to do it, and set you up with a template so you could build from that. If you want to e-mail me your .xff file, I would be interested in seeing what could have been done with it... I would hate to see you throw the Xilinx parts (which can be a far better part for a lot of applications) out of your bag of tools if there was something that could have been easily done to solve your problem. Did you contact your Xilinx local FAE, or the Xilinx tech support and tell them your problem? If you did, and they didn't tell you about the floorplanner, or how to do placement, then they did you a dis-service. Could you please e-mail the name of your local Xilinx rep? Thanks! Austin Franklin ..darkroom@ix.netcom.com.Article: 5535
That would be a tight squeeze, if able to be done at all. It certainly would leave no room for much of a back end interface.... Could you be so kind as to elaborate on how you did this? It seems like the resources needed to implement a target are barely there, much less a master? Thanks, Austin Franklin darkroom@ix.netcom.com Hack-Man <sahack@ccgate.hac.com> wrote in article <330A2E36.781B@ccgate.hac.com>... > We have used Altera MAX7000 parts to implement PCI masters and targets. > At first we target Xilinx, but couldn't get the claimed speed. We had > Xilinx Apps help, and they did worse than we did. So.....Altera seems > to be the way to go. > > Scott >Article: 5536
In article <330EF6D7.2311@sj.co.uk>, steve@sj.co.uk says... It's always fun to watch civilians beat on Peter Alfke [Xilinx] <g>. In a recent episode, the following excerpt is replayed... > > Xilinx devices tolerate pin-locking better than Altera's, an obvious > > result of the different interconnect architecture. > > This has not been my experience. An almost-full Xilinx device gets very > sensitive to pin positioning, I find. So do Altera devices, but I've > not been hit as hard (yet?) > > > As pc-board lead times exceed FPGA design times, this becomes a critical issue. > > I get my PCBs made on a 12-hour turn. Perhaps I'm a bit slow, but I > rarely get an FPGA design completed that fast.... Steve, I'm deeply envious of your access to miraculous PC board turns. However, Peter has a good point here, and your comments shouldn't be allowed to stand without some gratuitous followup! 1. For the rest of us, PC board layout, drcs, checking, "tapeout", tooling, fab, incoming inspection, build, cleaning, test, etc. represents a *way* longer "turn" than most FPGA design changes that *may* affect pinout in an FPGA. The ability of an FPGA to accommodate unanticipated pinout changes is arguably a very valuable attribute. 2. Once a board is built, and is in the hands of several development/eval/test engineers, design changes in the form of FPGA "code" are *much* easier to distribute and install than a "board turn". I understand your enthusiasm in presenting the "other side" to Peter's assertions, but in this one case you may have outrun the lot of us. > Steve > Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5537
Austin Franklin wrote: > > Paul, > > Given what you say, then it is impossible to meet the PCI requirements for > a master in an Altera part? The CEs are required in the IOB in case the > master disconnects, or stalls. > > Well, then the only answer for a PCI interface is Xilinx... > > Thanks for the info... > > Austin No, he stated (correctly) that the 8K series had no explicit CLKen facility. 10K has them, with a bus of up to 6 clock enables running round the IOEs. 10K parts are hardly new. The decision as to which manufacturer to use for PCI is not at all clear-cut. (but Actel's devices with a PCI core on a corner are going to be well worth a look.) I'm about to start building a slave-only PCI card (to run a dawn'o'time non-PC network to PCs, just for fun). That ought to prove things one way or the other. (Anyone out there want to trade some PCI knowlege for some ATM experience?) Steve -- Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK Desk +44 1223 578524 (Fax 578524) Group +44 1223 578518 steve@sj.co.ukArticle: 5538
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A N N O U N C E
Qualis Design Corporation is offering another session of our popular course
"High Level Design Using Verilog" at our Beaverton, Oregon, Training Center.
This course presents a comprehensive introduction to the Verilog
language while teaching you how to approach complex design tasks using
High Level Design methods. Through our advanced presentation methods,
we teach cutting-edge knowledge in a way that sticks -- graduates of the
course are immediately ready to tackle large scale Verilog-based designs
including ASICs and FPGAs.
For additional information about the material covered in this leading-edge
course, see the course description below.
This course can also be held at your facilities in a private, one-on-one
setting -- contact us for more information.
Schedule
--------
The March 1997 schedule for this class follows:
Course Title Course Date Status
-------------------------------------------------------------------
High Level Design Using Verilog: Mar 10 - Mar 14 Open
The Qualis Difference
---------------------
We know what it's like to work under the pressure of aggressive schedules and
immense technical challenges. We believe that High Level Design methods
and technology, such as HDL-based verification and synthesis, are the key
to tackling those challenges and conquering today's design problems.
Our courses can make a real difference in your day-to-day work life
by showing you the high leverage points of Verilog and High Level Design.
Here's how we do it:
-- The Qualis "Best In Class" Instructor Team draws upon the absolute best
Verilog and VHDL consultants in the industry -- our people! Your
instructor regularly tackles 500,000+ gate ASICs, and is ready to
share his in-depth knowledge with you. Synthesis, verification,
design methodology -- it's all there. You won't find instructors
of this caliber anywhere else.
-- Our courses are intense, hands-on events using the latest EDA tools
and hardware. Everything you need to learn quickly and efficiently is
provided -- you supply the brain, we'll supply everything else.
-- Our courses are like no other in the EDA industry. Engineers and
Managers who attend our courses will learn what's important and why, and
where to focus their time and resources for maximum leverage from HDLs
and design tools. And, unlike other vendor courses, our courses are
*dynamic* -- we constantly update our material with the latest in
High Level Design techniques and information, so you're assured of
learning the latest in the field.
-- Our courses are respected in the industry. We have taught our
High Level Design courses to many Fortune 500 companies and
hundreds of Engineers and Managers. Our student references attest
to the outstanding quality and real-world usefulness of our classes.
Just ask and we'll prove it.
About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of Elite Consulting and Training
Services. The company provides services to leading-edge
high technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, and Northern Telecom. Qualis' corporate
headquarters are located in Beaverton, Oregon.
Don't miss this opportunity to learn the latest in High Level Design
from the best in the industry. For course syllabi and registration
information, contact us at:
Linda Boyd, Training Registrar
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
mailto:training@qualis.com
Brief Course Description
--------------------------
High Level Design Using Verilog
Course Overview
Copyright (c) 1995, 1996, 1997 Qualis Design Corporation
"High Level Design Using Verilog" is a fast paced, five-day hands-on,
multimedia course designed to make class participants immediately productive
in a Verilog-based design environment using state-of-the-art simulation,
waveform viewing and synthesis tools.
After an introduction to Verilog, the course deviates from the
traditional bottom-up, gates-to-behavioral modeling presentation of
other Verilog courses and reverses the flow, teaching top-down design
practices, with early special emphasis on coding guidelines, efficient
testbench generation and advanced design verification techniques.
These skills are reinforced throughout the week while teaching Verilog
from a top-down perspective.
The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. All students
complete the main part of the lab and an optional part is for students who
finish early and want to learn additional material. This lab structure
caters to all student skill levels and provides excellent opportunities
to expand one's knowledge of Verilog simulation and modeling techniques.
Each day of class includes interactive lectures and several lab sessions.
Students will have access to individual Sun Sparcstations, the Verilog-XL
simulation environment, and the Synopsys DC Expert synthesis environment
for use during the laboratory sessions. The instructor presents the material
using a projection system that allows 30% more material to be presented
in a given amount of time with vivid, interest-grabbing color slides.
Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course
is available. Contact us for more information.
------------------------------------------------------------------------------
Qualis Design Corporation
8705 SW Nimbus Avenue, Suite 118
Beaverton, Oregon 97008 USA
Phone: +1-503-644-9700
FAX: +1-503-643-1583
mailto:training@qualis.com
"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.
Copyright (c) 1995, 1996, 1997, Qualis Design Corporation. All Rights Reserved.
Article: 5540Erik de Castro Lopo wrote: > I'd agree with what Robert has to say. FPGAs and CPLD are just means of > replacing 74XX series logic and small PALs (ie Lattice 22v10). > I would not agree with this statement. I worked at Fairchild in 1968 when we introduced one TTL-SSI and -MSI circuit per week. That kind of effort lasted until the early 'seventies. TTL-SSI and -MSI innovation has stagnated since that time, when many of today's designers were still in diapers. It's like saying: an automobile is nothing but a substitute for a horse-drawn carriage, or a TV is a radio with pictures. I find it flattering that designers think of logic functions in TTL-MSI terms. We must have done a good job back then, if designers, 25 years later, still think of counters as 74161s and decoders as 74138s and ALUs as 74181s. That's o.k., as long as that does not stifle the imagination. TTL circuits were defined with one overriding constraint: the 14- or 16-pin package, later stretched to 18 to 24 pins. Today, it would be silly to consider the 7490 or the -much better- 74161 as the "standard" counter. FPGAs and CPLDs offer much more exciting flexibility: wide decoding, small RAMs, abundance of flip-flops, internal busses, efficient identity comparators, novel ways to perform the multiplications needed in DSP, etc. Yes, you can use FPGAs and CPLD as TTL-equivalent "garbage collectors". But you can also use them for much more productive things Peter Alfke, Xilinx ApplicationsArticle: 5541
Bill Harris wrote:
> .....
> Lets talk about nonsense. Lets look at the Xilinx app note located at
>
> http://www.xilinx.com/partinfo/3volt.pdf
>
Obviously! If you can't get the manufacturer to guarantee
safe input currents, you can't use it.( except maybe on the bench, if
you monitor your supply voltages). Sometimes I read these app notes and
I feel like Xilinx is saying, 'yeah we know its technically illegal, but
it'll probably work, so go ahead and do it but don't tell your boss'. I
mean, if it works, why don't they guarantee it?
I find it very irritating that while they won't guarantee tracking
delays, or min delays, there are many references to 'reasonable'
tracking (70%) and min delays(20%). It is desireable to make use of
tracking, especially when confronted with interfacing to memories, and I
never quite know where the line is.
Let me give you a simple example of what I mean. You may need to
guarantee an output pulse width, say 10ns. There are 4 delays of
interest, the clkin to pin register delay for both low and high
transitions, and the clk to output delay for both types of
transitions.
clkin __/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\
clk __/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\
pulse ------\_____/-----------------------------
Without using tracking delays:
clkin->clk 7ns (use max delay )
clk ->lo 7ns (use max delay )
Tpw 10ns ( the spec )
clkin->clk 0ns (use min delay )
clk ->hi 0ns (use min delay )
----------------------------------
Total 24ns (without use of tracking)
With using tracking delays:
clkin->clk 7ns (use max delay )
clk ->lo 7ns (use max delay )
Tpw 10ns ( the spec )
clkin->clk -5ns (use max*70% delay )
clk ->hi -5ns (use max*70% delay )
----------------------------------------------
Total 14ns (with use of tracking)
There is considerable difference in the max cycle time.
_
Brad
Article: 5542One way to secure your FPGA (with Xilinx anyway) is to do a "hardwire" conversion. This is basically a mask version of the programmable product. Secure as far as external probing is concerned. For reconfigurable systems, I have seen systems where an external CPLD is used as a "dongle" for the FPGA. A unique handshake occurs each time the system boots. This stops the system being copied but does not actually secure the FPGA design. -Andrew Metcalfe, ACD Australia John A. Harding <harding@pelican.cs.ucla.edu> wrote in article <5eii65$399@pelican.cs.ucla.edu>... > > Hello- > > Are there any ways to prevent SRAM FPGAs from being > reversed engineered. Or copied. I have heard about > the approach using a battery and loading the config. > in the Factory, but what about upgrades, and reconfigurable > systems. > > It seems that many applications cannot use FPGAs because > of this reason. > > Thanks, > > John > >Article: 5543
Hi All, I would be very greatful if anybody was aware of a site on the WWW where I could find information on the market share of the major FPGA EDA vendors - in particular in relation to their synthesis tools. Thanks in advance for any help, Cheers, Phil.Article: 5544
If the application has enough volume, or security is manditory, use a hardwire after debugging the design. Austin Franklin ..darkroom@ix.netcom.com. John A. Harding <harding@pelican.cs.ucla.edu> wrote in article <5eii65$399@pelican.cs.ucla.edu>... > > Hello- > > Are there any ways to prevent SRAM FPGAs from being > reversed engineered. Or copied. I have heard about > the approach using a battery and loading the config. > in the Factory, but what about upgrades, and reconfigurable > systems. > > It seems that many applications cannot use FPGAs because > of this reason. > > Thanks, > > John > >Article: 5545
We're designing several larger XC4KE devices under XACT 5.2.1 with XABEL as
our HDL (long story; absence of timing-driven mapping is annoying, but not
terminal). Most of the designs are proceeding reasonably. One is giving us
hell.
We had gotten PPR to produce results that _almost_ met our timing constraints
several times. After complicating the timing constraints to exclude multicycle
paths, and a few design adjustments indicated by functional simulation, the
design now no longer routes.
We have tried to add placement hints in the form of "bounding boxes" (i.e.
[clb_r1c1 clb_r5c5] kinds of things where the available number of cells in the
box is about twice what is needed), and more carefully placing bussed items,
but PPR is producing more and more unroutes with each run.
Both placement and routing efforts are maxed. The design used to complete in
about 6 hours, but now seems to want to go for days. As part of trying to
diagnose this problem, we'd been waiting till the ppr.log file indicated
placement was complete and then issuing a kill -2 to review the placement, but
have begun to just set route=false.
A symptom seems to be that when the solutions were _almost_ meeting timing,
the occupied CLBs reported by Floorplanner seemed to be evenly distributed
across the device (as were the unoccupied CLBs), but now PPR keeps packing the
CLBs in a tight knot near the center of the device, so it runs out of routing
channels. It also used to sequence bus bits pretty well, but now scrambles
them hopelessly (so we now explicitly place key register bits as anchors).
The hotline suggested that we noplace every third row or so to force better
distribution of CLBs. This sounds like a hack, and we didn't need it before
(nor on the other designs that use timing constraints). Has anyone else seen
this kind of behaviour, or have any PPR or constraint tips that might get us
out of this hole? Can anyone provide a better description of how PPR works,
what it looks for, what it tries, to give us some insight on how to work
around it? Any help is appreciated.
--
---------------------------------
Tom Vrankar
twv@ici.net
http://www.ici.net/customers/twv/
Rhode Island, USA
Article: 5546"Iswada Osumundli" <#io@galofzu.net#> wrote: >The Lattice parts do not provide enough resources to do a PCI interface, >except a simple target. If you want burst target or master functionality, >the Xilinx parts are the only ones that can do it. > IYHBO (In Your Heavily Biassed Opinion) ;-)Article: 5547
Kevin D. Drucker wrote: > > Sorry about the psuedo-spam... > > I am looking for a tool to assist me in documenting state machines. > Something similar to Rational Rose (which is a C++ tool), but > specifically geard towards digital logic design. It would be nice if it > allowed you to show the diagrams either as a mealy or moore type > machine. We've a tool called SME (State Machine Editor). It allows the drawing of state-machines, but doesn't care about moore/mealy. Instead you can specify for each output whether it should change whenever the input changes or only at the clock edge. The diagrams look like program flowcharts, consisting of state/switch/condi- tion/assignment symbols. Variables that keep their values over several clocks exist as well. The tool can generate VHDL and Verilog (synthesizeable). It is available vor HPUX and Sunos/Solaris (sparc). The tool is usually not used to document state machines afterwards but to design them in the first place. Basically, our ASIC-designers use it as a tool for implementing program flowcharts. > Any one know of such a tool? If there is a shareware program out there > that'd be great. Windoze 95 or HP-UX... Sorry, it costs money. VolkerArticle: 5548
Help, We are trying to convert a AHDL file into an ABEL file. The problems that we have, have to do with the default section of the file and how it is defined during the state transitions. He defaults a signal to VCC (all of the circuit was designed to be active low). Then during the first state he assigns a logic 1 to that signal defined in the default section. Then for the next few states he does not mention the state of that output, so we assume the output will take on that default (VCC or unchanged). After that he will again assign that signal to a logic level 1. From what we can gather, this signal will never change, hence has no real need to be a part of this state machine. Are we right ? From some of the examples of state machines in AHDL and on a handout we had on AHDL basics tells us that we are right, but it does seem strange that the programmer did this. We want to make sure who is right. The state machine has 82 states, and we don't want to guess. (Note: We can not get in contact with the orginal programmer) Also while I am at it, we have another problem from this same state machine. Has has named two state the same names, but assigned different outputs in the two states (i.e. s11 has one set of outputs and s11 has another set of outputs). I would say this would be a problem, but to get to and from each of those states has nothing to do with inputs, hence I would guess this would not effect the status of the state machine. Does anybody know for sure ? Thank you for your time, Jonathan Montag, SSD RaytheonArticle: 5549
Use the AHDL FOR/GENERATE statement. Woody ----------------------------------- Graham Seaman wrote: > > Hi all, > > I'm trying to implement a cellular structure using Altera's > MaxPlus software; that is, I have a simple basic 'cell' of > about 10 gates which I need to replicate many times across > the FPGA (connections are mostly NEWS style; ie. to 4 nearest > neighbours of each cell). > If I was doing this in VHDL, I'd just use the 'generate' > statement in a nested for loop. But I don't have VHDL, only > AHDL, and can't work out a good way of doing this. Or am > I better off sticking to schematic entry (lots of cut-and-paste)? > > Anyone got any ideas? > Thanks for any help > Graham >
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