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We are a specialist agency based in the UK seeking experienced hardware / software / firmware engineers. The contracts are mainly UK based although some are in Europe and will last 6 - 18 mths. Please see our web page http://www.cliveden.co.uk or email us for more details. Regards, Malcolm Burgess.Article: 6326
We are a specialist agency based in the UK seeking experienced hardware / software / firmware engineers. The contracts are mainly UK based although some are in Europe and will last 6 - 18 mths. Please see our web page http://www.cliveden.co.uk or email us for more details. Regards, Malcolm Burgess.Article: 6327
Article: 6328
I want FPGA defintion. I will make FPGA board for image processing.Article: 6329
What's the FPGA defintion? I want FPGA defintion. I will make FPGA board for image processing.Article: 6330
lee youngtae wrote: > > I want FPGA defintion. > I will make FPGA board for image processing. A Field programmable Gate Array (FPGA) is an array of small logic blocks. The logic function of each block (aka cell) and the interconnect between cells is determined by a configuration "program" loaded by the user. Depending on the family of FPGA the configuration program may be volatile (stored in static registers) or non-volatile (stored in EEPROM cells, fuses or antifuses). The large array of user defined cells, can be programmed to do fairly complex logic functions. The arrays range from 8x8 cells for the smallest ones to 80x80 cells and larger. A sixteen bit adder can be made using 8 cells in many devices. The individual logic cells vary from family to family. The so called coarse grain cells are typically small look-up tables with four or five bit 'addresses' and one bit outputs followed by a flip flop. Multiplexors are used to bypass the flip-flop or invoke oather features. Other architectures use multiplexers and constants to generate the logic function at each cell. The fine grain FPGAs typically only have 2 or 3 inputs to each cell, but have more cells per unit area. Interconnect between cells is a combination of metal routes and switches consisting of fuses, antifuses, multiplexers or pass transistors. The FPGA allows the user to design custom logic using a generic chip. Therefore the NRE associated with custom silicon is avoided. SRAM based FPGAs (these are the volatile ones) can be reconfigured without limits on the number of times it is done. This makes these devices useful for applications where changing the logic circuit when part of it is not being used. For a simplistic example, consider a telephone implemented in a integrated circuit (thanks John Watson). Using conventional design practices, the chip would have separate logic for the ringer, dialer and voice processing. However, only one of these sections is ever used at any particular time. By using reconfigurable logic, the ringer circuit could be loaded when the phone is on the hook. When the phone is picked up we can load in the dialer circuit in place of the ringer circuit, USING THE SAME PHYSICAL LOGIC. Similarly, when voice is being used, the logic cells are reprogrammed for voice communications. In this way, the actual chip has fewer gates than a solution that has all of the logic present all of the time. In the case of your image processor, The FPGA would be programmed with hardware designed to efficiently process your particular algorithm. Of course, this is a hardware design rather than the software design that most DSP folks are familiar with. The advantage of the hardware design is that you can use many gates in parallel to perform say, multiple adds in the same clock cycle. Contrast that with the DSP microprocessor where each instruction cycle can only perform one fairly simple operation. It should be obvious that by being able to do many operations at once, there is a substantial acceleration of the process. Finally, before going off and building an "FPGA board for image processing" it is import that you understand what it is you are going to accomplish, and that you have an idea of how it is going to be implemented in the FPGA. I might suggest you look at some of the FPGA boards intended for reconfigurable computing before rolling your own. Some commercial vendors are: Annapolis Micro, Giga-Ops, Virtual Computer Corp. These guys have invested alot of effort into making the FPGA more accessible to people not familiar with hardware design. Their offerings include various software tools and macros to help arrive at efficient designs. There are also people who have make TIM boards with FPGAs that ae intended to fit onto DSP base boards as co-processors.Article: 6331
On Wed, 14 May 1997, Mark Champion wrote: > On the other hand, ASIC designers will commonly use Verilog. If you > do an ASIC, most of the ASIC vendors will require Verilog XL sign off. > That pretty much means you will have to buy Verilog XL from Cadence - > about $20-25K. I'm not sure what VHDL ASIC designers do for signoff. > > mchampion@Xbigfoot.com > > Mark Champion - Leave out the "X" to send me email > > Waht do you mean by signoff, anyways? -- Amr G. WassalArticle: 6332
Umesh Nair wrote: > > Can anybody send me the diagram showing how the outputs of decoder are > connected to the output of the chip? > The outputs are connected to the routing structure, so you can connect them anywhere you want. Half of the inputs come from the device pins, the other half come from internal sources. It is a little bit more flexible and general-purpose than you seem to think. Peter Alfke, Xilinx ApplicationsArticle: 6333
I thought the readers of this newsgroup might want to see the following article from the June97 issue of Scientific American. It's kind of nice to see FPGAs (and associated researchers) getting some recognition in the mainstream press. My guess is that this won't be the last article. Notice that they call it "configurable computing". http://www.sciam.com/0697issue/0697villasenor.html I'm interested in any comments about the article. - BradArticle: 6334
>>>>> "Brad" == Brad Taylor <blt@emf.net> writes:
Brad> I thought the readers of this newsgroup might want to see the
Brad> following article from the June97 issue of Scientific American.
Brad> It's kind of nice to see FPGAs (and associated researchers) getting
Brad> some recognition in the mainstream press. My guess is that this
Brad> won't be the last article. Notice that they call it "configurable
Brad> computing".
That's interesting, indeed. For those who might be interested in
"Re"-configurable computing (the next generation, maybe?) I suggest to have a
look at
http://www.comlab.ox.ac.uk/oucl/hwcomp.html
(To pick just one random URL :)
Brad> http://www.sciam.com/0697issue/0697villasenor.html
Brad> I'm interested in any comments about the article. - Brad
I haven't read it thoroughly yet, but it seems that the authors completely
forget about what is going on in Europe (see the above URL)
Cheers,
Matthias
--
Matthias Sauer Tel +44-1865-283549
Oxford University Computing Laboratory Fax +44-1865-273839
Wolfson Bldg., Parks Road email masa@comlab.ox.ac.uk
Oxford OX1 3QD, U.K.
URL: http://www.comlab.ox.ac.uk/oucl/users/matthias.sauer/
Article: 6335Brad Taylor wrote: > I thought the readers of this newsgroup might want to see the following > article from the June97 issue of Scientific American. > It's kind of nice to see FPGAs (and associated researchers) getting some > recognition in the mainstream press. My guess is that this won't be the > last article. Notice that they call it "configurable computing". > > http://www.sciam.com/0697issue/0697villasenor.html > > I'm interested in any comments about the article. Nice article. Thanks for the pointer. Intriguing that there was no mention of the Hardware Compilation team at Oxford University, UK (see http://www.comlab.ox.ac.uk/oucl/hwcomp.html ). For several years they have been developing both the hardware and design software of reconfigurable computing engines. On Wednesday May 14, Ian Page presented a paper on this subject at the UK's Annual Advanced PLD & FPGA Day (see http://www.pld97.co.uk ) Full list of his papers is at http://www.comlab.ox.ac.uk/oucl/users/ian.page/papers.html A point made during the presentation was that "programmers are easier to hire and train than circuit designers" - thus giving substantial commercial justification to the project. Of course, someone has to design the platform for the programmers to program... Which brings in a point made by another speaker that in many FPGA systems, overall performance was now being limited by PCB design aspects rather than the internal silicon. Tim Forcer tmf@ecs.soton.ac.uk Department of Electronics & Computer Science The University of Southampton, UK The University is not responsible for my opinionsArticle: 6336
In article <3366edb8.1614528@news.rt66.com>, mma@rt66.com (Mark Aaldering) says:
>
>On 29 Apr 1997 11:35:03 GMT, sloman@sci.kun.nl (Bill Sloman) wrote:
>
>>I've got to fit 8 clock extractors/resynchronisers into one or two SMD
>>PLDs - each has two inputs, three outputs and either three or four
>>flip-flops depending on what the PLD can be made to do. The system is
>>clocked at 6MHz.
>>
>>But my biggest constraint is that I've only got 50mA for the PLD/PLDs.
<snip>
>By my back of the envelope calculation, you need 16 inputs, 24
>outputs, and 32 Macrocells, and of course low power. This should
>easliy fit in a CoolRunner Fast Zero Power CPLD - My rough estimate is
>that total power consumed in a 5V PZ5064 would definitely be less than
>10mA, probably in the neighborhood of 4mA. This device is available in
>a 7.5nS Tpd at the power stated above. 3V versions also shipping. The
>rational behind a 64 Macrocell suggestion is that at 40 I/Os, you're
>just above the 32 Macrocell devices I/O capability - of course you
>could partition this into two 32's...
>
>For more info, datasheets, etc refer to our website at
>
> www.coolpld.com
Well, when I tried to fit it into two PZ5032's, the XPLA software pointed
out that the PZ5032 has only got two clock networks, and thus won't
support four independent clocks. I hadn't picked this up from my
reading of the data sheet. I'd already had to reject the AMD MACH110
because of essentially the same problem, and I thought I'd read the
Philips data sheet very carefully.
The PZ5064 apparently will support 4 independent clocks, so I hope it
really is obtainable.
Bill Sloman (sloman@sci.kun.nl) | Precision analog design
TZ/Electronics, Science Faculty, | Fast analog design and layout
Nijmegen University, The Netherlands | Very fast digital design/layout
| e-mail for rates and conditions.
Article: 6337In article <3378D8C7.2221@vtechcorp.com>, kev@vtechcorp.com says... > Hi, > The company that I work for is in the process of deciding on a new > simulation tool. Right now we use a schematic entry/ABEL-HDL tool, but > we want to upgrade to a VHDL or Verilog. I have been left with the task > of deciding which is better. I could use some input on the pros and > cons of each, maybe listing some of the major benefits or drawbacks. > Also what seems to be the most widely used. Any help I can get would be > greatly appreciated. Please reply to me as well as the newsgroup, and > no spam please. Thanks > There's some good high-level commentary on VHDL vs. Verilog and on PLD design tools in a recent issue of EE Times. Go to the EE Times Web site (http://techweb.cmp.com/eet/) and search on "Dini". -- Terry Ragsdale J.P. Morgan Securities ragsdale_terry@jpmorgan.comArticle: 6338
I am looking for the file format for the '.bit' file produced from the Xilinx makebit program. The documentation describes the configuration stream format, but not this file. Thanks in advance Archer Lawrence Sr. Engineer Tanisys TechnologiesArticle: 6339
Amr G. Wassal wrote: > > On Wed, 14 May 1997, Mark Champion wrote: > > > On the other hand, ASIC designers will commonly use Verilog. If you > > do an ASIC, most of the ASIC vendors will require Verilog XL sign off. > > That pretty much means you will have to buy Verilog XL from Cadence - > > about $20-25K. I'm not sure what VHDL ASIC designers do for signoff. > > > > mchampion@Xbigfoot.com > > > > Mark Champion - Leave out the "X" to send me email > > > > > > Waht do you mean by signoff, anyways? It's when you tell the IC-Company that the code you produced is the one the ASIC should be compatible to. Then the IC-Company starts to produce ASICs (yes, there are risc-prods...) and when the ASIC does not do what you want, you have to prove that the ASIC is not compatible to the code you provided. But now I'm interested too. How to sign off a VHDL-project? VolkerArticle: 6340
There is information on the Xilinx solution on their web page at 'http://www.xilinx.com/products/logicore/lounge/pcim/pcim.htm'. I believe that it is still a VHDL instantiation of their XNF netlist. They do this because there are some critical timing and placement parameters that cannot yet be described from VHDL for the Xilinx tools. There is an Acrobat application also listed on the same page for the HDL design flow. They also now have a web-base "core configuration" tool. There is a demo copy at: 'http://www.xilinx.com/products/logicore/cg_intro.htm'. The problems and how to solve them are long and complex. I would recommend looking at the User Guide at 'http://www.xilinx.com/products/logicore/lounge/pcim/pcimrequser.htm'. They ask for your name and address but I think you can get access nearly immediately. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Holger Venus <Holger.Venus@dlr.de> wrote in article <337AB98C.28EF@dlr.de>... | Hi | | did anybody successfully perform a VHDL PCI bus implementation in a FPGA | (XILINX, ACTEL, | QUICKLOGIC,..)? | What were the main problems and how did you solve them? | How did you test your hardware (PCI analyzer, logic analyzer, only | simulation,..)? | | Thankx for any reply. | | Best regards | | Holger Venus | | German Aerospace Establishment | Institute of Space Sensor Technology | Rudower Chaussee 5 | 12489 Berlin | Germany | | Telephone: +49-30-67055-556 | Telefax : +49-30-67055-532 | e-mail : Holger.Venus@dlr.de |Article: 6341
Just FYI, there are many more references on reconfigurable computing listed on the Programmable Logic Jump Station at: 'http://www.optimagic.com/research.html' -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Brad Taylor <blt@emf.net> wrote in article <337BE859.56B9@emf.net>... | I thought the readers of this newsgroup might want to see the following | article from the June97 issue of Scientific American. | It's kind of nice to see FPGAs (and associated researchers) getting some | recognition in the mainstream press. My guess is that this won't be the | last article. Notice that they call it "configurable computing". | | http://www.sciam.com/0697issue/0697villasenor.html | | I'm interested in any comments about the article. | - | Brad |Article: 6342
On Thu, 15 May 1997 16:57:33 GMT, "Amr G. Wassal" <wassal@vlsi.uwaterloo.ca> wrote: >On Wed, 14 May 1997, Mark Champion wrote: > >> On the other hand, ASIC designers will commonly use Verilog. If you >> do an ASIC, most of the ASIC vendors will require Verilog XL sign off. >> That pretty much means you will have to buy Verilog XL from Cadence - >> about $20-25K. I'm not sure what VHDL ASIC designers do for signoff. >> >> mchampion@Xbigfoot.com >> >> Mark Champion - Leave out the "X" to send me email >> >> > >Waht do you mean by signoff, anyways? >-- >Amr G. Wassal > When you design an ASIC, you write separate Verilog code to test the design before it is committed to silicon. This is simulation. It requires the use of a simulator. Most ASIC vendors require this simulator to be Cadence's Verilog XL. In other words, the vendor will "sign off" or guarantee the design based upon a sucessful Verilog XL simulation. mchampion@Xbigfoot.com Mark Champion - Leave out the "X" to send me emailArticle: 6343
If you are trying for best pin-to-pin performance through the wide decoders, be sure to: * Place the output pad on the same edge as the wide decoder * Use both pull-up resistors, if you are using a full edge * Set the output pad to FAST The output of the decoder can actually connect to just about anything else in device. However, it uses standard interconnect to do this, so your performance may suffer if you have to go far from the edge. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Umesh Nair <nair@ee.tamu.edu> wrote in article <Pine.SOL.3.96.970514190907.21698A-100000@mimolette.tamu.edu>... | hi | Can anybody send me the diagram showing how the outputs of decoder are | connected to the output of the chip? | | The data book shows only the block diagram of inputs of decoder connected. | | thanks in advance | umesh nair | |Article: 6344
Bill Sloman wrote: > > In article <3366edb8.1614528@news.rt66.com>, mma@rt66.com (Mark Aaldering) says: > > > >On 29 Apr 1997 11:35:03 GMT, sloman@sci.kun.nl (Bill Sloman) wrote: > > > >>I've got to fit 8 clock extractors/resynchronisers into one or two SMD > >>PLDs - each has two inputs, three outputs and either three or four > >>flip-flops depending on what the PLD can be made to do. The system is > >>clocked at 6MHz. > >> > >>But my biggest constraint is that I've only got 50mA for the PLD/PLDs. > An XC3020 would do the job easily, and well within your power budget of 250 mW ( I assume it's a 5-V application ) with lots of logic left for potentially other purposes. Don't use the global clock routing, but rather normal vertical Longlines. Metastability info is in the data book. Of course, you have to store the configuration either in an SPROM or in another interface. That's why this solution is most appealing when you use the FPGA to suck up additional logic. But if you are in a power bind... Both FPGA and SPROM come in tiny SMD packages. Peter Alfke, Xilinx ApplicationsArticle: 6345
I guess it depends on your interpretation of the word 'cheap'. Here are a few options: For the mid-range Xilinx FPGA and CPLD devices, see the APS-X84-FB1 system for about $650 (http://www.erols.com/aaps/X84price.htm). Includes schematic capture, simulation. For Cypress, you can get VHDL support and simulation for between $100 and $200 (http://www.cypress.com/cypress/warp2/page2.htm) There are various vendors that have "free" software. These are either older software or limited evaluation versions. Evaluation Software: Xilinx (http://www.xilinx.com/products/software/xacteval.htm) Xilinx CPLD (http://www.xilinx.com/products/software/abeleval.htm) Philips (http://www.coolpld.com/cdrom-offer.html) Older Revisions Vantis MACH-XL (ftp://ftp.vantis.com/pub/software/machxl/machxl_2.1) Vantis PALASM (ftp://ftp.vantis.com/pub/software/palasm/) These are only a few of the options that I've come across. If you are interested in a particular vendor, then I would recommend asking them what they can offer. Many have demo or evaluation disks that aren't widely advertised. There is also a host of software available through major universities (http://www.optimagic.com/software.html#UniLanguages). For a comprehensive list of software available for programmable logic design, see 'http://www.optimagic.com/software.html'. If you are a student at a university, then the various vendors usually have some sort of a university program. You'll need to do some checking around. For example, Xilinx and Prentice-Hall announced a new student book/software package (http://www.xilinx.com/prs_rls/univers.htm). -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Christos Dimitrakakis <mbge4cd1@afs.mcc.ac.uk> wrote in article <33785149.62F8@afs.mcc.ac.uk>... | Is there a cheap way to develop for FPGAs, suitable for the enthusiast? | | -- | Christos Dimitrakakis | --------------------- | mailto:mbge4cd1@fs4.eng.man.ac.uk | mailto:mbge4cd1@afs.mcc.ac.uk | http://www.man.ac.uk/~mbge4cd1 |Article: 6346
Xilinx Seminars In early June ( late May in California ) Xilinx goes on the road and gives 60 all-day seminars, with an emphasis on new devices and new software. If you are interested, just click on: http://www.xilinx.com/seminar.htm Peter Alfke, Xilinx Applications, off to Europe to give nine of these seminars.Article: 6347
Robert Trent wrote: > > In my latest Xlininx design, I used X-BLOX libraries and have been > really impressed by how much time it has saved, relative to my previous > FPGA schematic capture for Xilinx and Actel. It also dramatically > improves schematic readability and flexibility. > > So now, with the new M1 Xilinx development system, I understand X-BLOX > is being dropped! Anyone know why? Anyone else think X-BLOX is a good > thing? > > Robert.I've been using XBLOX for almost a year and found it to be a great concept that usually works well in practice. The problem is, a few months ago I found a weird bug that sometimes occured in some designs, when I ran XBLOX (in either fncsim8 or xmake): XBLXGS: ERROR: Bad status 79501083 from ddp__create_sheet. Not only does this error not really TELL me anything, but the Xilinx support group doesn't have any idea what the real problem is, either. Their 'solution' is for the user to methodically go through his design and replace XBLOX-containing components with dummy components, and rerun XBLOX, until you've isolated the offending parts. Presumably, you are then supposed to replace those bad XBLOX components with regular unified library components or synthesis-based components. Big cost in my time! Big pain in my @#$%#*@$! What is most offensive about this is that when I first encountered the problem, I went ahead with the 'solution' described above, but I was told that Xilinx was working on a REAL solution. So, I foolishly went further with some more XBLOX designs, only to encounter the problem again with a different XBLOX component ..... except now I've discovered that Xilinx has abandoned all effort at solving this problem, and as you've discovered, they are abandoning XBLOX altogether. Perhaps I was somewhat foolish to go on with more XBLOX design after the first encounter with this problem, but (a) I thought I'd isolated the bad component and (b) Xilinx led me to believe that a REAL solution was imminent. Nevertheless, Xilinx deserves some blame for not being up front with their customers. I think XBLOX (Xilinx' LPM) is/was a great bridge between traditional schematic designing and total HDL/Synthesis-based designing. I don't know why Xilinx is dropping it, because most designers haven't crossed that bridge yet! Bill Lenihan Hughes Aircraft Co. wlenihan@ccgate.hac.comArticle: 6348
Anyone with some advice about using leonardo? Any pros/cons regarding this development software ? thanks +_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_ Name: Daniel Roganti Email work : daniel@betronic.nl Email home : ragman@euronet.nl Smail: Oud Wulvenlaan 35-2, 3523XS Utrecht, Netherlands,Europe WWW: http://www.euronet.nl/users/ragman Back home: Margate, Florida Hometown : Elmont, New York ...exploring cyberspace before it runs out of space... +_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_+_Article: 6349
Does anyone know if I can use xilinx xblox with orcad capture ver 7.00 ? It seems that only Orcad Express can do the job but I am not sure . Has anyone had any experience with that ? please help Zbigniew Sobota Igt Australia
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Compare FPGA features and resources
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