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Hi A couple of months or so ago there was some discussion in this newsgroup about whether a UART could be implemented in programmable logic. Answer was that it can be and has been. I'm interested in comparing the number of PLD macrocells used by an RS232 circuit and the number used by a circuit implementing the IEEE 1355 protocol, which I know fits a Lattice 1016 with 64 macrocells, with just a few spare. Would any of the RS232 implementors have figures for macrocells? And of course if the function provided by the circuit is less than that of a full UART, could they say how much of the circuit is implemented by those macrocells? Many thanks Paul -- Paul Walker Editor of 1355 Association 4Links phone/fax paul@walker.demon.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.walker.demon.co.uk Milton Keynes MK8 8NS, UK 566253Article: 6301
Kate Meilicke wrote: > > Unfortunatly, in the Pre-Release software, there are several things that > don't work in the UCF file but they do work in the PCF file. > Configuring PAR is one of the things that I think works if inputted > directly into the PCF file. M1.2 is shipping this week so you should > see it soon. Some people received it today. I haven't seen the release yet either... but my local FAEs have also reported that it is shipping this week... I solved my UCF problem the hard way... I got the FF into the desired CLB easily with the following line. INST "*U1/U2/WEO*" LOC = "CLB_R27C36" The *s insure that if the synthesizers prepend or append strings I still get the flop I want. THe trick is to always name things with enough of a unique string so you can do this. To put the gate I wanted into this same clb, I had to create a level of heirarchy with just the gate in it and NOOPTed the gate so the heirachy remained in the XNF file. I then manually edited the XNF file (which is why i LOVE ascii files like XNF and HATE the binary NGO/NCD files!) and added an FMAP with a LOC parameter on it to place the gate into the CLB_C27R36. This ends up pretty much using up the CLB and MAP tends not to put anything else in it. Why do we always have to spend our creative energies getting around limitations in the tools? UGH.. I've been pretty successful getting timing thru the UCF file. TIMESPEC = "TSFFs_to_bus" = FROM : FFS : TO : PADS(DATA<0>:DATA<1>:...) ; works pretty well. also NET "*SIGNAL_NAME*" MAXDELAY = 7 ns; works to give some priotity in critical signals. -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable VHDL and Verilog Cores 20 Trafalgar Sq. #443 http://www.vautomation.com Nashua NH 03063 (603) 882-2282 FAX:882-1587Article: 6302
Kristopher Miller (millerkl@bucknell.edu) wrote: : Hi all! We are frantically trying to design a microcontroller in a : masochistic attempt to expose ourselves to HDL's and FPGA's. : ..[ deleted ].. : We put a little ASCII drawing of the particular problem we have. This : question is specifically geared towards the HDL called PLDasm and the : EPX780 FPGA. However, this question may apply to all HDLs. I don't think you chose the right device and the right language: a) EPX780 is more a CPLD with big PAL-like blocks and global routing than an FPGA; b) EPX780 is discontinued by its manufacturer (Altera); c) PLDasm is not much of an HDL - it is just an enhanced PALASM; Probably, the only advantage of your choice is that you can use the free software package (PLDSHELL). : : ______ : |\ | | : INPUT ----| >----*--------|D Q|------------ : |/ | | A | : | | |______| : | | : | | : \control | control : | | : | ______ | : | | | |\ : | |D Q|-----| >----| : | | B | |/ | : | |______| | : | | : |______________________________| : We want to connect two signals to the input of register A. The signals : are tristated to prevent contesting. The two statements we used to : connect the registers are: : A := INPUT.io : A := B.io : with tristating equations: : B.trst = control : A.trst = \control Without getting into details of PldASM I can tell you that your approach requires two separate pins in EPX880. It does not have internal tristate resources - you can only tristate an output buffer. Besides, EPX880 does not provide separate tristate controls for each pin so your design will waste resources rather than save them. : The .io extension refers to feedback taken after the tristate buffer. : The error that this produces is "Multiple definitions for A". We can : circumvent this using a combinational equation instead of tristate: : A := INPUT * \control + B * control This will work much better.Article: 6303
Kristopher Miller wrote:
>
> We put a little ASCII drawing of the particular problem we have. This
> question is specifically geared towards the HDL called PLDasm and the
^^^^^^
> EPX780 FPGA. However, this question may apply to all HDLs.
^^^^^^
>
I think you answered your own question right there.
It took all of about 30 seconds to find an online EPX780
application note, and a PLDasm manual. Try www.altavista.digital.com.
[...]
>
> We would appreciate any advice you might have for us. Thank you.
>
Learn to use the resources that are available. Two years from now,
how you learn is going to matter a whole lot more than what you know.
> Kristopher Miller millerkl@bucknell.edu
> Bucknell University
> Lewisburg, PA 17837-2082
--
Best Regards,
Jeff Buckles
NEC Electronics Inc.
Portland ASIC Design Center
(503) 526-6679
jeffb @ el.nec.com
Article: 6304Does anyone have design experience using Gatefield ProASIC family design tools? VHDL->Synopsys->Gatefield->Quickhdl ?Article: 6305
In article <5km8gv$j12@ms.mimos.my>, mazlaini@ms.mimos.my says... > >Does anybody know what are the advantages/disadvantages for chips that were designed for target process CMOS or BiCMOS. > >Design engineers widely understand that CMOS consumes less power while BiCMOS >eats lots of power but the trade off is that you get extremely high unity-gain >bandwidths. > >Are there any convincing advantages/disadvantages on CMOS/BiCMOS? >From a design point of view, what platform should a designer target his/her >design between CMOS and BiCMOS to get the most cost effective chip out of the >two processes. > > > >******************************************************************** >Please visit : http://www.jaring.my/mimos/bi/rd/icdc/icdcprof.html > >******************************************************************* If your talking about analog, bipolar differential inputs have lower volltage offsets. In general bipolar transistors have better matching charactoristics. CMOS output stages are better for "rail to rail" operation and CMOS inputs have lower input bias currents. It just depends on what your trying to achieve. DaveArticle: 6306
Is there a cheap way to develop for FPGAs, suitable for the enthusiast? -- Christos Dimitrakakis --------------------- mailto:mbge4cd1@fs4.eng.man.ac.uk mailto:mbge4cd1@afs.mcc.ac.uk http://www.man.ac.uk/~mbge4cd1Article: 6307
In article <33785149.62F8@afs.mcc.ac.uk>, Christos Dimitrakakis <mbge4cd1@afs.mcc.ac.uk> writes >Is there a cheap way to develop for FPGAs, suitable for the enthusiast? > I'm playing with the free ETH Zurich Trianus software for the Xilinx XC6216 FPGA. Details are on my web page. I think that this is the cheapest way into them, although you'll have to build your own hardware. Leon -- Leon Heller Amateur radio callsign: G1HSM Email: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk Tel: +44 (0) 118 947 1424 (home) +44 (0) 1344 385556 (work)Article: 6308
Hi, The company that I work for is in the process of deciding on a new simulation tool. Right now we use a schematic entry/ABEL-HDL tool, but we want to upgrade to a VHDL or Verilog. I have been left with the task of deciding which is better. I could use some input on the pros and cons of each, maybe listing some of the major benefits or drawbacks. Also what seems to be the most widely used. Any help I can get would be greatly appreciated. Please reply to me as well as the newsgroup, and no spam please. ThanksArticle: 6309
Christos Dimitrakakis <mbge4cd1@afs.mcc.ac.uk> wrote in article <33785149.62F8@afs.mcc.ac.uk>... > Is there a cheap way to develop for FPGAs, suitable for the enthusiast? This week we had some great news, which I'm surprised no one else has commented on. Xilinx and Prentice Hall have announced they will offer an inexpensive student edition of Xilinx tools. (Your email address seems academic.) See http://www.xilinx.com/prs_rls/univers.htm. Jan.Article: 6310
Dear all, I am working on a design for a 4020 part containing two 640 bit shift registers implemented by using ram16x1s instatied VHDL components. So far ppr seems to place and route the design pretty well, however I suspect that I could achieve much better results by floorplanning the memory banks with fplan before running ppr. The problem is that the number of cells to be manually placed is large, so I'm wondering if there is a way to build a sort of RPM macro block directly in VHDL, that could be eventually reused in other designs. It seems that the new M1 software has a tool called Logi-BLOX that just solves this problem. Is there any way to accomplish this also with synopsys 3.5a, the XSI and XACT? Thanks in advance, -Arrigo -- Arrigo Benedetti e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 phone: (818) 395-3695 Pasadena, CA 91125 fax: (818) 795-8649Article: 6311
Hi altera readers.
I'm trying to work with ByteBlaster with no success.
I have NT4 on my computer, MAX+2 ver7.2, added the 7_1pch3.exe -o,
and nothing works.
After declaring the device (EPM9560RC240), I've tried to change the
programmer hardware setup to byteblaster, and then all the option
disapeare. What am I doing wrong????
Thanx,
Gabby.
--
========================================================================
Gabby Shpirer | e-mail: gabby@isv.dec.com
Digital Technical Center | phone : 972-2-5892640
Har hotzvim, Jerusalem | fax : 972-2-5892600
91450 Israel |
========================================================================
Article: 6312Hello everyone, I'm thinking about buying the Actel "Designer Series" FPGA design package. Can anyone provide any comments or details of practical experience with this? I have prior experience with CUPL up to moderately complex devices (Atmel ATV2500) but I'll be a newbie to very large FPGAa and also to VHDL. The intended first application is _very_ register-rich, hence the choice of Actel. Thanks in advance, Richard ------------Richard Dungan------------- Radix Electronic Designs, Orpington, UK Email> Richard.Radix@BTinternet.com ---------------------------------------Article: 6313
On Tue, 13 May 1997 17:10:31 -0400, "Karl E. Vinacco" <kev@vtechcorp.com> wrote: >Hi, > The company that I work for is in the process of deciding on a new >simulation tool. Right now we use a schematic entry/ABEL-HDL tool, but >we want to upgrade to a VHDL or Verilog. I have been left with the task >of deciding which is better. I could use some input on the pros and >cons of each, maybe listing some of the major benefits or drawbacks. >Also what seems to be the most widely used. Any help I can get would be >greatly appreciated. Please reply to me as well as the newsgroup, and >no spam please. Thanks I don't consider myself an expert - just a novice with an opinion. Most people consider the two HDLs to be equivalent in functionality. In my limited experience, I have seen that VHDL is more common when targeting FPGAs and Verilog is more common when targeting ASICs. For example, if you use Xilinx, you can get a complete development system for Win95 based on VHDL for very little $$$. They can provide some Verilog support but it starts costing more $$$. On the other hand, ASIC designers will commonly use Verilog. If you do an ASIC, most of the ASIC vendors will require Verilog XL sign off. That pretty much means you will have to buy Verilog XL from Cadence - about $20-25K. I'm not sure what VHDL ASIC designers do for signoff. mchampion@Xbigfoot.com Mark Champion - Leave out the "X" to send me emailArticle: 6314
Richard Dungan wrote: > > Hello everyone, > > I'm thinking about buying the Actel "Designer Series" FPGA design > package.. > The intended first application is _very_ register-rich, hence the > choice of Actel. I do not think that the words "register-rich" and "Actel" go together. Look-up table based FPGAs are register-rich. For Xilinx FPGA devices you find the number of flip-flops by dividing the specified gate count by ten. For example, an XC4010E has 1,120 flip-flops, and if you build long shift registers, you can hide them in the RAMs and get a ten times higher density of "virtual flip-flops". Sorry for this commercial interruption, but facts are facts. Peter Alfke, Xilinx Applications ----Article: 6315
It's a business decision. Look at every factor EXCEPT language features. Their value can only be evaluated subjectively and is the source of much religious conflicts. And the feature that makes a language better for your next project may not be that important for the next one. Here are a few things to look at, in no particular order (except the order in which they came to mind): - Cost of tools - Relationship with tool vendor - Integration of HDL tool with existing tool set - Knowledge and experience of engineers - Engineer's subjective preference - Support from target and potential FPGA/ASIC vendors - Quality of models from vendor - Relationship with FPGA/ASIC vendor - Availability of 3rd party models for board/system simulation - Availability of IP blocks - Ease of use - Sign-off kit requirements - Customer requirements (if they purchase the final design) Better yet: edge your bet by picking bilingual tools! If you pick Verilog, I personally think Verilint is a must have. -- Janick Bergeron Qualis Design Corporation Ph.: (503) 350-3663 Director of PO Box 4444 Fax: (503) 643-1583 Technology Beaverton, OR, USA, 97075-4444 janick@qualis.com VHDL - Verilog - Synthesis - Modelling - Verification - TrainingArticle: 6316
Arrigo, The XACT program is called MEMGEN. Go the Xilinx home page, http://www.xilinx.com and click on Answers Search. Search for MEMGEN and SYNOPSYS. You should get two results. The first is HDL Synthesis for FPGAs. This is a great book but very large to download. The second is an Apps note - XAPP057: Using Select-RAM Memory in XC4000 Series FPGAS. In this Apps note there is a section on how to use it in HDL land. For Synopsys, you should put a dont_touch on the instantiated RAM module. KateArticle: 6317
kevintsmith@compuserve.com wrote: Don't believe any vendor on FPGA gates..... You will be better served by counting Flip-flops, look-up tables( or their equivalent), I/Os, and RAM bits ( If applicable ). Gate counting is only good between FGPAs and/or CPLDs from the same vendor. Like XC4000 vs XC5200... Routing plays a huge factor in the ability to utilize these "gates". The amount you can route will often depent on your design, and speed requirements. "gates" are for ASICs only..... Good luck. ------------------------------------------ J.W. Brooks, Xilinx FAE (603) 891 1096 x19 jwbrooks@xilinx.com ------------------------------------------Article: 6318
In article <3377B37A.58EB@el.nec.com> Jeff Buckles <jeffb_EatNoSpam@el.nec.com> writes: > > [snip] > > Learn to use the resources that are available. Two years from now, > how you learn is going to matter a whole lot more than what you know. Ain't that the truth... -- ----------------------------------------+------------------------------------ David Buckley of Electric Solutions Ltd | Email: dbuckley@esl.tex.com Services to the Computing,Electronics | and Entertainment industries. | Calling from South London, in the UK | -----------------------------------------------------------------------------Article: 6319
Peter Alfke wrote: > > Richard Dungan wrote: > > > > Hello everyone, > > > > I'm thinking about buying the Actel "Designer Series" FPGA design > > package.. > > The intended first application is _very_ register-rich, hence the > > choice of Actel. > > I do not think that the words "register-rich" and "Actel" go together. > Look-up table based FPGAs are register-rich. > For Xilinx FPGA devices you find the number of flip-flops by dividing > the specified gate count by ten. > For example, an XC4010E has 1,120 flip-flops, and if you build long > shift registers, you can hide them in the RAMs and get a ten times > higher density of "virtual flip-flops". > Sorry for this commercial interruption, but facts are facts. > > Peter Alfke, Xilinx Applications > > ---- And for those applications where you need access to more than 1 of every 16 'registers' realized in RAM, you'd be better off with a truly register rich architecture like the Atmel 6K series or the Xilinx 6200. These devices simply can't be beat for bit serial stuff, as well as certain corner-turning applications. The Atmel AT6010 has 6400 cells (80x80 array), each of which is essentially a half adder with a flip flop on the sum output with some extra gating to obtain other 2 and 3 input functions. The 6005 is similar except that its array is 56x56 cells (3136 registers). The Xilinx 6216 is a hierarchical array of 4096 cells (4x4 array of 16x16 arrays). Each cell is contains a D flip-flop and muxes sufficient to realize any two input function and some 3 input functions. Xilinx is supposed to release the larger 6264 sometime this summer, which has four times the cells of the 6216. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 6320
Free internet connection worldwide via our BBS. Please visit as much as possible our sponsor pages, it’s how we are paid... Follow the link and enjoy... http://www.cybercity.hko.net/LA/interbbs/index.htm aababcabcd1121231234Article: 6321
hi Can anybody send me the diagram showing how the outputs of decoder are connected to the output of the chip? The data book shows only the block diagram of inputs of decoder connected. thanks in advance umesh nairArticle: 6322
In article <33799BDC.5150@isv.dec.com>, Gabby Shpirer <gabby@isv.dec.com> writes... >Hi altera readers. > > I'm trying to work with ByteBlaster with no success. > I have NT4 on my computer, MAX+2 ver7.2, added the 7_1pch3.exe -o, > and nothing works. > After declaring the device (EPM9560RC240), I've tried to change the > programmer hardware setup to byteblaster, and then all the option > disapeare. What am I doing wrong???? > >Thanx, > Gabby. >-- >======================================================================== >Gabby Shpirer | e-mail: gabby@isv.dec.com >Digital Technical Center | phone : 972-2-5892640 >Har hotzvim, Jerusalem | fax : 972-2-5892600 >91450 Israel | >======================================================================== The Altera website lists the ByteBlaster patch for Max+2 as being 7_2pch1.exe Daniel Lang dbl@hydra1.caltech.eduArticle: 6323
Hi did anybody successfully perform a VHDL PCI bus implementation in a FPGA (XILINX, ACTEL, QUICKLOGIC,..)? What were the main problems and how did you solve them? How did you test your hardware (PCI analyzer, logic analyzer, only simulation,..)? Thankx for any reply. Best regards Holger Venus German Aerospace Establishment Institute of Space Sensor Technology Rudower Chaussee 5 12489 Berlin Germany Telephone: +49-30-67055-556 Telefax : +49-30-67055-532 e-mail : Holger.Venus@dlr.deArticle: 6324
Richard.Radix@BTinternet.com (Richard Dungan) wrote:
>Hello everyone,
>
>I'm thinking about buying the Actel "Designer Series" FPGA design
>package. Can anyone provide any comments or details of practical
>experience with this? I have prior experience with CUPL up to
>moderately complex devices (Atmel ATV2500) but I'll be a newbie to
>very large FPGAa and also to VHDL.
>The intended first application is _very_ register-rich, hence the
>choice of Actel.
>
>Thanks in advance,
>
Richard
I have been using Designer Series for well over 2 years now and have
found it generally acceptable. I nearly put 'pleasing' there, that
would have been way over the mark!
There are bugs in the current version, and have been in every version
I have used, but currently, nothing that prevents me working. There
have been much more serious bugs in previous versions, one in
particular caused some _very_ heated 'phone calls to Actel. 'Nuff
said.
As a front end I use ViewLogic WorkView Office. I'm surprised to find
myself saying this but it's actually not bad. The surprise arises
because all the previous ViewLogic incarnations I've had to use have
been absolutely, utterly, unquestionably awful.
I strongly recommend you get a months trial on both the Designer
series and whatever front end you choose.
BTW, have you looked at Orcad Express?
Good luck
Julian
--
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk error: smartass.sig not found
Hardware development eng. August Systems Ltd
---------------------------------------------------------------------
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