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I'm a ham fisted software person and I eventually soldered on a TQFP
package.
>Two questions:
>
>1) Do any of you find such packages tend to come in with such
>connection problems?
Yes they're a bitch, but with care they aren't as bad as all that.
- Make sure that the pins are all aligned and are flat.
- I used a hot air iron (Weller gas iron costing less than $100.)
- Use as little solder paste as possible.
- Check each joint with an exacto knife and a microscope (I got a $20
hobby microscope for this). Mechanical pressure from the knife helps
identify poor connections and dry joints.
>
>2) What is the feeling about attempting to re-solder such pins if a
>connection seems to be flakey? Am I wasting my time trying to fix it?
>Maybe if some pins have flakey connections then others on the same
>chip are likely to (eg. if some are bent down too much, then obviously
>the others are at a different level...).
I had better results slowly walking the surplus solder along the pins to
the end of a row, then wicking it off or just shaking it off.
------------ When all else fails, find a scapegoat ----------------
Charles Manning manningc@southern.co.nz
Christchurch, New Zealand
-------------------------------------------------------------------
Article: 6476Richard Schwarz wrote: > The other kits are equally valued. Especially the FSV kit which gets you > in the 4000 and 5000 series chips with gate count restraints. Full That should say WITH NO GATE COUNT RESTRICTIONS for the FSV. Sorry :-)Article: 6477
Stephen P. Pope <spp@rahul.net> wrote in article <5m2qfc$j3p@samba.rahul.net>... > There is a Cypress product, on CD, entitled "Cypress WARP Version 4.0". > The current Cypress databook does not to describe a product > by this exact name; the products listed there are "Warp2", > "Warp2+", "Warp3", and "Warp3 Pro Series Built-in". > > Does "WARP Version 4.0" correspond to any of these? > Yes. We use Warp2 Version 4.0 (and now Version 4.1) Cypress aren't very good with their product labelling! Regards -- /--------------------------------------------------------------------------- -\ | Graham Rhodes | Motion Media Technology Ltd | +44 (0) 1454 338504 Direct | | Design Engineer | Horton Hall, Horton | +44 (0) 1454 313444 Voice | | | Bristol. England. BS17 6QN | +44 (0) 1454 313678 Fax | | mailto:grahamr@mmtech.co.uk | http://www.mmtech.co.uk | |--------------------------------------------------------------------------- -| | The views expressed in this email are not necessarily the views of my | | employer or any other group to which I belong. | \--------------------------------------------------------------------------- -/ A professional is a man who can do his job when he doesn't feel like it. An amateur is a man who can't do his job when he does feel like it.Article: 6478
John Lundgren wrote: > > Bharat Kurani (Bharat.Kurani@add.ssw.abbott.com) wrote: > : I need address/phone/fax list of all semiconductor companines > > Then you should be looking in the Thomas Register. Check your local > library. > > : Thank you > > : bharat@antrix.com > : Bharat.Kurani@add.ssw.abbott.com Or you could try the web page I administer at http://www.mindspring.com/~rsligar/semi.html I think you'll find it to be a great beginning. Roger Sligar Field Applications Engineer Nu Horizons Electronics / AtlantaArticle: 6479
Xilinx is switching from XNF to EDIF in the M1 software. The current version of M1 still supports the XNF format. This includes XNF, XTF (A flattened XNF file generated after XBLOX and XNFPREP in the XACT 6.0.1/5.2.1 software) and SXNF (Synopsys XNF). Kate Meilicke Xilinx FAEArticle: 6480
See:
http://www-ese.fnal.gov/eseproj/svx/bert/xbert.htm
This is a circuit for a RAM-based BERT. Since we are a non-profit lab,
these circuits, software, and PC-board layouts can be used for free by
anyone willing to match wits with our crack team of technology-transfer
bureacrats.
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Article: 6481In article <3387F3EC.569D@earthlink.net>, "William E. Lenihan III" <lenihan3we@earthlink.net> writes: |> |> Also, when it comes to FPGAs and CPLDs, this problem is not just |> peculiar to synthsis: if you are thinking about doing this part of your |> design in schematic and adding the cover terms there, be warned that |> most vendor's mapping and P&R tools will also remove redundant logic in |> the NETLIST it is fed, regardless of whether it came from schematic or |> synthesis. The only exception is if the cloud is small enough to fit in |> one LUT - these are usually glitch-free (though the vendor may not |> guarantee it). |> I was under the impression that most synthesizer tools would allow one to "preserve" the structure of logic. In other words, simply "pass this stuff through without optimazation". I have seen PAL/CPLD tools which allow this, but have little experience (yet) with FPGA targets. There are always cases where one needs to cover a hazard and thus I would question the usability of any tool which demands reduction. There should (must) be some way to get just what you ask for. Any comments on popular synthesizers and back end tools (FPGA place & route) from different vendors? -- Darrell Boots Irvin |"Any ideas or opinions expressed here VND Engineering, Tektronix Inc. | do not necessarily reflect the ideas voice (503) 627-4828 | or opinions of my employer." email boots.irvin@tek.com |Article: 6482
Free Adult Internet Connection Worldwide Via Our Bbs. Follow the link and enjoy... http://cybercity.hko.net/la/interbbs/freenet/free.htmArticle: 6483
Robert Trent wrote: > Okay, I've been using schematic capture for all of my designs (Actel > > 1240s and 1280s, Xilinx 5210 and 5215). This summer I'll be > starting on > a new large audio signal processing design and I want to design with > > VHDL. I'm not sure, at this point, what chip I'll be using but I've > > been eyeing some of the larger Altera 10K series FPGAs. I think > I'll be > needing about 50,000 gates. > > So what's the best way to learn VHDL? Any recommended texts? > Courses? > Tutorials? Or do I just dive in? I'll be talking to some of the > FAEs > soon but I want some less biased opinions from this newsgroup... > > Robert. We have a free introduction to FPGA/VHDL tutorial at http://www.erols.com/aaps/x84lab The tutorial will be peridically updated with on going examples. I hope this is helpful. -- _____________________________________________________ Richard Schwarz, President Associated Professional Systems Inc. (APS) 3003 Latrobe Court Abingdon, Maryland 21009 USA email: aaps@erols.com web site: http://www.erols.com/aaps Phone: 410-515-3883 or 410-290-3918 Fax: 410-661-2760 or 410-290-8146Article: 6484
Simon Bacon wrote: > For those of us who are not on the M1 pre-release program - possibly > > because we don't have paid-up software support - what is M1? > > From other posts, it sounds as if XNF is being dropped. Is that > correct? > > Will we have to abandon our home-grown tools which manipulate > and/or generate XNF? > > --- > Regards > Simon No. The new M1 tools from XILINX will still support XNF files. M1 is the name they gave to the new routing software. The old stuff was called XACT. I have only played with the new M1 for a short time, but it looks really neat. A XILINX rep like Peter Alfke would do better at explaining the M1 in detail, but fear not, the XNF format is still supported. It looks as if eveyone is starting they default to EDIF for outputs but XNF is still in there. -- _____________________________________________________ Richard Schwarz, President Associated Professional Systems Inc. (APS) 3003 Latrobe Court Abingdon, Maryland 21009 USA email: aaps@erols.com web site: http://www.erols.com/aaps Phone: 410-515-3883 or 410-290-3918 Fax: 410-661-2760 or 410-290-8146Article: 6485
Kristopher Miller (millerkl@bucknell.edu) wrote: : Hi all! We are frantically trying to design a microcontroller in a : masochistic attempt to expose ourselves to HDL's and FPGA's. This is : our design project for a junior level class in Digital Electronics, NOT : computer architecture... so don't scream at us for having less than : optimal design... :) : No screams, just a few educational observations. :-) I'm not very familiar with the EPX780, but I suspect that your "tri-state" control statements are affecting the output path of your two storage cells "A" and "B", rather than creating a bussed node for "INPUT" and "B". (assuming that "A" and "B" are defined as "pins" somewhere in your design). I also suspect that PLDasm does not "collect terms" to form equations. By having two separate assignment statements (the statements with "A :="), you are asking the compiler to collect the "right-hand-values" of these statements into a single statement. This may yield the "Multiple definition" error that you are seeing. The statement that worked: : A := INPUT * \control + B * control is one of the preferred techniques, as it directly shows the multiplexor/selector operation that you are trying to perform. If you used some sort of HDL to create the circuit, it is likely the compiler would have yielded something similar. Another good thing to do, to validate the feasibility of your "tri-state multiplexing" approach, is to study exactly what resources in the EPX780 can be controlled in this fashion (i.e., can be tri-stated), and what routing restrictions (which impacts what equations you can write) may be present. Many (most?) PLDs only allow tri-stating of external I/O pins, and not internal cell resources. My vague recollection is that the EPX780 follows this format. FYI, some FPGAs offer limited internal tri-stating through a specific "bus resources", that cells can connect to. Good luck! == Tom Keaveny Hewlett Packard Co. "disclaimer: all comments are my own, and not necessarily that of Hewlett Packard Co."Article: 6486
CADKEY '97 -100+ Available- Save $HUNDRED's EACH!!! Hello! A new copy of Cadkey 97 is selling on the street for $1,195. To guarantee updates for the next year costs $350 more, bringing it up to $1,545 total! I have available over 100 NEW unopened, shrinkwrapped copies of Cadkey 6.0 on CD for DOS which can be upgraded to Cadkey 97, INCLUDING the year's worth of free updates, for the street price of $595; that's $950 LESS than the normal street price! Or, maybe Cadkey 6.0 has enough power for you with no upgrade at all! (Cadkey '97 is basically Cadkey 8.0) I'm selling these for best offer, one or all. If you would like more info on Cadkey 97, here's Cadkey 97's Web page: http://www.cadkey.com/cadkey/index.htm Thanks! KarlArticle: 6487
Djimm2 wrote: > > Hi there 27.5.97 > > A friend of mine told me, that the "guru's" of FPGA's reside in this > usergroup . (Let's see......) > > To all the Xilinx experts I have three questions. First please read the > description of the matter: > > I need to program a Flash-Eprom (AM 29LV008, 8MBit parallel ) which > is attached to a Xilinx 4010 at its dedicated A0..A18 and D0..D7 directly > and exlusively. I cannot physically connect the Flash directly to a > programmer. I have no CPU or uController in this design. > Hi Jim: You may save yourself a lot of time and hassle by programming the flash on a programmer, you do have to have a socket if you plan to change your program frequently. Regards, Kayvon Irani Los AngelesArticle: 6488
Feel free to visit,
http://www.netjava.com
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-------------==== With A Whole Lot More ====------------------
Article: 6489Stuart Clubb wrote: > > On 28 May 1997 19:25:10 GMT, lharold@mrc.uidaho.edu (Len Harold) > wrote: > > >Richard Schwarz (aaps@erols.com) inspired us with the words: > >> All APS-X84 kits come with synthesis. The $499.00 package comes with > >> schematic synthesis. As well as: > > ^ > > | > > > >I think you meant schematic capture and/or optimization. > > > > Thankyou Len, I was beginning to think that I was the only one who > thinks of synthesis as meaning VHDL or Verilog, rather than hooking a > bunch of symbols together in a drawing package. > > I answered an e-mail from Richard, but my diatribe was far too long to > be posted here, plus I try not to post from personal e-mails. > > In summary though, I made three points: > > Firstly, The FB1 package ($499 special offer) does not come with > synthesis (VHDL?). That was my question. I will try to say "VHDL > synthesis" in future. > > Secondly, the Foundation Base V package offering VHDL synthesis is > $1200 in the special offer. So if you specifically want VHDL, you pay > more than with Lucent ($999). Admittedly you do get the great target > board and Xilinx download cable with the Foundation kit. > > Thirdly, and in my opinion, probably most important, is the gate > limitation placed on the Base kits. The upgrade cost to FSV from > Xilinx here in the UK is very high (someone told me about $4000.) > That's a lot for using a 4005E, or a 5206. The Lucent kit offers the > user place and route up to, and including 2C10A and 2T10A both of > which have 28% more 4 input LUT's than XC4010E. Therefore for $999 you > get access to a good density mix with high performance 5V and 3.3V > parts. > > However, if ultimate low cost is your goal, and you don't want VHDL, > and won't yearn for a 4005E ;-) then Richard's offer is great, and > certainly comes in my "cheap" category. It is obviously lower cost > than the Lucent "Summer Offer". > > Stuart I guess I stand corrected on the SYNTHESIS issue. That is, I always considered synthesis of the design to be a step in the process before routing/placement and one synthesis option being schematic capture. Perhaps this is semantically incorrect. The point I was trying to make was that the kits are fully able to implement the designs. Also keep in mind that CPLD support is also included in the Foundation kits, Of course Lucent does not currently have CPLD a product line. All that being said, I think the AT&T kits are a good deal also. Stuart has some good points about the chip sizes available at $995.00. This gets you to a 2c10 I think. However, at $2800.00 in our APS-X84-FSV kits you get no chip size restrictions and full VHDL support with CPLD support and FPGA board and FPGA. I wonder how much the Lucent kits are with unrestricted support. I would wager a good deal more than $2800.00 and still without CPLD support and FPGA board and FPGA. I think the kits which both Stuart and I are putting forth are both great values, and will be a plus for all concerned. Who knows, APS may just put forth a Lucent board kit with that 40K gate part on it! For now we are extremly pleased with the XILINX kits and are pleased to see the FPGA and VHDL tools becoming more and more accessible to start-up engineers. Richard Schwarz http://www.erols.com/aapsArticle: 6490
Per Bjuréus wrote: > > Robert Trent <trent@helix.net> wrote <33876A08.3E71@helix.net>... > > So what's the best way to learn VHDL? Any recommended texts? Courses? > > Tutorials? Or do I just dive in? I'll be talking to some of the FAEs > > soon but I want some less biased opinions from this newsgroup... > > If you are looking for a course or CD-ROM tutorial, check out Esperan at > http://www.esperan.com/ > I attended a Verilog course of theirs last year and was very satisfied, > and I plan to use their MasterClass tutorial now that I convert to VHDL. > > /Per > > -- > pebj@celsiustech.se > is... > Per Bjuréus > CelsiusTech Electronics > S-181 84 LIDINGO > SWEDEN That tutorial comes free with the XILINX foundation kits, and it is very nice. I have also heard talk about the Cypress Book by Skahill, which is an excellent TEXT!! If you only want to do CPLDs, I would reccomend buying just the Cypress Warp kit. It is a good value. If you want to do more serious FPGAs however, the VHDL kits from APS XILINX are a great value! You can see them at: http://www.erols.com/aaps A short VHDL/FPGA tutorial is available on line at http://www.erols.com/aaps/x84labArticle: 6491
John,
This patent lawsuit is complicated, involving claimed infringements on
*both* sides. It will probably end up as a negotiated business
settlement. The patent ruled on most recently will be challenged in
court, as QuickLogic believes they have prior art demonstrating that the
patent should not have been granted, invalidating it.
This lawsuit does not affect the business of Actel or QuickLogic or the
ability of either company to design, produce, or ship products.
---
Kevin Smith
In article <19970526224329123272@cust4.max1.minneapolis.mn.ms.uu.net>,
john@customer1st.com (John Sievert) wrote:
>
> Technology, which it appears, probably came from Actel (per summary
> judgement against QuickLogic on patent infringement.).
>
> <kevintsmith@compuserve.com> wrote:
>
> > In this case, it's not marketing hype, just superior
> > technology.
>
> --
> Regards,
> John Sievert
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Article: 6492Richard Schwarz (aaps@erols.com) inspired us with the words: > All APS-X84 kits come with synthesis. The $499.00 package comes with > schematic synthesis. As well as: ^ | I think you meant schematic capture and/or optimization. Len -- ___ ___ ___ ________ ______ /| | /\ \ /| \|\ _ \/\ __\ Len Harold | | | \ \ - | \ \ \_\ /_ \ \_/ | | \ \ \ \ _|\ \ \ _ \ \ \___ Phone: 208-885-7034 | | \ \ \__\/\ \__\ \__\ \__\ \_____\ Fax: 208-885-6840 | |* | \/__/ \/__/\/__/\/__/\/_____/ Email: len@len.moscow.id.us |/\ |/\ Web: www.mrc.uidaho.edu \/ \_/\ /| | Microelectronics Research Center | | | Center for VLSI System Design | |____________| University of Idaho |/____________/Article: 6493
>If the output is combinatorial, glitches are unavoidable for many >logic functions if there is no way to control the skew of the inputs >to the combinatorial block. For example, a 2-input NAND gate will >glitch on a 00, 01, 10, 11, 00 ... binary sequence Unless I mis-understand: I was told by a Xilinx engineer that the CLBs are designed so that they guarantee NO glitches if the entire gate is done with just a single lookup table. Of course, if the logic is too wide and needs >1 CLB then glitches will exist. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 6494
Peter wrote: > > >If the output is combinatorial, glitches are unavoidable for many > >logic functions if there is no way to control the skew of the inputs > >to the combinatorial block. For example, a 2-input NAND gate will > >glitch on a 00, 01, 10, 11, 00 ... binary sequence > > Unless I mis-understand: I was told by a Xilinx engineer that the CLBs > are designed so that they guarantee NO glitches if the entire gate is > done with just a single lookup table. The gate is never used in isolation. Skew between the input signals to the CLB can cause the glitching described by the (more) original poster. How do you guarantee that there is no skew between the input signals (or so little that it doesn't matter)? In the case of Xilinx LCAs, it can (pragmatically) be done by placing the sources of the input signals right next to the 'NAND' gate, and carefully verifying (with the design editor or timing analyzor) that the delays from these sources to/thru the gate are small and matched. Does this guarantee absence of glitches? I don't know. > > Of course, if the logic is too wide and needs >1 CLB then glitches > will exist. > > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to z80@digiserve.com.Article: 6495
On 28 May 1997 19:25:10 GMT, lharold@mrc.uidaho.edu (Len Harold) wrote: >Richard Schwarz (aaps@erols.com) inspired us with the words: >> All APS-X84 kits come with synthesis. The $499.00 package comes with >> schematic synthesis. As well as: > ^ > | > >I think you meant schematic capture and/or optimization. > Thankyou Len, I was beginning to think that I was the only one who thinks of synthesis as meaning VHDL or Verilog, rather than hooking a bunch of symbols together in a drawing package. I answered an e-mail from Richard, but my diatribe was far too long to be posted here, plus I try not to post from personal e-mails. In summary though, I made three points: Firstly, The FB1 package ($499 special offer) does not come with synthesis (VHDL?). That was my question. I will try to say "VHDL synthesis" in future. Secondly, the Foundation Base V package offering VHDL synthesis is $1200 in the special offer. So if you specifically want VHDL, you pay more than with Lucent ($999). Admittedly you do get the great target board and Xilinx download cable with the Foundation kit. Thirdly, and in my opinion, probably most important, is the gate limitation placed on the Base kits. The upgrade cost to FSV from Xilinx here in the UK is very high (someone told me about $4000.) That's a lot for using a 4005E, or a 5206. The Lucent kit offers the user place and route up to, and including 2C10A and 2T10A both of which have 28% more 4 input LUT's than XC4010E. Therefore for $999 you get access to a good density mix with high performance 5V and 3.3V parts. However, if ultimate low cost is your goal, and you don't want VHDL, and won't yearn for a 4005E ;-) then Richard's offer is great, and certainly comes in my "cheap" category. It is obviously lower cost than the Lucent "Summer Offer". StuartArticle: 6496
> Unless I mis-understand: I was told by a Xilinx engineer that the CLBs > are designed so that they guarantee NO glitches if the entire gate is > done with just a single lookup table. I think Xilinx will promise that if you change a single input to a LUT there won't be any glitches on the output. The output will either not change (no up-down spike) or it will cleanly transition up or down (no up-down-up double edges). Note that there is only one signal changing in this case so skew is not being discussed. I don't remember ever seeing any comments about no-glitches in the presense of not-much-skew at the inputs to an LUT.Article: 6497
In article <19970526224329123272@cust4.max1.minneapolis.mn.ms.uu.net>,
john@customer1st.com (John Sievert) wrote:
>
> Technology, which it appears, probably came from Actel (per summary
> judgement against QuickLogic on patent infringement.).
>
> <kevintsmith@compuserve.com> wrote:
>
> > In this case, it's not marketing hype, just superior
> > technology.
>
> --
> Regards,
> John Sievert
Aren't you the Actel Manufacturers Rep in the MN area?
It would behoove you to not sling mud and try to hide your identity.
Regards,
Ben Blair
Manager Field Applications
QuickLogic Corporation
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Article: 6498To anyone living in the San Francisco Bayarea: Complimate Technical Staffing (Sunnyvale, CA) is seeking people with programming and other Software backgrounds who wish to work as Technical recruiters. If you are interested please call 408-733-8994 Or e-mail: CareerDesk@complimate.com Or fax: 408-733-0968Article: 6499
Hal Murray <murray@pa.dec.com> wrote in article <5mi9o3$d5u@src-news.pa.dec.com>... | > Unless I mis-understand: I was told by a Xilinx engineer that the CLBs | > are designed so that they guarantee NO glitches if the entire gate is | > done with just a single lookup table. | | I think Xilinx will promise that if you change a single input to a LUT | there won't be any glitches on the output. The output will either not | change (no up-down spike) or it will cleanly transition up or down | (no up-down-up double edges). | | Note that there is only one signal changing in this case so skew is not | being discussed. | | I don't remember ever seeing any comments about no-glitches in the | presense of not-much-skew at the inputs to an LUT. I seem to remember that a LUT is glitches only for single input transitions. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic
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