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Hello, I'd like to solicit some opinions once again for the age old Verilog vs VHDL question. Definitely NOT trying to start another holy war, but like to hear opinions about these languages. I'm simply trying to solicit these opinions on behalf of my advisor. Here at the University of Maryland, we've been using an HDL from Japan, known as Parthenon/SFL (and octools) to go from a high level hardware description to Silicon. Those designs are then sent to MOSIS for fab. However, since SFL isn't well known, or widely used here in the US, We're probably going to emphasize either VHDL or verilog more. Currently, we're using VHDL under Mentor Graphics for design work, though we haven't submitted anything for MOSIS fabrication. Soon, we will be getting Cadence. Our target device will be various types of FPGA's that we are just starting to get, Motorola, Xilinx, and perhaps a few others, We would also like to be able to compile down to a VLSI layout, and submit it to MOSIS for fabrication. The general feeling by just about everyone I have spoken with is that Verilog with Cadence, with synopsis Libraries is the direction that we should be going. Any suggestions? opinions? please post or email davewang@wam.umd.edu, or kazuo@eng.umd.eduArticle: 6176
Hello all, I have code for a couple of 22V10 PALs written in PALASM. I want to consolidate the PALs into a CPLD and add some other logic. To do this I have to convert the PALASM code to VHDL. My problem is I'm looking into using the AMD's ISP Mach family or the Cypress ISP Flash370 family. I need to know what are the pros and cons for both parts. Which one has better the better design tools? The Mach software is free. The Flash370 is $99. Both have ISP. What's the price and performance difference between the two? Thanks, Del SolArticle: 6177
Timothy Del Sol wrote: > > Hello all, > > I have code for a couple of 22V10 PALs written in PALASM. I want to > consolidate the PALs into a CPLD and add some other logic. To do this I > have to convert the PALASM code to VHDL. My problem is I'm looking into > using the AMD's ISP Mach family or the Cypress ISP Flash370 family. I > need to know what are the pros and cons for both parts. Which one has > better the better design tools? The Mach software is free. Tim, which MACH software are you talking about? Last time I checked into buying the complete VHDL toolset + fitter + timing analyzer for MACH5 the cost was over 5 grand! I guess the problem is AMD does not produce any of these tools not even the fitters for new devices. As far as Cypress tools, they produce the entire toolset and therefore can sell it at a lower price hoping they'll make that up in silicon sales. I have seen both toolsets and they both have their high and low points but overall they both do a descent job. Regards, Kayvon Irani Los Angeles, CaArticle: 6178
Timothy Del Sol <tdelsol@primenet.com> wrote in article <335D90EB.31E7@primenet.com>... > > better the better design tools? The Mach software is free. The Flash370 > is $99. Both have ISP. What's the price and performance difference > between the two? > Hi, Timothy: I think Lattice ispLSI/pLSI is your best choice! All lattice CPLDs have ISP function, and Lattice ISP is free now! (the unit price of ispLSI device is the same as non-ISP pLSI device). Lattice ispLSI device's DATA retension is more than 20 years, and more than 10,000 Erase/Reprogram cycles, (AMD only 100 cycles). The price is also lower than other vendor's. (in my country:-) For sw, Lattice now has free CD of ISP Synario Starter sw, you can request it from your local Lattice sales office or distis/reps. You can find more information from (http://www.latticesemi.com) good luck! DavidArticle: 6179
Greetings all:
To those reading this group with a large interest in RC, is there
a different forum dedicated to RC? There appears to the little discussion
about RC, existing platforms, developments, plans given DARPA ACS funding,
etc.
Please fill me (us) in.
Thanks,
Bruce
Article: 6180> Therefore, our pASIC1 lineup looks like this: > > pASIC1 device # logic cells 2-input NANDs usable gates > QL8x12B 96 2,976 1,056 (1k) > QL12x16B 192 5,952 2,112 (2k) > QL16x24B 384 11,904 4,224 (4k) > QL24x32B 768 23,808 8,448 (8k) > Any comments on how these compare to CPLD gates/logic cell counts? Recently, I had a design done in VHDL with a bunch of up/down counters (count up by two down by one) and some simple I/O logic. The design fit in QL12x16B with 84% utilization; the same design also fit in a Xilinx xc95108(108 logic cells) with 98% utilization. Both designs were run through the same synthesis tool with area optimization optin selected. Any comments? Kayvon Irani, Los AngelesArticle: 6181
DEADLINE: MAY 1
Call For Papers: FPGA
IEEE Design and Test of Computers
Special Issue
Spring 1998, Volume 15, Number 1
Web Page: http://www.cs.tamu.edu/faculty/lombardi/datsi.htm
IEEE Design and Test of Computers seeks original manuscripts for a
theme issue on Field Programmable Gate Arrays (FPGAs) scheduled to
appear in the first issue of 1998. Articles concerning applied
research and practical experience reports are solicited. The topics
of interest include, but are not limited to:
FPGA Fabrication and Technology. Manufacturing, process control,
yield enhancement, and novel architectures for and device
technology to support field programmable chips.
Exploitation of Field Programmability. Configurable computer
architectures, rapid prototyping, programmable interconnect
architectures, field configurable memories, programmable I/O
systems, and novel implementations.
Reliable Online Implementations. Online testing, built-in
self-test, concurrent testing, design for rapid testability,
latency reduction, fault containment, verification of
reprogramming, online reconfiguration approaches, and design for
reconfigurability.
Synthesis Approaches and Tools. Partitioning, logic minimization
and technology mapping, placement and routing, test generation,
verification of synthesis, and design for synthesizability.
Submitted articles must not have been previously published or
currently submitted for publication elsewhere. Authors should submit
their original work to the guest editor by May 1, 1997, formatted
according to the instructions below. Notification of acceptance will
be sent September 1, 1997. Camera-ready copy for accepted papers will
be due November 1, 1997.
Submit articles by May 1, 1997 to:
Prof. Fabrizio Lombardi, Guest Editor
Department of Computer Science Phone: (409) 845--5464
Texas A & M University Fax: (409) 847--8578
College Station TX 77843-3112 E-Mail: lombardi@cs.tamu.edu
Important dates:
May 1, 1997: Submission deadline
September 1, 1997: Authors notified of acceptance
with requested revisions
November 1, 1997: Final copy due to Design & Test Managing Editor
Spring 1998: Publication in IEEE Design and Test of Computers
Submission requirements:
Send six (6) copies of the manuscript, in English, to the guest
editor. Manuscripts are not to exceed 35 double-spaced pages,
inclusive of figures and tables, in A4 or 8.5 by 11 inches. Type size
must be at least 12 point. Each copy of the manuscript must contain a
cover page with author contact information (name, postal address,
telephone number, and e-mail address) and a 100-word abstract.
Manuscripts must be cleared for publication. Accepted manuscripts
will be edited for technical content, structure, style, clarity, and
grammar. Detailed information for authors can be found at the Computer
Society D&T website at http://www.computer.org/pubs/d&t/d&t.htm or in
the Spring 1996 issue of Design & Test.
Article: 6182Can somebody tell me if it`s possible to download a bitstream to a XC4000 component with a Xchecker cable that`s supposed to be used for a XC3000 or a XC2000 component? If it`s possible, how can I do it?Article: 6183
Kayvon Irani <kirani@cinenet.net> wrote in article <335DA0EB.7240@cinenet.net>... > Timothy Del Sol wrote: > > > > Hello all, > > > > I have code for a couple of 22V10 PALs written in PALASM. I want to > > consolidate the PALs into a CPLD and add some other logic. To do this I > > have to convert the PALASM code to VHDL. My problem is I'm looking into > > using the AMD's ISP Mach family or the Cypress ISP Flash370 family. I > > need to know what are the pros and cons for both parts. Which one has > > better the better design tools? The Mach software is free. > Last time I checked the AMD mach ISP parts were many times more expensive than the Cypress equilevents. I've used the Cypress CY7C374i parts with the $99 software (plus a $99 programming pod) and have been very happy with them. Lots of routing resources.Article: 6184
In article <5jk8hh$jh2@newsstand.cit.cornell.edu>,
Bruce Pirger <pirger@astrosun.tn.cornell.edu> wrote:
>Greetings all:
>
> To those reading this group with a large interest in RC, is there
>a different forum dedicated to RC? There appears to the little discussion
>about RC, existing platforms, developments, plans given DARPA ACS funding,
>etc.
> Please fill me (us) in.
This (comp.arch.fpga) is the usenet forum for discussion of
reconfigurable computing, although it's difficult to tell from the
content these days. The original charter of c.a.f states:
The unmoderated newsgroup comp.arch.fpga will be open to discussions
on all topics related to the use of reconfigurable Field
Programmable Gate Arrays (FPGAs) as computational engines.
Appropriate topics include, but are not limited to:
system architecture
FPGA device architecture
languages and compilation techniques
tools
software environments
applications
At the time this newsgroup was formed (during the "request for
discussion" period) there was a great deal of discussion about the
name of the group. Some felt that "FPGA" was too technology specific,
while others maintained that since there was no concensus name for the
field, FPGA would suffice if the group were put under the "comp.arch"
hierarchy. So here it is.
With the increasing interest in custom computing as evidenced by the
record attendance at FCCM and the DARPA ACS program, perhaps we will
see an increase in releated postings in comp.arch.fpga.
-jeff
--
Jeffrey M. Arnold jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace Tel: 619-547-9257
San Diego, CA 92131 Fax: 619-547-9010
USA
Article: 6185The registration information and the advance program for the International Workshop on Logic Synthesis (IWLS) '97 is available off the web at: http://www.ee.princeton.edu/iwls97.html Sharad Malik. -- Sharad Malik sharad@ee.princeton.edu Associate Professor 609-258-4625 Dept. of Electrical Engineering 609-258-3745 Fax Princeton University http://www.ee.princeton.edu/~sharadArticle: 6186
Kayvon Irani wrote: > > Timothy Del Sol wrote: > > > they both have their high and low points but overall they both do a descent > job. > > Regards, > Kayvon Irani > Los Angeles, Ca Descent job ? You mean they fall over often ?Article: 6187
Hi all, Below is a report I sent to xilinx support about a problem I am having with the hardware debugger. While Xilinx tech support have been most cooperative, I still have not had the problem resolved. If anyone can help me on this, I would be most appreciative - time is a-waistin'..... -------------------------------------------------------------------------------------------------------------------- Version of Software: V7.12 XactStep V6.0.1 OS: WFW311/Win32S13C HW Config: P5-150, 48MB RAM, 2G Disks Installation: Local HD Notes: The whole translation/compilation process in XDM works fine, and I have included the Readback symbol in the schematic. Note that the RDCLK symbol is removed during the compilation process. I assume that the compilation automatically uses CCLK as stated in the documentation. Problem: ====== I have a question re. the hadrware debugger that comes with Xact V6.0.1. When I load the bitstream file (root.bit) into the debugger, I get the message: "The logic allocation file (.ll file) for the specified design was not found. Debugging options will b disabled" The file (root.ll) is in the directory (d:\test\test\v1_8\rev1\root.ll) and has standard file attributes. Even if I copy the file to other directories higher up the tree, or into Xact/Data as suggested in the Hardware & Peripherals Guide, I have no success. This Guide says to ensure that the file is in either the xact/data directory (why, when each different version of the design would probably have different logic layouts????) or the current dir (?? presumably the v1_8\rev1 directory quoted above.). Am I looking at the wrong warning in the Guide? I am looking at Warning 005 "LL file filename.ll is not found. Design verification will not work correctly.", P3-69. The warning has the same apparent meaning, but differs in detail: The message that comes up in the debugger does not quote a warning number, and is worder slightly differently. I have looked through Xilinx Answers on Xilinx's web site, & it merely points me to this info in the Hardware & Peripherals guide. -------------------------------------------------------------------------------------------------------------------- Regards, Stu. --------------------------------------------- Stuart Summerville Project Engineer Practel International 442 Torrens Road, Kilkenny, SA 5009 Tel: (61.8) 8268 2196 Fax: (61.8) 8268 2882 Email: stuart.summerville@practel.com.au ---------------------------------------------Article: 6188
At FCCM, co-chair Ken Pocek of Intel challenged us to go after the search for Mersenne prime numbers, which are the biggest of all known primes. A Mersenne prime is of the form 2^n-1. The current biggest is 2^1398269-1, found by the Great Internet Mersenne Prime Search project, which has lots of people using their PCs' spare cycles to run prime-searching free shareware. http://www.mersenne.org The hard compute problem is to multiply really big integers very fast. Really, really big. Millions of bits long each. Ordinary multiplication is an order-n^2 algorithm, which blows up on such numbers. There are many better algorithms, including some based on using FFTs. (See Knuth Vol. 2) Most of the algorithm development lately has naturally been directed towards algorithms that run well on conventional computers, which have lots of memory, fast pipelined floating point, but narrow, fixed-length words and the dreaded memory-processor bottleneck <choke>. With FCCMs, that is FPGA-based machines, those constraints are reversed. We can program thousand-bit multipliers, parallel FFT accelerators, cellular automata, systolic arrays, whatever. What are good algorithms to use for very long word multiplication on FPGAs? Ones which get faster when more FPGAs are added? Ones which get really fast with tons of FPGAs? FPGAs are always growing, you know. Who will be the first to discover the largest prime so far using FPGAs? --MikeArticle: 6189
George (gzs@explorer2.clark.net) wrote: : : >Both available memory and processor speed will enhance your performance, : : how about these dual or quad pentium or pentium-pro boards : : is it realistic to expect a speedup for the Altera or Xilinx : software compared with the uni-processor machines if running : NT - (im a unix person I do not know what kind of multi-tasking : NT really has for running other jobs simultaneously) I think it was discussed some time ago -- Max+Plus II doesn't take advantage of more than one CPU. But if you multitask, one CPU can be used exclusively for compiling while the other's free to do other things. --- Reply-To: and From: fields have been altered to avoid spam.Article: 6190
The Xchecker cable, DLC4, can be used with XC2000, XC3000, XC4000, and XC5000, products. The FPGA is setup for Serial Slave mode configuration, and in the case of the XC4000, you will need to connect the following signals from the DLC4 to your target system: Vcc, Gnd, CCLK, D/P (connect to the done pin, with a pullup resistor as well), Din, Prog, and Init. The rest of the DLC4 signals can be left unconnected. This is shown in my "Xact Hardware and Peripherals Guide". The hard copy has the info on page 5-18. The online copy (with V6.0.1 SW) has it on page 3-20 All the best, Philip Freidin. In article <5jl4dn$lp9@infoserv.rug.ac.be> jmaus@elis.rug.ac.be (Jurgen Maus) writes: > >Can somebody tell me if it`s possible to download a bitstream to a XC4000 >component with a Xchecker cable that`s supposed to be used for a XC3000 >or a XC2000 component? > >If it`s possible, how can I do it? >Article: 6191
Hi all, I am looking for a full discription of the EDIF200 netlist-standard. Does anybody know, where to get it ? Regards, Thomas email: finke@iti.mu-luebeck.deArticle: 6192
Thomas Finke wrote: > > Hi all, > > I am looking for a full discription of the EDIF200 netlist-standard. > Does anybody know, where to get it ? > > Regards, Thomas email: finke@iti.mu-luebeck.de You could try the edif web site at http://www.edif.org/ Christian Glover. email: cartland@apg.philips.co.ukArticle: 6193
In article <peter-1404971535550001@appsmac-1.xilinx.com>, peter@xilinx.com (Peter Alfke) wrote: >In article <5iocgn$thg$1@news.goodnet.com>, waynet@goodnet.com (Wayne >Turner) wrote: --- begin included text --------------------------------------------------- [...] >If you promised to measure, you measure honestly and don't use any magic >tricks with disappearing logic. > >Peter Alfke, speaking for himself --- end included text --------------------------------------------------- I've included the above text so everyone knows what my followup below was directly referring to, namely Mr. Alfke's desire for honesty in measurement. He left that part out of his post for some reason. The following was my post about disappearring logic and honesty in measurement: >> Then do you also disagree with how your company seems to report macrocell >> usage in your 9500 family, where even if all products terms for a macrocell >> are borrowed He also left out the rest of this statement, which continues: "the report shows the macrocell as not used, though there are no products term left in it? I found that to be an interesting measurement itself. Correct me if I'm wrong, but if I'm not then what is your opinion on that?" >That was a cheap shot. Really? Mr. Alfke's first response to my question was the private unsolicited email he sent me after my post, which is included here in its entirety: --- begin included email -------------------- "Wayne, I agree with you, if it's the way you say. Borrowing from a macrocell is, of course a "soft" thing. If I borrow one or two terms, I have not really killed it. But borrowing all five makes the macrocell useless. I will look into this. I am all for honesty. Thanks for pointing this out. Peter Alfke" --- end included email ---------------------- At the time, I appreciated his response, and he obviously didn't feel my question was a "cheap shot" and even thanked me for pointing it out. I later emailed him and merely asked if he had any new news on the situation, and he responded with this post which he also emailed to me. >I had complained about Altera using deceptive methods in PREP, where >potential users are supposed to find a fair and honest comparison between >technologies and manufacturers. > >Wayne then compares that to the XC9500 fitter reporting only the number of >macrocells used, without consideration of how many product-terms were >³stolen² from the neighbor(s). Actually, my post was in reference to "disappearring logic", which is what you occassionally get if you try to use the remaining macrocells that seem to be unused in a XC9500 design report file. You may think you have half the macrocells left, but when you try to use them, they disappear because the logic in the front of them was gone already. >But that is a detailed report that you get AFTER you have done the design, >and the same report also specifies product terms and I/Os used. The number >of macrocells used is just one ingredient, and there really is no fair way >to report it any differently. > >1. I/O pins limit how many signals may be brought into and generated by >the device. > >2. Macrocells limit the size of the design with regard to how many logic >functions may be implemented. > >3. Product terms determine the complexity of the design with regard to >the complexity of each implemented logic function. > >Any CPLD design, regardless of vendor, may be I/O limited, macrocell >limited, or product-term limited. Therefore, we report I/O, macrocell, >and product term usage in the header of the fitter report. I still fail to see how a device can have any "macrocells" left if all of the product terms are used. And I also wonder if anyone has seen an apps guy use the macrocell usage statistic to show less device usage over a competitor for the same design. Let's face it, when parts are numbered by number of macrocells, macrocell usage is what people are going to look at first. The problem is, most people assume a macrocell has LOGIC associated with it; it's generally not just an unused register. >To take this a step further, exporting all 5 product terms from a macrocell >does not necesssarily make that macrocell unusable. That same macrocell >that exported all its product terms, can import product terms from other >macrocells that are implementing less complex logic functions. ( I have >heard that the French import some red wine from California ). A quote from Mr. Alfke's email to me, also shown above: "Borrowing from a macrocell is, of course a "soft" thing. If I borrow one or two terms, I have not really killed it. But borrowing all five makes the macrocell useless. " So is it useless or not? You've said both... And one cannot indefinitely borrow product terms; eventually you run out of macrocells, right? Otherwise all of those chain-letters to ask 10 friends to send you a dollar would really work and we would all be millionaires ;) >This subject has no relationship to Alteras ³manipulation of the truth² in > PREP. I would think all manipulations of the truth are related... The point is, I personally feel you are probably an honest person yourself, but your perception is colored to the point where you think YOUR company doesn't do the same marketing types of things as you beat on your competitors for supposedly doing. As someone else said so well in an earlier post, "let he who is without a marketing department cast the first stone"... WayneArticle: 6194
Yves Blaquiere wrote: > How can these designs, generated with xbloxgen and memgen, be > simulated in Synopsys. I think that instantiation is useless if their > behavior cannot be simulated before place and route. The XACT 5.2.1 software doesn't provide simulation models for xbloxgen and memgen. The only solution with this version of software is to do a quick place and route - router/placer effort of 1, back annotate and do simulation. It is not a good solution. The real fix is the next version of software - M1. xbloxgen and memgen are replaced with LogiBLOX. LogiBLOX provides Verilog or VHDL for functional simulation. Talk to your local FAE or Sales Rep about getting the new version of software. Kate Meilicke Xilinx FAEArticle: 6195
Kayvon Irani wrote: > > Hello every one: >Are the FPGAs in a position to offer a cost-effective hassle-free > solution to system level integration compared to ASICs and gate arrays for > densities below 100K and volumes of less than 5K? Can the tools easily handle > different IP cores from different providers? Has any one implemented multiple > IP cores in one FPGA? Any comments are appreciated. Check out the Xilinx web page: http://www.xilinx.com Click on Systems Level Integration and then Alliance Core Program. There are several Third party vendors that have cores for Xilinx FPGAs. Kate MeilickeArticle: 6196
Anyone have experience with the Escalade Design Book (v 2.1) VHDL front end tools? I'm aware the earlier releases had problems, but how about the new one? NOTE: remove <SPAM> from reply email address if responding via email THANKS!!Article: 6197
Some time ago, I was working on an FPGA implementation of a systolic array, which was a serial array of adders and maximum functions. I implemented a saturating adder and max function as xilinx macros. The design also had a lookup table for each unit cell. Well, a unit cell was five 16 bit saturating adders, six 16 max functions, and an n by 8 lookup table. I could get four such unit cells into a XC4013. It was interesting to see what optimizations PPR could do. Earlier in the design, I was using adders and maximum functions designed by a verilog compiler, which required, and allowed, more optimization. The main optimization that is allowed is that the comparison required by a maximum function is all generated by the carry logic, and the LUT are free for the multiplexer. This is how I designed it as a macro. But between the verilog compiler and ppr, it did manage to reuse some, but not all, of the LUT in the subtractor for doing the compare. Anyway, I think that any optimizations a compiler can find in real problems should be legal in benchmarks. If they have to be hand optimized, then that probably isn't fair. But then some real desings need hand optimizing, also. Maybe, like the SPEC processor benchmarks, some real designs need to be used. How about an implementation of the Intel 8086? For smaller ones, the i4004? Maybe other new or old processors could be used, too. Maybe there are better real-world designs, but I think, like SPEC, they should reflect what people really use them for. -- glenArticle: 6198
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THE ADVANCED PLD & FPGA DAYS, 97
Call for participation at the
7th Annual Advanced PLD & FPGA
Conference and Exhibition,
May 13th, May 14th, The Ascot Pavilion
Ascot Racecourse, UK.,
May 20th, Stockholmsmassan, Stockholm
The event is organized by Miller Freeman plc.
30 Calderwood St., London SE18 6QH
Details and on-line registration are available via the World Wide Web at
URL = http://www.pld97.co.uk
May 13th
2.00 - 5.00pm TRAINING MODULE
"Introduction to PLDs and FPGAs"
Workshop run by University of Kent
14th May
9.00am Registration & Exhibition opens
9.20am Introduction and best paper award for APFD '96
9.30 - 10.00am KEYNOTE PRESENTATION
"Challenges for the CPLD and FPGA market"
Prof. Gabriele Saucier
Institut National Polytechnique Grenoble
The remainder of the day is divided into two streams denoted A and B
10.20am A "Efficient implementation of telecoms IP cores in system
programmable gate arrays", Stef Niewiadomski, Actel
B "Advanced high-level HDL design techniques for
programmable logic", Darron May, ALT Technologies
10.50am A "Three FPGA systems and subsystems clocked at 200MHz",
Peter Alfke, Xilinx
B "How much VHDL simulation is needed for a complex FPGA",
M. S. Abrahams, TransEDA
11.20am C O F F E E B R E A K
11.50am A "Flek 10K: extending the boundares of programmable
logic", Tim Symons, Altera
B "Design methodologies for dynamically reconfigurable
FPGAs", Joel Rosenberg, Atmel
12.20pm A "The 100Kgate plus FPGA design challenge",
Steve Collis, Mentor Graphics
B "Video motion tracking using Harp and Handel: a case
study", Jonathon Saul, Oxford University Computing
Laboratory
12.50pm L U N C H B R E A K
2.15pm A "Implementation of a PCI-bus target interface in a high
density FPGA", Adam Elbirt, Viewlogic Systems
B "FPGAs: the value of reprogrammability",
Thomas Oelsner, Quicklogic
2.45pm A "Complex RTL-to-silicon time scales using
laser-programmable gate arrays"
Nick Heaton, Excel Consultants
B "A designers guide to selecting in-system programming"
Mark Aaldering, Philips Semiconductors
3.15pm B R E A K
3.45pm A "Techniques and tools for FPGA-based DSP design"
Bradly Fawcett, Xilinx
B "SCUBA: a tool for efficient ORCA FPGA data-path/memory
synthesis", Tom Smart, Lucent Technologies
4.15pm A "CPLDs and FPGAs: is there really a difference",
Peter Trott, Vantis
B "Timing-driven optimization of FPGAs using top-down
design", Doug Perry, Exemplar Logic
4.45pm C O N F E R E N C E E N D S
--
Peter Clarke
Programme Co-ordinator
Article: 6199> [...] > >If you promised to measure, you measure honestly and don't use any magic > >tricks with disappearing logic. > > > >Peter Alfke, speaking for himself > --- end included text "Magic tricks with disappearing logic" is what reconfigurable computing is all about! So, does that make me dishonest??? (deliberately taken completely out of context) -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randraka
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