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In article <33362D36.474D@nocrc.abb.no>, Johannes Soelhusvik
<jso@nocrc.abb.no> writes
>Tom Burgess wrote:
......
>First of all, thanks very much for responding to my query.
>I confirm that I just want the integer portion of the division. And your
>suggested solution is nice and simple, but I do not have time to go
>through as many as 255 clock cycles (worst case). What can I do to
>reduce this to say 32 ?
>
I've a similar problem to do at pixel rates.
You can solve the problem simply by repeated subtraction with shift.
for A/B
if (A - B * 2^7) is negative MSB of result = 0
else A = A - B * 2^7 MSB 0f result = 1
repeat for 2^6 etc.
This should produce results in 8 clocks and provide the remainder.
On the down side this more logic expensive than some of the approaches.
Savings in clock cycles can be made by matching the highest set bits of
A and B eg. A highest bit is 6, B highest bit is 4 can start with
2^(6-4+1) This however provides data dependant execution times, as a
result the worst case still needs to be covered and this still takes the
same number of cycles.
--
Andrew Papageorgiou
DSP Hardware Engineer
Article: 5901Hi, Does anyone want to say something about EPLD domain? Please join me.Article: 5902
Henry Spencer (henry@zoo.toronto.edu) wrote: : Alas, not all chip suppliers are smart enough to see that they will sell : more chips if they make a firm commitment to a competitive market in : support tools. If the objective is to sell more chips, it makes no sense : to artificially restrict the prices and functionality of support tools by : maintaining a monopoly position. Ah! One of my pet peeves! I recently updated a design with several CPLDs to an ISP design. The original design was done using CUPL from Logical Devices, targeting AMD Mach/Cypress 37x CPLDS. CUPL used PLA file interfaces to the AMD (Machxl 2.1) and Cypress (Able fitter kit ver3.2) fitters. In evaluating which ISP vendor to select, CUPL compatibility was a primary concern, because the existing designs worked. Fine pitch SMT packages were also required for density. So here were my results: Altera: There was no CUPL/Altera fitter combination to support their ISP CPLDs. Besides, Altera caused me too much re-design grief by discontinuing plds in use by current products. AMD: Stopped supporting 3rd party tool vendor PLA interfaces when they turned development over to MINC. CUPL was not going to integrate and sell me their competitors product! Maybe Vantis will fix this (I hope). With no ISP fine pitch pkg support in the Machxl 2.1 fitter, ruled out. Cypress: Said they were not going to upgrade their fitter kit to support their ISP devices. Since I did not want to port CUPL to VHDL for their WARP fitter, they were out. With some experimentation, the Warp fitter might have worked with CUPL, but I did not have the time to play. Lattice: CUPL supported the Lattice $1000 fitter, so we tried it. Lattice technical support was outstanding! Fron the regional FAE to the factory people. They made every effort to make sure I and the CUPL development people had the fitter information needed for my designs and CUPL's fitter interface. Unfortunatly, the Lattice device architecture did not lend itself well to my designs. I had to make too many compromises to be comfortable with the results. This leads to... XILINX: The Xilinx XC95xx cplds looked like ideal candidates for my application. So I bought the DS-560 fitter, and got the CUPL interface update from Logical. The biggest impediment to porting my designs turned out to be Xilinx technical support, or the lack thereof. Item: My first email for help elicited a response that XILINX does not support CUPL as a design front end! This despite the figure in the DS-560 data sheet showing CUPL feeding the design tool chain. Item: I was also told that the current fitter was 6.20 [sic- the current rev is really 6.02). I then asked why I received (that same day in January) release 6.01, with no update notice in the package. Two months later I am still waiting for an answer. Fortunatly my distributor FAE found the 6.02 update on the Xilinx FTP server. Item: The documentation on the fitter CDROM was totally inadequate. I had to rely on the old CUPL/Xilinx 5.1 fitter book from Logical, and a couple of downloaded Xilinx app notes. Xilinx Tech support disclaimed any support for controlling the fitter using the .ctl file, even though that is how the GUI interface does it. The CUPL development folks were most helpful in modifying their fitter interface on short notice whenever I managed to find design controls that needed to be supported. Xilinx could have made the 3rd party integration virtually painless had they included even a 1-page summary of declarations which were useable in the plusasm source, and a list of the the legal entries in the .ctl file, and the fitter command line syntax. Even with a caveat that this could change in future releases, it would have saved a lot of headaches. -- Gerry Belanger, WA1HOZ wa1hoz@a3bgate.nai.net Newtown, CT g.belanger@ieee.orgArticle: 5903
We'd like to announce that SUMMIT Microelectronics website is now OPEN! http://www.summitmicro.com === Summit Microelectronics Website Open For Business Website Includes Pricing Information Monday, March 24, 1997 Summary 1) Summit Microelectronics Website is located at http://www.summitmicro.com 2) Information Includes: - Data Sheets - Applications Notes - Pricing - Sales and Technical Marketing Contacts - Company Background, News and Employment Opportunities Summit Microelectronics, Inc. announces the availability of its website located at http://www.summitmicro.com . The website is intended to serve as a major resource to design engineers seeking information on Summit’s products combining state of the art analog and E²PROM technologies. "We view the Internet as a major element of our marketing strategy to reach the design engineers who need the cost effective solutions which Summit is offering", states Rich Palm, Vice President of Marketing. "Our goal is to provide the design engineer with the information that he or she needs in order to make a decision regarding the suitability of the Summit products for the project at hand. Since component price is an important design criteria, we have decided that accurate and relavent pricing must also be included on the web site in addition to the more traditional data sheets and sales contact information." The Summit website allows the engineer to select a product in two different manners; either by reviewing data sheets and selecting the appropriate product or by filling out a questionnaire describing the technical attributes of the product they are seeking. If the second method is chosen and a matching product exists in the Summit product offering, reference data, including data sheets, application notes and 10,000 unit pricing will be made available. In the event there is not a product match, the engineer can choose to submit the product configuration to Summit as a product proposal. It is also planned that customers will be able to order product directly from Summit via the website by using a credit card. "We feel that the absence of current pricing on semiconductor manufacturer’s websites greatly reduces their effectiveness to the design engineer," continues Palm. "It seems kind of silly to give all of the technical information to the engineer and then force him to either EMAIL or phone a request to get pricing information, reducing information data flow rate from a torrent to a trickle. The 10,000 unit price has been chosen since it is the medium volume customer requirement in the markets that the Summit devices serve." Background Summit Microelectronics, Inc. is a privately held company focusing on the integration of analog and E²PROM technologies to provide cost-effective solutions to a variety of applications in the telecommunications, consumer and automotive markets. Its website may be found at www.summitmicro.com . === thanks, and please let us know if we've structured it correctly!!! webmaster@summitmicro.comArticle: 5904
Welcome to the web ... I've added your website to my directory and as soon as my ISP clears up their security problems I'll upload the new pages. P.S. tell your web-folks to include a way to turn off the dang frames ... some folks love 'em, some hate 'em, and some web browsers can't hack 'em -- Electronics Resource Page at http://homepage.dave-world.net/~donw1948/index.html webmaster <webmaster@summitmicro.com> wrote in article <33375F49.4C9A@summitmicro.com>... > We'd like to announce that SUMMIT Microelectronics website is now OPEN! > > http://www.summitmicro.comArticle: 5905
In article <01bc38e6$3bb9d800$09021ace@rickweis>, Dodderin' Ol' Don <?@usa.net> writes >Welcome to the web ... I've added your website to my directory and as soon >as my ISP clears up their security problems I'll upload the new pages. P.S. >tell your web-folks to include a way to turn off the dang frames ... some >folks love 'em, some hate 'em, and some web browsers can't hack 'em <soapbox> I agree! I find it annoying that web page designers make their pages inaccessible to part of their potential users by putting all the latest bells and whistles on them. Whilst it is OK to want to make your site as attractive as possible, have some way for people using older browsers and slow connections to use them. I have only a 9600 connection because the 'phone lines out here in rural Herefordshire (England) are not good enough (I have a 28.8 modem!), and when I use the web it is with Netscape 1 something with images switched off. I get the impression that a lot of web page designers never take the trouble to look and see what their work looks like when used in this way!! Assuming that you think the information on your site is worth looking at :) - isn't it worth taking the trouble to make it available to the greatest number of people? </soapbox> -- Chris Wright Rolt Manufacturing Ltd ki11@cityscape.co.ukArticle: 5906
Interesting story. I too like CUPL, use it for 16v8/22v10 PLDs all the time, and have successfully used it to develop parts of various XC3064/3090 FPGA projects, mainly state machines done with CUPL's state machine preprocessor. Xilinx used to give away a program from Exemplar called PDS2XNF. This converts PALASM output (which CUPL can generate) to XNF. There was also an optimiser called XNFOPT (not really necessary but worth it). They no longer supply this program but I have it. It took me only about 1 day to get this working, with no documentation or support available. In CUPL, you have to use the VIRTUAL device, so there is no pin limit. All this was done using the virtually solid 1991 DOS tools, and it works fine with XACT6 P&R. I was told some time ago that CUPL later withdrew support for the VIRTUAL device in their base tools, allowing it only in their $2500 "FPGA" version which also has direct XNF output. Clearly their marketing department determined that someone using FPGAs has a budget several times bigger than someone using ordinary PLDs. Now, where have we noticed that before?? Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5907
I am using a 4013pg223 and 16K X 8 EPROM to make a master parallel up mode. When during configuration, the address counter count to 400e and the data frame error occur and the INIT pin to low forever. After reprogram, the error still occur. I just connect the address pin A0 - A13 to EPROM. A14 - A17 is float. Does it right? Email: lhkwong@netvigator.comArticle: 5908
Samir Marc Falaki wrote: Hi, I am by no means posting this article to put Mentor but I thought this was too funny. I use Mentor and find that I always come across problems requiring patches or work-arounds for some reason. If it's not that, it's problems with paths and pointers pointing at pointers pointing etc... Anyhow, I made a request for the free evaluation of "Renoir" which I thought I could run on my mom's PC. I thought that it would probably be straightforward to use. Today I got a demo CD. They send you this CD first, and then you ask for the evaluation kit. Well, the demo CD installs fine but when I run it I get some kind of "invalid date" error right from the start (something to do with a .ilm file). I said to myself, "ahh yes, Mentor". If the demo CD doesn't work, how do they expect people to have confidence in their software? What the hell are they doing at Mentor? They have all these powerful tools but they always have these stupid little problems. Sam Please read the release notes (see below). The demo CD "is" the evaluation kit. You may want now a full authorization code. Please let us know. Best regards Paolo Spazzini Renoir Product Marketing Manager ======================================================= Extract from the Release Notes ======================================================= Licensing Errors on PC Systems Renoir Release Notes 18 February 1997 Licensing Errors on PC Systems The following error message may be displayed on Windows NT systems if the decimal symbol is not set correctly: ilm: Views: invalid expiration date ".200" in "C:\\WINDOWS\TEMP\ilog2 If this error is issued, use the Number tab in the Regional Settings control panel (which can be accessed from the Settings option in the Windows Start menu) to ensure that the decimal separator is set to “.”Article: 5909
hi, the subject may seem silly but it is not. previously, i had posted a question about viewoffice <--> viewoffice file compatibility. i have run some tests and found that for a viewoffice system derived from a pro series license (bought from actel) and a viewoffice system derived from workview plus (bought from viewlogic) could not exchange schematic files representing an actel fpga design. i have e-mailed viewlogic a bunch of times on this, sent license files, asked what restrictions and capabilities there are for each of the licenses, and the answer i have received to solve this problem is between the square brackets, two lines below this one: [] so, do any experienced viewlogic users/customers/fae's/critics/supporters/abusers/whateverers have any ideas? i now have 3 viewlogic seats networked together (pc's derived from workview plus) and two dormant actel-bought/derived viewlogic licenses and need to activate them as we have 1 or 2 new designers joining. what do i do? i don't mind paying the required maintenance fees and all but i need to have each of the designers' systems being compatible with one another. having all of the seats being viewlogic and the same revision seemed initially to be a good idea. has anyone tried this before? did my pc have a bad hair day? any thoughts or advice? thanks, rkArticle: 5910
Stuart, I've received mine in a day, or even that very same day I call... You may want to give them a call... They could e-mail it to you...since you are not quite down the road... Austin Franklin ..darkroom@ix.netcom.com. Stuart Summerville <stuart.summerville@practel.com.au> wrote in article <333169f3.256884@news.on.net>... > Hi all, > > I've now been waiting for 1 week to receive my license.dat file from > Viewlogic for Workview Office. Am I being too impatient, or are > Viewlogic either slack in customer support or inefficient in supplying > presumably basic license details....? > > Stu. > --------------------------------------------- > Stuart Summerville > Project Engineer > Practel International > 442 Torrens Road, Kilkenny, SA 5009 > Tel: (61.8) 8268 2196 Fax: (61.8) 8268 2882 > Email: stuart.summerville@practel.com.au > --------------------------------------------- >Article: 5911
I am with Human Resources for the Small Internetworks Business Unit (formerly Grand Junction) at Cisco Systems. We develop switches, routers, and hubs that focus on small and medium-sized companies. Revenue-wise we are the fastest growing Business Unit at Cisco Systems with 30+% growth over the last five quarters. We are currently looking for senior and intermediate ASIC Engineers (digital) as well as senior and intermediate Systems Engineers (embedded CPU, FPGA) to join our team. We are located in San Jose, California. If you, or anyone you know is interested, please contact me or send me your resume. I will be happy to talk with you further about the positions. To send your resume: fax: 408-527-8048 or email: lshevock@cisco.com No agencies please -- To send your resume: fax: 527-0180 or email: lshevock@cisco.com No agencies pleaseArticle: 5912
We had a semi-informal get-together at last year's FCCM, to work
up a list of predictions for 'FPGA computing' five years hence.
(Credit to the CANDE workshop for originating such things, so far
as I know, anyway.)
Semi-informal in that it was moderated and organized, but with
plenty of Casselbrau, good Napa Valley wine and general high
spirits around. Several sub-groups each came up with their lists,
which we then rolled up into this list by raving and voting. A good
time was had by all. Nearly a year into the five years, I'd say
the list is holding up pretty well.
We'll try and organize something similar for this year. Be sure
to attend! If you are at all serious or even curious about
reconfigurable
hardware computing, FCCM is the place. http://www.fccm.org
Looking forward to seeing you all there!
--Mike Butts
---------------------------------------------------------
FCCM '96 Top Ten Predictions on FCCMs in 2001
13: It didn't fit.
12: FPGAs used in FCCMs will have 4-LUTs, FFs
and not enough routing.
11: FCCM apps will be downloaded from the Internet
a'la Java.
10: FPGAs used in FCCMs will have embedded
functional units.
9: Microprocessors will have FPGA logic
(for x86 emulation ;-), but not in the API.
8: Dynamic FPGAs with on-chip DRAMs in FCCMs.
7: Time-sliced FPGAs will be commercially
available, and used in FCCMs.
6: FCCM languages will be
Visual Verilog++tm, gcc, and Matlab.
5: Top 3 application areas will be communications,
military, image processing, and
one we don't know of today.
4: $100M/year FCCM industry with
two public companies.
3: FCCM '01 will have 1K attendees and
a 100 vendor trade show.
2: 50% of the 1996 DARPA goals* will be met.
1: We will hate the tools.
*
http://www.ito.darpa.mil/ResearchAreas/Adaptive_Computing_Systems/ACS_16.html
Article: 5913You are only half way there :-) The XC4013 requires a bitstream of 247960 bits (30995 bytes), so a 16K byte EPROM just isn't going to make it. You need at least a 32K EPROM, and need to be using A0 thru A14. The address that you are failing at (0x400E) is the first end of frame that the chip sees after it has wrapped around to the beginning of your 16K EPROM. The CRC is wrong, and the INIT pin is telling you so. For bitstream length, see page 2-26 of the 1994 data book, or 4-57 of the 1996 data book. Thanks for stating your problem so clearly. It makes helping you an easy thing to do. Philip Freidin In article <01bc392f$62f809c0$9d638bd0@kwonghei> "kwong lau hei" <lhkwong@netvigator.com> writes: >I am using a 4013pg223 and 16K X 8 EPROM to make a master parallel up mode. >When during configuration, the address counter count to 400e and the data >frame error occur and the INIT pin to low forever. After reprogram, the >error still occur. >I just connect the address pin A0 - A13 to EPROM. A14 - A17 is float. Does >it right? > >Email: lhkwong@netvigator.com >Article: 5914
Dodderin' Ol' Don < wrote: > > Welcome to the web ... I've added your website to my directory and as soon > as my ISP clears up their security problems I'll upload the new pages. P.S. > tell your web-folks to include a way to turn off the dang frames ... some > folks love 'em, some hate 'em, and some web browsers can't hack 'em once you browse a site that effectively uses frames, you'll see what you've been missing. it becomes so much easier to find what you're looking for on a frame site than on a non-frame site. because we don't want to double our workload and create multiple identical sites (frames and non-frames), we decided just to go with a frame site (anticipating that just about everyone will have a frames-capable browser on their computer in the near future), however, if you don't have a frame-capable browser, you are pointed upon entry to a "synopsis" page with direct access to our product literature (data sheets and application notes and all the rest of the "goodies") in PDF format. you should still find the site useful even if you don't view it using frames. > -- > Electronics Resource Page at > http://homepage.dave-world.net/~donw1948/index.html > > webmaster <webmaster@summitmicro.com> wrote in article > <33375F49.4C9A@summitmicro.com>... > > We'd like to announce that SUMMIT Microelectronics website is now OPEN! > > > > http://www.summitmicro.comArticle: 5915
Chris Wright wrote: > > In article <01bc38e6$3bb9d800$09021ace@rickweis>, Dodderin' Ol' Don > <?@usa.net> writes > >Welcome to the web ... I've added your website to my directory and as soon > >as my ISP clears up their security problems I'll upload the new pages. P.S. > >tell your web-folks to include a way to turn off the dang frames ... some > >folks love 'em, some hate 'em, and some web browsers can't hack 'em > > <soapbox> > > I agree! I find it annoying that web page > designers make their pages inaccessible to > part of their potential users by putting all > the latest bells and whistles on them. frames is at least 1 year old technology now, so I wouldn't say that it's the latest bell or whistle :-) > > Whilst it is OK to want to make your site as > attractive as possible, have some way for > people using older browsers and slow connections > to use them. I have only a 9600 connection > because the 'phone lines out here in rural > Herefordshire (England) are not good enough > (I have a 28.8 modem!), and when I use the > web it is with Netscape 1 something with > images switched off. I get the impression > that a lot of web page designers never > take the trouble to look and see what their > work looks like when used in this way!! if you can't access our site because your browser doesn't support frames, then you'll still get pointed to a synopsis page which allows you to download our data sheets and get other product information. we're trying to make access to our site universal, but for reasons of efficiency and appearance, we chose to limit ourselves to a frames site with minimal superfluous pictures. it loads pretty fast and should be easy to navigate and find what you want. > > Assuming that you think the information on > your site is worth looking at :) - isn't it > worth taking the trouble to make it available > to the greatest number of people? > > </soapbox> > > -- > Chris Wright > Rolt Manufacturing Ltd > ki11@cityscape.co.ukArticle: 5916
I don't work for Viewlogic, I have never worked for Viewlogic, I once owned shares in Viewlogic (and I think I lost money or broke even when I sold my shares), Viewlogic didn't ask me to post this. (is that sufficient disclaimers??) Like many who have been posting on this group, I have been suffering with the new VL tools under NT, and have been annoyed at how the new tools (in particular ViewDraw) are more difficult to use, and I am far less productive with them than with the old DOS version of the programs. Every time someone posts a message here about problems with the Workview Office product, I have forwarded it directly to someone at VL, in case they don't read this group. I also have sent my bug reports/wish list stuff to them. The biggest draw back with the NT versions were: No Command line No key rebinding Unstable No Macro Commands Help System Well, I've been playing with the new version 7.31, and I like what I see. The command line is back!, and has most of the functionality of the old version. Combined with hotkeys, it is fairly useable. It also doesn't crash (well not in several days of use). Given how long this software has been out since its first release, and the incremental releases every 3 or 4 months, I am really impressed at how they have responded to user input. (contrast this to another vendor I have some experience with, who seems to totally ignore all input from users about the importance of backward compatibility to prior generations of tools.) Here's whats left to do (assuming someone from VL reads this post): 1) Finish off the few commands that still don't work on the command line. 2) Let me alias strings to various keys, including ctrl, shift, alt versions of F1 .. F12, insert, home, page up/down, delete, end. Let me over-ride the standard bindings too. 3) Give me back the mex command, (and macro and mclose). 4) Keep working on the help system. It is now fairly good, but I still can't find things. I.E. while I'm in viewdraw, how do I find out the the names and meanings of all the @values on a FF primative? Where is the documemtation on creating arbitrary sized RAMs or ROMs, Where is the documentation on how to use the OLE interface (with examples?) 5) I still want a hard copy of the documentation. The hypertext help that keeps poping open windows of variable size all over the screen is not conducive to learning how to use the product. Other than that, thanks for command lines in V7.31 Philip Freidin A Viewlogic sw user.Article: 5917
In article <3338B6B7.7296@summitmicro.com>, webmaster <webmaster@summitmicro.com> writes >however, if you don't have a frame-capable >browser, you are pointed upon entry to a "synopsis" page with direct >access to our product literature (data sheets and application notes and >all the rest of the "goodies") in PDF format. you should still find the >site useful even if you don't view it using frames. > That's absolutely fine - I wasn't asking for any more than for there being a way for me to be able to get the info. Just give some alternate way for people with the most basic equipment to get in :) Remember, not everyone out there has Pentium PCs, there are people using all sorts of systems to access the 'net, some of which are short on memory and disc space. -- Chris Wright Rolt Manufacturing Ltd ki11@cityscape.co.ukArticle: 5918
In article <01bc392f$62f809c0$9d638bd0@kwonghei>, "kwong lau hei" <lhkwong@netvigator.com> wrote: > I am using a 4013pg223 and 16K X 8 EPROM to make a master parallel up mode. That combination cannot possibly workThe XC4013 needs 247,960 configuration bits, and the 16kx8 EPROM can hold barely half of that. Get a bigger EPROM, and also make sure you are consistent regarding incrementing or decrementing addresses ( Master Parallel UP or Master Parallel DOWN ) We document the number of bits clearly in our data book: page 2-26 in the 1994 and earlier books, page 4-57 in the 1996 book. Peter Alfke, Xilinx ApplicationsArticle: 5919
In article <fliptronE54JCK.Cp@netcom.com>, fliptron@netcom.com (Philip Freidin) wrote: >In article <5d5gjt$165b@watnews1.watson.ibm.com> kgold@watson.ibm.com (K > Goldman) writes: >> >>fliptron@netcom.com (Philip Freidin) writes: >>|> The reason is that the storing of a reference CRC value on chip will >>|> permute the calculated CRC. If you then change the reference value to the >>|> new value, it will just permute again. I suspect you may be able to play >>|> this silly game forever. >>There are ways to append a generated CRC to a serial bit stream such >>that, when the receiver checks the total CRC including the generated >>CRC, a _constant_ magic number results when there are no errors. >>Ken Goldman kgold@watson.ibm.com 914-945-1466 > >This wont work in this case because the adding of the check value to the >logic in the FPGA will permute the CRC so it will not match. There is no >facility for adding a check value that does not cause this permutation to >take place. Really. If you want to check the bitstreams this way, you will >have to store the calculated CRC outside the FPGA. The actual compare >logic, and the timing and counting logic can be in the FPGA. > >Philip. > I'm not sure exactly what you're all saying, but I think Ken is right, and the others are wrong, and I *know* this following is true, because I've done it: If you have a bitstream xxxxxxxxxxxxxxxxxxxxxxx aaaa yyyyyyyyyyyyyyyyyyyyy Where the 'a' field is, say, 32 bits you can change to anything you like, then you can (1) calculate a 32-bit CRC on the whole thing (2) XOR that with the CRC you *want* to have (3) transform the result of step 3 (4) xor the aaaa field with the result of step 4 Step 3 is the tricky part. Briefly, a 32-bit CRC register acts as multiply by a fixed 32x32 GF(2) matrix, the determinant of which is 1; you simply invert this matrix and raise it to the n-th power (where n is the sizes of the aaaa and yyyyyyy fields combined). Step 3 is then a multiplication by this matrix. It's not even very computationally intensive. In fact, it can often be done even if the 32 'a' bits are distributed throughout the codeword. You find the 32-bit contribution of each changeable bit to the final CRC result, and invert the matrix they form. This matrix may be singular - this happens when the 32 changeable bits correspond to an error pattern undetectable by the CRC - in which case you can't use that pattern. Greg Smith gsmith@passport.caArticle: 5920
In article <Ayx4JFA1XPOzEwWD@cityscape.co.uk>, Chris Wright <ki11@cityscape.co.uk> wrote: >In article <3338B6B7.7296@summitmicro.com>, webmaster ><webmaster@summitmicro.com> writes >>however, if you don't have a frame-capable >>browser, you are pointed upon entry to a "synopsis" page with direct >>access to our product literature (data sheets and application notes and >>all the rest of the "goodies") in PDF format. you should still find the >>site useful even if you don't view it using frames. >> >That's absolutely fine - I wasn't asking for any >more than for there being a way for me to be >able to get the info. Just give some alternate >way for people with the most basic equipment >to get in :) > >Remember, not everyone out there has Pentium >PCs, there are people using all sorts of >systems to access the 'net, some of which >are short on memory and disc space. > >-- >Chris Wright >Rolt Manufacturing Ltd >ki11@cityscape.co.uk -------------------------------------------------- StrongAgreeMsg!! Try using an XT with 640KB and a Hercules-type mono display on a UNIX shell account using Lynx 2.6 to try to navigate shells! I think people who do frames should create alt= paths for non-NutScrape folks and remain/retain alt=Lynx compatibility! Up to half the Net is using these old pre-NutScrape machines with shell accounts! That's a dirty little status secret about the Info Super Highway, that there are lotsa "elite" stretches of highway that YOU PAY for!! And every PDF SHOULD fucking well have a text plus .gif download at LEAST!! Howabout a menu for which ever compatibility you need when you land on your root page, eh??? -Steve -- -Steve Walz rstevew AT armory.com http://www.armory.com/~rstevew/ -Lots of New FTP Electronics Stuff!! 900 Files/45 Dirs (Full Mirror ==> *) -- -Steve Walz rstevewATarmory.com ftp://ftp.armory.com:/pub/user/rstevew * Europe:(Italy) ftp://ftp.cised.unina.it:/pub/electronics/ftp.armory.com * Oz:.AU ftp://ftp.peninsula.apana.org.au:/pub/electronics/ftp.armory.com * (U.Cinci) ftp://ieee.cas.uc.edu:/pub/electronics/mirrors/ftp.armory.com *Article: 5921
ANNOUNCEMENT: MODEL AND TIP OF THE MONTH ++++++++++++++++++++++++++++++++++++++++ The Winning Edge at www.doulos.co.uk has been updated with the latest VHDL/Verilog Model and Tip. This month's model is: A Universal Asynchronous Receiver (in Verilog) This month's tip is: Synthesizing "+" (using VHDL) You can find both at http://www.doulos.co.uk You can also access previous Models and Tips of the Month from the same site. ____________________________________________________________________ Also *** NEW *** for this month are the latest updates to: A Hardware Designer’s Guide to Verilog A Hardware Engineer’s Guide to VHDL _____________________________________________________________________ DOULOS Church Hatch Tel: +44 1425 471 223 22 Market Place Fax: +44 1425 471 573 Ringwood BH24 1AW Email: webmaster@doulos.co.uk UK _____________________________________________________________________Article: 5922
In article 8DC@uqtr.uquebec.ca, Samir Marc Falaki <Samir_Marc_Falaki@uqtr.uquebec.ca> () writes:
>Hi,
>
>I read somewhere (one of Ray Andraka's articles I believe) about using
>bit serial multiply to implement a tap filter on an FPGA. What I don't
>quite understand is how one can impose an architecture into an FPGA
>when using high level tools. I implemented a 16X16 bit multiply
>today via behavioural VHDL on Synopsys and got about 120 CLB usage
>for a 4010 Xilinx device. Any tips would be appreciated and on
>implementing signal processing algorithms on FPGAs in general. Thanks
>in advance.
>
>Sam Falaki
Here's an example of one from a recent design. Basically, describe the registers
and the dataflow between them. Everything is controlled with a LFSR.
--alu_m1.vhdl
--
--include header.h
--include_alpha
--Copyright 1997 Rockwell International Corporation
-- Collins Avionics & Communications Division
-- 350 Collins Road NE
-- Cedar Rapids, IA 52498
--
--Program Information
---------------------
-- deleted
--
--ASIC/FPGA
------
-- Keokuk
-- Technology: Altera Flex-10K
--
--include_omega
--This calculates F_DIAL * 1000000 (hF42240) where the 1000000 is a scaling factor
--to convert F_DIAL from Mhz units to Hertz units
--
--The max result (for 399.99875 Mhz) is
--
-- 319999000000 (h4A816D3DC0) = 319999 (h4E1FF) * 1000000 (hF4240)
--
--which is a 39 bit result.
--
--
--This code implements a serial mutiply circuit with the following architecture
--
-- 0 OP_A
-- | |
-- V V
-- +----------+
-- | 0 1 |
-- | Mux |
-- | |<------------------------------+
-- +----------+ |
-- | "hF42240" |
-- V | |
-- +--------------->(+) 21 bit adder/accumulator | |
-- | | | |
-- | V V |
-- | +----------------------------------------+ |
-- | '0' ->| Accumulator | Answer |--+
-- | +----------------------------------------+
-- | | \|/ sr(1) -->
-- +-----------------+ |
-- V
-- RESULT
--
library ieee;
use ieee.std_LOGIC_1164.all;
library compass_lib;
use compass_lib.compass.all;
entity ALU_M1 is
--include alu_m1.io
--include_alpha
port(CLRF : in std_logic; --async clear, active low
CLK : in std_logic; --rising edge clock
START : in std_logic; --1: begin mutiply, 0: continue
OP_A : in std_logic_vector(18 downto 0);
RESULT : out std_logic_vector(38 downto 0)
);
--include_omega
end;
architecture a1 of ALU_M1 is
--Constants
-----------------------------------------------------------
constant prop_delay : time := 1 ns;
signal add_result : std_logic_vector(19 downto 0);
signal accum, n_accum : std_logic_vector(19 downto 0); --one extra stage for accumulator overflow
signal k_hF4240 : std_logic_vector(19 downto 0); --one extra stage for accumulator overflow
signal answer, n_answer : std_logic_vector(19 downto 0);
signal mux_out : std_logic_vector(19 downto 0);
signal lfsr, n_lfsr : std_logic_vector( 5 downto 0);
signal mux_in : std_logic_vector(19 downto 0);
signal tmp : std_logic; --just go keep vlogic happy
component add_20
--include add_20.io
--include_alpha
port(OP_A : in std_logic_vector(19 downto 0); --operand
OP_B : in std_logic_vector(19 downto 0); --operand
RESULT : out std_logic_vector(19 downto 0) --result
);
--include_omega
end component;
begin
--define constants signals (for viewlogic)
-----------------------------------------------------------
k_hF4240 <= "11110100001001000000"; --one extra stage for accumulator overflow
tmp <= lfsr(5) and lfsr(4) and lfsr(3) and lfsr(2) and lfsr(1) and lfsr(0);
--Internal to external port assignments
-----------------------------------------------------------
RESULT <= accum(18 downto 0) & answer;
mux_in <= '0' & OP_A;
mux_out <= mux_in when answer(0) = '1' else "00000000000000000000";
u0: add_20 port map(OP_A => accum, OP_B => mux_out, RESULT => add_result);
sync: process(CLRF,CLK) --rising edge, async reset ff's
begin
if CLRF = '0'
then accum <= "00000000000000000000";
answer <= "00000000000000000000";
lfsr <= "110111";
elsif CLK'event and CLK = '1'
then accum <= n_accum after prop_delay;
answer <= n_answer after prop_delay;
lfsr <= n_lfsr after prop_delay;
end if;
end process;
comb: process(START,OP_A,accum,answer,add_result,lfsr,k_hF4240)
begin
--defaults
-----------------------------
n_lfsr <= lfsr; --This is required because of a viewlogic bug
if START = '1' --begin processing
then n_accum <= "00000000000000000000";
n_answer <= k_hF4240; --answer is used to control the mux
n_lfsr <= "000001";
elsif lfsr = "110111" --done processing, hold values
then n_accum <= accum;
n_answer <= answer;
n_lfsr <= "110111";
else n_accum <= '0' & add_result(19 downto 1);
n_answer <= add_result(0) & answer(19 downto 1);
n_lfsr(5 downto 1) <= lfsr(4 downto 0);
n_lfsr(0) <= lfsr(5) xor lfsr(0);
end if;
end process;
end;
---
============================================= \ /
Russ W. De Hoedt Phone: 319-295-3063 \ _ /
Rockwell Fax: 319-295-4550 _________\_( )_/__________
E-mail: rwdehoed@cca.rockwell.com. \_( o )_/
============= ASICS - R - US =============== \_/
library rockwell; use rockwell.disclaimer.all Check Six!
I speak only for myself, not Rockwell.
Article: 5923Consultant Needed We are a technology research firm in immediate need of another synthesis or simulation-savvy consultant. We are particularly interested in finding somebody with good knowledge in: * ASIC/FPGA implementation and design flows * synthesis/simulation vendors * Marketing/sales experience a plus The pay is good, the work is fun, and we need you now. We don't care where you live, as long as you are in North America. All work is contract, from your home/office. You must have available time during business hours (evenings/weekends won't work). We have two projects: * one contract is for about two weeks work during the next month, with options to extend through end of the year. This project involves logic synthesis tools *We have another project that will run through early summer. This project involves Intellectual Property (IP) and sub 0.35u design. All work involves conducting telephone interviews with technical staff at various companies, analysis, and some simple report writing. Excellent communications skills are required, so please DO NOT email your response-I need to talk to you directly. Please call toll-free 800-298-2982 any time. We expect to staff this project by April 2, so call soon! Thanks! Dave Millman http://www.tactics.com/Peer_Research/index.htmlArticle: 5924
I am a graduate student majoring in Computer Engineering at Texas A&M University.I will be graduating in August-September 1997. I am looking forward to a digital design job which will help me establish a career in the semiconductor industry. I have good knowledge of Verilog and also worked on Simulation tools like Cadence and Synopsis. I have also done projects on microprocessor design : 1. Behavioural modeling of the DLX architecture based microprocessor(32 bit) using Verilog. 2. Complete design of a 16 bit microprocessor from a given architecture model using Cadence Design tools. Other projects are in resume. Attached is my resume in postsript format. thanks for your time Sincerely Name Deleted. __________________________________________________________________ Undertake something that is difficult,it will do u good; Unless u try to do something beyond what u have already mastered you will never grow -:Ronald E Osborn __________________________________________________________________ Name Deleted Graduate Assistant Teaching Dept of Electrical Engineering tel:(409)-5551212 Texas A&M University email:Name_Deleted@tamu.edu ___________________________________________________________________ ** ____________________________________________________________________
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