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In article <33245D4C.2811@ids.net>, Ray Andraka <randraka@ids.net> wrote: there was an app note in the 1994 Xilinx data book on building a > deep fifo using DRAM. Perhaps you can use that for some hints. I > beleive that design used an LFSR for the address counters and a cute > shift scheme to get the row and column addresses. > I was the one who came up with this addressing trick in 1989, but it really works only for FIFOs where the binary address sequence is irrelevant, as long as write and read port follow the same sequence. Memories of a distant past... The additional question is refresh of the DRAMs. If the refresh requirement is anything like it was in the olden days, you need to at least control it, at worst even apply part of the refresh address. That again chews up a few CLBs. But the whole design is not very complicated. Peter Alfke, Xilinx ApplicationsArticle: 5726
In article <qDednAArrEJzMA5V@vizef.demon.co.uk>, steveb@vizef.demon.co.uk says... > In article <5g176i$694$1@info1.fnal.gov>, Don Husby <husby@fnal.gov> > writes > >Renoir Support renoir@em-wv03.wv.mentorg.com wrote: > >> Introducing Renoir for VHDL/Verilog Graphical Entry Starting to sound like the "Teenage Mutant Ninja Tools"....Article: 5727
Based on the most common reccomendation I have decided to try out
ModelTech's V-System for Windows NT, which should arrive sometime this
week. Thanks for your input and replies to my post.
BTW: I was actually using the View Logic tool chain before trying out Warp
4.1, but since they ported it to windows it has just got sucessively worse.
I didn't even bother upgrading...
--
- h
<< return address is bogus, getting spammed too much - henry at odo dot com
>>
Article: 5728
In article <331DD299.7A28@emf.net>, Brad Taylor <blt@emf.net> wrote:
>> Does this realization mean that Xilinx will be releasing documentation on
>> the contents of its bit streams? ... No, I'm not seriously expecting it...
>
>I'm just curious. What would you do with it? (the bitsream information)
Freely-redistributable programming software. Distributed free, in source
form, portable to any POSIX environment, with no copy protection. At least
for starters, something very simple in which the user has to do almost all
the work -- a tool for people who can spare time more than cash, and are
willing to do placing and routing themselves to save money.
It's not like I don't have *enough* projects to fill my copious spare time
already, but this one would be very much worth doing. Alas, it does require
not just access to the bitstream info, but public release of same.
--
Committees do harm merely by existing. | Henry Spencer
-- Freeman Dyson | henry@zoo.toronto.edu
Article: 5729
In article <33208CDD.4563@xilinx.com>,
Eric Dellinger <ericd@xilinx.com> wrote:
>Why do you want the bitstream format? Do you really
>need the bitstream itself, or can you settle for
>inexpensive or free means of controlling the
>contents of the bitstream? Is the real issue
>the cost of tools, or do you need quicker
>ways than guided ppr to munge the bitstream?
Six of one and half a dozen of the other. The cost of the tools could
certainly stand to be reduced. However, I'm also interested in things
that want to do dynamic reconfiguration, where *my* software has to be
able to generate the bitstream -- selecting among a handful of pre-built
possibilities, or telling the user to carry a floppy over to an MSDOS
machine, wait two hours, and carry it back, is not good enough. (This
is not an Official Project of a Big Institution, so the usual "we can
negotiate a special deal, provided your name is Thomas Edison" is no help.)
--
Committees do harm merely by existing. | Henry Spencer
-- Freeman Dyson | henry@zoo.toronto.edu
Article: 5730In comp.lang.verilog Renoir Support <renoir@em-wv03.wv.mentorg.com> wrote: : Introducing Renoir for VHDL/Verilog Graphical Entry : Full information on a brand new HDL graphical entry tool can be found : at: : http://www.renoir.com/ : You can also download an evaluation copy for Windows, SUN and HP : platforms. Will there be a version for Linux too? -- Uwe Bonnes bon@elektron.ikp.physik.th-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 5731
Uwe Bonnes wrote: > > In comp.lang.verilog Renoir Support <renoir@em-wv03.wv.mentorg.com> wrote: > > : Introducing Renoir for VHDL/Verilog Graphical Entry > > : Full information on a brand new HDL graphical entry tool can be found > : at: > > : http://www.renoir.com/ > > : You can also download an evaluation copy for Windows, SUN and HP > : platforms. > > Will there be a version for Linux too? > And AIX 4.1 perhaps...? -- Nick Weavers, IBM SSD, Havant, PO9 1SA, UK. e-mail: weav@hursley.ibm.com Tel: 011-44-(0)1705-486363 ext 5121 Fax: 011-44-(0)1705-499278Article: 5732
I read your replies about instantiation and maybe you have an answer to my problem. I know that a hdl description in Synopsys can instantiate (for synthesis) XILINX primitives and designs generated with xbloxgen or memgen, . My question is: How can these designs, generated with xbloxgen and memgen, be simulated in Synopsys. I think that instantiation is useless if their behavior cannot be simulated before place and route.Article: 5733
hi, i have upgraded a bunch of viewlogic 'seats' to the viewoffice stuff and got them all at the exact same revision. seems like a good idea. now, some seats were upgraded from workview plus and others from pro series. this REALLY seems like a good idea since at one time i was using three different user interfaces during the 'transition' phase and while waiting months and months for s/w and correct license files. anyways, now that they are all the same, i am having trouble (like can't do it) reading files on 'heritage' pro series seats from former workview plus seats, although they are just simple schematics that i can easily create on either computer. and going from the former pro series to the former workview plus seems to work just fine. suggestions? comments? thanks for any help, rkArticle: 5734
suzanne M southworth wrote:
>
> Jim,
>
> It's a tool developed by Mentor Graphics.
^^^^^^^^^^^^^^^^^^
by Exemplar
Rudi
Article: 5735Our office has a limited number of licensed PC/Windows viewlogic 'seats', and we often have people being locked out while other users are not actively using the tools (but have it up on their PC). My question is how to have the VL software on our server pass some information down while locking out the extra users, specifically so someone can call other users to see if they can close the VL tool down if not actively in use... Currently, we all have to phone around the building to search for the available 'seats'. Thanks in advance, Dan Alley Xetron CorporationArticle: 5736
Christos Dimitrakakis wrote: > > I am considering the usage of a Xilinx FPGA as a DSP chip that also > controls memory access to a single SIMM. The FPGA will be the only > device accessing the memory. > Are there any app notes/example designs on using the Xilinx as memory > decoders? > Furthermore, I have no knowledge of SIMM operation, so if anyone could > fill me in on that I would be very grateful :) > -- > Christos Dimitrakakis > --------------------- > mailto:mbge4cd1@fs4.eng.man.ac.uk > mailto:mbge4cd1@afs.mcc.ac.uk > http://www.man.ac.uk/~mbge4cd1 SIMMs typically have timing spec's identical to the parts with which they're built, which are generally DRAMs, although SRAM SIMMs are also available. If you are using DRAM SIMMs and doing DSP inside the Xilinx, you may find that your throughput is limited by the high access penalty attached to the RAS (Row Address Strobe) and RAS precharge sections of the memory cycle. To overcome this, pay close attention to data formats in memory, and try to keep your algorithms structured so that the DRAMs may be operated in Fast Page Mode most of the time. If the data is structured in blocks spread across different row of memory, Fifo's can be built inside the Xilinx to buffer data between memory and your processing engine. -- John L. Smith Univision Technologies, Inc. 6 Fortune Drive Billerica, MA 01821-3917 jsmith@univision.comArticle: 5737
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Article: 5738szamos wrote: < Eric Dellinger (ericd@xilinx.com) wrote: < : < : [I had written a lengthy posting espousing my < : personal philosophy that Xilinx should provide < : freeware for programming the parts, < < Do you mean the software just to download the config data into < the FPGA's, or you mean the whole development system? The former, at the very least. Preferably the latter. ==ericArticle: 5739
In a previous article Henry Spencer <henry@zoo.toronto.edu> writes: : ;In article <331DD299.7A28@emf.net>, Brad Taylor <blt@emf.net> wrote: :>> Does this realization mean that Xilinx will be releasing documentation on ;>> the contents of its bit streams? ... No, I'm not seriously expecting it... :> ;>I'm just curious. What would you do with it? (the bitsream information) : ;Freely-redistributable programming software. Distributed free, in source :form, portable to any POSIX environment, with no copy protection. At least ;for starters, something very simple in which the user has to do almost all :the work -- a tool for people who can spare time more than cash, and are ;willing to do placing and routing themselves to save money. : ;It's not like I don't have *enough* projects to fill my copious spare time :already, but this one would be very much worth doing. Alas, it does require ;not just access to the bitstream info, but public release of same. One question is does the biggest customers of Xilinx want to be challenged in their market by a swarm of little guys armed with free or affordable softwares? It is all market driven, even though at times the strategy may seem counter-intuitive to some of us. Another example -- why isn't PCI spec designed so to make it easy to build a high-performance interface out of FPGA (eg, IRDY and TRDY should have been made to mean readiness to transfer data in the NEXT clock cycle). Could it be that the consortium members want no challenges from those who are not big enough to do hardwired gate arrays?Article: 5740
Richard Schwarz wrote: > > Anybody had any experience with the ACTEL RAM BASED FPGAs? I have heard that there are several beta customers in the US, testing this new technology and its new design software, but I believer no parts are commercially available yet. Please refer to the ACTEL homepage (http://www.actel.com) for the latest news. > I think this is a smart move on their part but haven't heard much about them. I fully agree with you. I believe this technology will be the first SRAM-based technology on the marktet having a fine-grained (synthesis-friendly!) architecture. I'm very curious what ACTEL comes up with within the next few months. P.S. I am NOT an ACTEL employee, but our company has been using ACTEL anti-fuse technology, as well as XILINX and ALTERA SRAM-based technology. Best regards, Jaap Mol > > Richard SchwarzArticle: 5741
Uwe Bonnes wrote: In comp.lang.verilog Renoir Support <renoir@em-wv03.wv.mentorg.com> wrote: : Introducing Renoir for VHDL/Verilog Graphical Entry : Full information on a brand new HDL graphical entry tool can be found : at: : http://www.renoir.com/ : You can also download an evaluation copy for Windows, SUN and HP : platforms. Will there be a version for Linux too? -- Uwe Bonnes bon@elektron.ikp.physik.th-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- At the moment there are not plan for a Linux version of Renoir. thanksArticle: 5742
Hi, I was wondering if anyone has had this problem with XACT under Windows 95. We get a system error and have to reboot the PC. We are running on a Dell Pentium 133 system with 32MB of memory. The version of XACT is v6.0.1. This happens when we try to "implement" from an XNF file. The error message: Fatal Exception 0D occurred at 00a700000c9e And then the PC hangs. Has anyone seen this before or offer any suggestions? Please reply to shantanu@ece.neu.edu. Thanks! Shantanu...Article: 5743
We are currently using ViewSynthesis and ViewPLD for FPGA and PLD/CPLD designs. We find ViewSynthesis optimizes the Xilinx FPGAs very poorly and ViewPLD is buggy, unstable, and poorly supported. I would be very grateful for any feedback on the following products: 1) Exemplar 2) Synario 3) Minc (PLD/CPLD) + Synplicity (FPGA). I have done some benchmarking on Synplicity and found that it optimized better then ViewSynthesis, but I'd prefer a unified VHDL/ABEL solution. I also must say that I have a GREAT prejudice against Synario. I have found DataIO support to be on a par with VIEWlogic, that is to say horrible. I also have doubts about DataIO's commitment to EDA products. Does any one remember FutureNet/Gates? For these reasons I find my self leaning to Exemplar but only because I know next to nothing about them. Ignorance is, after all, bliss. Your feedback is eagerly anticipated. ToddArticle: 5744
Jaap Mol wrote: > I fully agree with you. I believe this technology will be the first > SRAM-based technology on the marktet > having a fine-grained (synthesis-friendly!) architecture. I'm very > curious what ACTEL comes up with > within the next few months. Atmel has had a fine-grained SRAM based FPGA on the market since the early '90s. The AT6005 has 3136 cells. Each is basically a half adder with a register on the sum output and a couple of and gates and muxes to allow most 2 and a few 3 input functions. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 5745
Stuart Summerville wrote: > I am trying to fit a current design into an XC5204-160PQ. I am > curious as to how much other designers utilise the I/O capabilities of > pins used in the configuration sequence of such devices. > > so far I have managed to restrict usage of I/O pins to dedicated I/O > pins, but I'm not really sure how far I should go in also using the > multi-purpose ones. > > Thanks for any advice. You can be sure that the guys who designed the chip had your problem in mind. Nobody wants to waste pins. In the XC2000 and XC3000 the PROGRAM and DONE function were even combined in one pin, which may not have been so smart but it demonstrates the concern. So, we care. And we describe the pin function very carefully. Please read the appropriate page, in your case it is 4-197. Which pins are critical depends on the configuration mode, with Master Serial being the least restrictive. If you use the mode pins as outputs during the normal operation, then you can easily, for configuration, establish the Low level with a pull-down resistor ( make it 2.7 kilohm to get a nice low voltage ) Aside from a little wasted current, these resistors cause no harm during operation. HDC and LDC may of course not be driven during configuration ( to be precise: they may not be driven the wrong way ), so it makes sense to use them as outputs later on. RDY/BUSY, RCLK,CS,WS,RS,the 18As and the parallel data inputs are all 3-stated with weak pull-up, like all the other I/Os. DOUT is active and DIN is being driven during configuration, so they are best used as outputs during system operation. These recommendations assume that you don't use external multiplexers or Quickswitch devices. With them, full flexibility is restored. So, it is not impossible to use these pins, but it is advisable to read the verbal pin desciptions. They are carefully written and do not try to hide anything. If they do confuse you, I did something wrong, give me a holler, and I will fix it. I am the resident wordsmith :-) Peter Alfke, Xilinx ApplicationsArticle: 5746
As far as I am aware, XACT 6.0.1 doesn`t work in windows 95. eg Prom File Formatter allows you to go up directories but not back down etc. We have two "Lab PC`s" at work which are still Windows 3.11 in order to run XACT. I have heard that the Win95 Xilinx software is currently being beta tested - but our maintenance just expired. :-( Paul. Shantanu Tarafdar <shantanu@curie.ece.neu.edu> wrote in article <slrn5ibk05.lhv.shantanu@rosalind.ece.neu.edu>... > Hi, > > I was wondering if anyone has had this problem with XACT under > Windows 95. We get a system error and have to reboot the PC. > We are running on a Dell Pentium 133 system with 32MB of memory. > The version of XACT is v6.0.1. > > This happens when we try to "implement" from an XNF file. > The error message: > > Fatal Exception 0D occurred at 00a700000c9e > > And then the PC hangs. Has anyone seen this before or offer any > suggestions? > > Please reply to shantanu@ece.neu.edu. > > Thanks! > Shantanu... > > >Article: 5747
Steve Bird steveb@vizef.demon.co.uk wrote: > I guess you didn't like it... I haven't tried it. This was supposed to be humor. Here's the smiley :) For the humor impaired: Galileo and Leonardo are products from Exemplar logic Renoir is a is a product of Mentor Graphics This was not intended to cast aspersions on any these products. Here's some more smiley's :) :)Article: 5748
Todd A. Kline wrote: We are currently using ViewSynthesis and ViewPLD for FPGA and PLD/CPLD designs. We find ViewSynthesis optimizes the Xilinx FPGAs very poorly and ViewPLD is buggy, unstable, and poorly supported. I would be very grateful for any feedback on the following products: 1) Exemplar 2) Synario 3) Minc (PLD/CPLD) + Synplicity (FPGA). I have done some benchmarking on Synplicity and found that it optimized better then ViewSynthesis, but I'd prefer a unified VHDL/ABEL solution. I also must say that I have a GREAT prejudice against Synario. I have found DataIO support to be on a par with VIEWlogic, that is to say horrible. I also have doubts about DataIO's commitment to EDA products. Does any one remember FutureNet/Gates? For these reasons I find my self leaning to Exemplar but only because I know next to nothing about them. Ignorance is, after all, bliss. Your feedback is eagerly anticipated. Todd Todd, I have used all the synthesis tools you have described. I also sell the the Foundation tool set for XILINX. The tool kits are priced very reasonably and come with VHDL and SCHEMATIC and ABEL synthesis, and an ISA FPGA test board and VHDL and C code examples. see: http://www.erols.com/aaps We are advertising in the Marketplace of Personnal Engineering & Instrumentation with a list of current prices. Exemplar is a good VHDL tool. I have Galileo and use it for many of my non XILINX projects. The support people are very good. I have had less experience with Synplicity --but have used it-- they seemed very good too. Exemplar had some advantages in certain areas while Synplicity had advantages for others. They both were well supported. Please feel free to ask me specifics about any of the above products Richard Schwarz Pres. APSArticle: 5749
Samir Marc Falaki wrote: Hi, I need to make a decoder and demultiplexer with at least 64 outputs each + related logic. I have used Xilinx FPGAs with Mentor and Synopsys but would prefer a device that is more straightforward to program and with inexpensive tools (personal project). I have considered using CPLDs that would be one-time programmable and it seems to be a good idea. Does anyone have some suggestions. I don't have $millions so I would like something that is inexpensive to program, lot's of i/o, and tools that don't require patches and work-arounds. Thanks, Sam Falaki Sam, Check our XILINX tool sets at http://www.erols.com/aaps they are very low cost!! But if even they are too much, You could check out Cypress anf AMD 84 pin PLCC in circuit programmable parts. I have used the AMD and Cypress version of the MACH 230. The old PALASM compiler is free. Also Cypress sells a $99.00 VHDL compiler for its PLDs. I have it and it works fine. But they really don't match the flexibility and power of the XILINX stuff. Feel free to call and ask any questions on the above stuff. Richard Schwarz Pres. APS
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Compare FPGA features and resources
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