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Hello, Having bought XACT6 about a year ago, I have been asked something around $1000 for the annual maintenance. (This is in the UK). Without wishing to sound sarcastic, is there some special reason I should consider paying this? What worries me by far the most is this: if the dongle breaks, will Xilinx replace it if I am not under maintenance, or will I be stuck with a useless program? What exactly is Xilinx's policy on dongle replacement with out-of-maint customers? Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5601
But, they kept the feature where a schematic always comes up zoomed halfway out inside a small window within another small window. You still have to click in three different places to bring up your schematic to a reasonable view.Article: 5602
Kayvon Irani <kirani@cinenet.net> wrote in article <33081250.4CF6@cinenet.net>... > Hi every one: > > After Xilinx left the anti-fuse market a couple of months ago, Cypress > also decides to stop marketing its anti-fuse line of FPGAs referring > their anti-fuse customers to Quicklogic. It's hard to figure out the > main reason behind this decision by reading Quicklogic and Cypress' > press releases. Is anti-fuse running out of steam ? Does Cypress know > some thing we don't know? From what I have heard from Cypress's Manufacturers Rep, SRAM based FPGAs are where the money is and anti-fuse is a comparatively small market. Cypress has a great deal of SRAM experience which they feel they can better leverage in the SRAM FPGA market. It came as quite a shock to me as well - I had been investigating the very favorable timing characteristics of the anti-fuse products, particularly the new 38000 ultra-logic series. I beleive that Quicklogic will still sell these components.Article: 5603
Peter Alfke wrote: > Well, well. > This was an attack on the accuracy of my app note about driving 3.3 V > devices with our XC4000 outputs, see the Xilinx Data Book, page 6-3/4. > That app note was 100% my idea and my writing, so here I am: > > The explanation is ³long drawn-out² because the issue is complex. The word > ³nominally² was only used to demonstrate that it is important to use > worst-case rules. HUH? In the first paragraph that you mention worst case rules you clearly state that the "interface violates the conventional specification". That's where it should end. Period. If it violates the specification, it violates the specification. If Xilinx doesn't like it, tough. Design and market a part that does meet the specifications. Guarantee that Voh max does not exceed 3.6 volts over the specified operating conditions and dispense with the voodoo. > I invite everybody to read the analysis. Yes everybody, please do... > It assumes worst-case conditions. And several other things... > It talks about the possibility of 5 V and 3.3 V supplies "tracking > reasonably² , but then analyses the worst case where they do not. And it > says clearly that the nominally 5 V supply must not go to 5.5 V when the > nominally 3.3 V supply is simultaneously at 3.0 V. I leave it to the > designer to draw the proper conclusion. So spend a bunch of time and money building a power supply that will track on power-up and power down so that you won't latch up an I/O cell which is being asked to do something that it wasn't designed to do. BTW, that rules out using a switcher running off of the 5 volt supply to generate a local 3.3 volts. > > I stand behind this app note. It was meant to show that there is more to > an IC than the data sheet numbers. It looks to me like it was meant to sell more 4000E/EX parts. Besides, us ignorant designers out here only have the published data sheets to go by. If your part will do what you say it will do, then put the numbers in the data sheet. > Most manufacturers still claim that > input excursions in excess of 0.5 V beyond the supply are dangerous. Can you believe the nerve of some manufacturers specifying something like maximum input voltages for their own parts, on their own processes, using their own testing parameters, without clearing it with Xilinx applications!!! What is this world coming to?? > After careful investigation > and testing, we changed the Xilinx data sheet to allow up to 10 mA > forever, and 2 V for a typical reflection of max 20 ns. Yea, so? That is not the point or the stated intent of the app note. The app note is obviously written to convince the reader that a 4000E/EX device operating off a 5 volt supply can safely and reliably interface to ALL 3.3 volt logic, not that it will interface to a Xilinx part operating at 3.3 volts. How practical is all this anyway? Look at driving a 64 bit wide, 3.3 volt data bus from one of your parts. Even at the 6 mA per pin number in the app note, you need to source 384 mA of DC current when you drive the bus from low to high on top of the AC current needed to switch the load. The device at the other end is going really enjoy dissipating 1/4 W of power just in its protection diodes. Yea, this is worst case and "unrealistic", but everyone I know designs for worst case conditions, plus some margin. And the XC4028EX has 256 user I/O..... > My app note is carefully phrased and gives the potential user all the > information needed to use it, or reject it. This was not written by > Marketing. It is obviously not written by marketing. It is technical, well written, logically structured, eloquently stated, and, IMHO, fundamentally wrong. It is fudging the numbers to make a case for something that is not justified by the "conventional specifications", which are what engineers must rely on to design reliable systems. I find it hard to believe that something like this would be published if Xilinx had a legitimate 5 volt core/3.3 volt I/O offering in its FPGA line at the time. > > On a different note: My vicious attack at the Altera power specification > is based on their erroneous assumption that all internal power is > dissipated in logic, and is therefore proportional to the percentage of > logic toggling. In reality, the clock distribution dissipates a lot of > power, often exceeding the logic dissipation. And clock power does not > change with the percentage of logic toggling. The error in the Altera > calculation can easily exceed 50%. If that was your argument, why didn't you say so? That is some useful information that can really help someone understand the issue of power estimation in FPGAs. How does Xilinx handle the issue? What is a reasonable estimation algorithm from your perspective? What other things is the competition leaving out? The point of my response to your comment about "nonsense" is that all companies have their fair share of nonsense. Most of the time it comes from marketing who is trying to get a leg up on the competition. That's their job, and most experienced engineers understand that and 'consider the source' when listening to the hype. Maybe I'm naive, but somehow I expect more from an applications group. All the garbage about who has the biggest or fastest part is entertaining, but not very useful. The part is big enough and fast enough if it will, at a minimum, implement the function that you need, run at the speed that is required, meet the cost goals, and result in a fundamentally sound and reliable system. > An applications > engineer must be allowed to explain subtleties that go beyond the simple > data sheet numbers. That's fine, and applications groups are invaluable to the guys/gals in the trenches who are trying to meet their goals and maintain the reputation of their profession. That makes it even more important that an applications group is straight with their customers. If a part is not designed to do the job, just say so. The apps engineer is not the one whose rear is on the line when systems start failing in the field because of a kludge. > We can do that because we are close to the people who > designed and test the chips. If the chip is designed to do the job, and tested to ensure compliance with the published specifications, then put it in the data sheet. > Yes, I would fly in a plane that uses an XC4000 to drive a nominally 3.3 V > input. Why not ! TWA flight 800? Bill Harris Cisco Systems "My opinions are my own and do not necessarily reflect those of my employer."Article: 5604
Hi Every one:
I know that vital simualtion should not have any thing to do with a
wrapper file, but I have difficulty closing the post-layout simulation
loop when I use the wrapper, SDF and VHDL netlist generated by Galileo
to simulate on Model Tech. If I include the SDF file name when I
invoke VSIM, I get an error on every internal net on the design. Every thing
simulates OK if I don't include the SDF file name. I do have seperate
SYNTHESIS and DESIGN libraries; the netlist is compiled to SYNTHESIS lib,
the wrapper and RTL are compiled to the DESIGN lib. Any suggestions will be
appreciated.
Regards,
Kayvon Irani
Lear Astronics
Article: 5605
In article <3315ef70.258070686@news.alt.net>, z80@dserve.com says...
> Having bought XACT6 about a year ago, I have been asked something
> around $1000 for the annual maintenance. (This is in the UK).
> Without wishing to sound sarcastic, is there some special reason I
> should consider paying this?
maintenance support gives you access to the following:
1. the tech support hotline (this costs money, and this is
where you pay for it).
2. access to (and sometimes notification of) bug fixes
3. access to upgrades which support additional Xilinx
products/families
4. access to upgrades which add features to the existing
software (e.g. better routing, faster compiles, etc.)
For some, the maintenance agreement is well worth its cost.
For others, the expense is wasted money. For quite a few
people the value of the support isn't apparent until it is
needed, and then one can always "get back on the carriage"
(for a price).
As they say (on the net), your mileage *will* vary.
> What worries me by far the most is this: if the dongle breaks, will
> Xilinx replace it if I am not under maintenance, or will I be stuck
> with a useless program? What exactly is Xilinx's policy on dongle
> replacement with out-of-maint customers?
On this specific issue, you should get a commitment directly from
Xilinx, since they won't be held accountable for anyone's
assurances but their own. You might want to start with an
email message to hotline@xilinx.com.
> Peter.
****************************************************************
Bob Elkind mailto:eteam@aracnet.com
7118 SW Lee Road part-time fax number:503.357.9001
Gaston, OR 97119 cell:503.709.1985 home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5606On Tue, 25 Feb 1997 00:57:30 -0800, Ray Andraka <randraka@ids.net> wrote: >Some of the applications I've personally used FPGAs for include numerous >pipelined DSP systems for radar signal processing, imaging, and video. >Several of these are reconfigurable computing applications where parts >of the logic are changed according to the immediate need to reduce the >hardware requirement. Just a short question: What kind of device did you use for the reconfiguration thing and how did you implemented it? I can't imagine how this should work. Robert M. Muench SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany --> Answer to: r.m.muench+ieee.org <-- --> replace the + with @ <-- PGP-Fingerprint: 08 E9 EE 9F 33 ED 46 11 A5 CD BE FC 9D ED 75 14Article: 5607
TswvXyooj wrote: > > x-no-archive: yes > > I coded all my previous VHDL designs using Rising_Edge(clk) and > Falling_Edge(clk) function in lieu of (clk'event and clk = '1') > and (clk'event and clk = '0') respectively. Now, I'm using Synopsys' > synthesis tools and I can no longer use the > Rising_Edge/Falling_Edge functions. > > Has anyone run into this problem. Does anyone have a "set" > script (or something like that) that will allow me to > continue using Rising_Edge(clk) and Falling_Edge(clk) > functions with Synopsys' tools? Thank-you in advance. Well... Maybe you mean a 'sed' script ? Try this (type this on a single line) : sed -e "s/Rising_Edge(\([a-zA-Z_0-9]*\))/\1'event and \1 = '1'/g;s/Falling_Edge(\([a-zA-Z_0-9]*\))/\1'event and \1 = '0'/g" toto.vhd > newtoto.vhd BTW, grep your code first to check for lowercases/uppercases, because 'sed' is case sensitive ! Easy, isn't it ? -- Michel EFTIMAKIS.......................Internet : Michel.Eftimakis@vlsi.COM DECT Design Engineer...................Phone....: +33 (0) 4 92 96 11 19 VLSI TECHNOLOGY France.................Fax......: +33 (0) 4 92 96 11 01 505, Route des Lucioles................CellularP: Sophia Antipolis - 06560 Valbonne FRANCEArticle: 5608
(people have been discussing the various "features" of Viewdraw, especially the PC versions.) Robert H. Owen wrote: >force a full image but to automatically load the last used file. Before >we dropped the product, I was about to expand it to allow me to start it >up with any chosen sheet. We're still back with version 5.1, we "upgraded" a few seats to vsn 6.0, but everyone else begs not to upgrade their machine. It sounds like you've "dropped the product", what have you switched to? For that matter, what does anyone else reading this use? We are doing primarily XC4K designs, and are wondering if we should start worrying about whether Procapture 5.1 (or Viewdraw, or whatever the 'name de rev' is) will support moves to XC4kEX and other parts. What's the current evaluation of Orcad and Aldec/Foundation? Other options? thanks for any advice or comments- -- --al. Alan Sieving, ars@quickware.com or ars@world.std.com Quickware Engineering & Design, 225 Riverview Ave Waltham, MA, 02154-3874 W: 617-647-3800, FAX: 617-647-3311 800-237-1185 for fast PDP-11's.Article: 5609
Hello All, I have about 55 FLEX780's available that we won't be needing. If anyone would like to purchase email with an offer. GaryArticle: 5610
In article <01bc251e$207534d0$b3c32299@infinity>, "Henry Thomas" <henry@odo.com> wrote: > From what I have heard from Cypress's Manufacturers Rep, SRAM based FPGAs > are where the money is and anti-fuse is a comparatively small market. As you know, Xilinx put some time and effort into Antifuses, then terminated the project. The reasoning was similar: From a manufacturing point of view, antifuses are not the mainstream process. They are actually quite tricky to manufacture reliably, and it is difficult to upgrade the process as fast as SRAM processes improve these days ( much faster than a few years ago. We went from 0.6 to 0.5 to 0.35 micron in one year, and will be doing 0.25 and 0.18 micron within a year's time.) It does not seem possible to move the antifuse process that quickly. There is also the issue of gate oxide thickness and supply voltage that may make it difficult to migrate antifuses to the faster processes. From a user's perspective, the volatility of SRAM-based FPGAs has lost its negative connotation, has actually become an asset when it is used for reconfigurable logic and reconfigurable computing. On a more mundane level, users don't like the idea of having to program fine-lead-pitch packages in a programmer, thus having to handle the part twice. Even CPLDs are going In-System-Programmable. I wish Actel and Quicklogic all the success they can achieve. They offer the user another choice. The marketplace will decide whether it is a viable alternative. Peter Alfke, Xilinx Applications ( speaking for himself ).Article: 5611
In article <33166669.44FF@cisco.com>, Bill Harris <wmharris@cisco.com> wrote: a lot of stuff. I will not put any new fuel into this fire. All facts have been stated. Everybody can draw his or her own conclusions I would like to turn this flame off, it just wastes bandwidth. In a way, Bill Harris and I agree on far more things than we disagree on. Not surprising, since he used to be an applications engineer. For Altera. Peter Alfke, Xilinx ApplicationsArticle: 5612
I am in a group that is trying to program a XC4003 chip on a demo
board from Xilinx in serial slave mode, without the use of the Xchecker
cable. After looking at the data sheets and using a program that
outputs the data serially from an Intel Hex format in what is apparently
the correct data stream, the done signal still fails to assert. Output
data however, still seems to be in the correct format (preamble,
postamble etc.).
Our latest question is, can you download a bit file directly via the
serial port? (Does the file have to be created with Makebits with the
rawbits(-r) option enabled?)
Thanks in advance.
Henele
(hia@srv.ml.org)
http://srv.ml.org/xilinx
Article: 5613
In article <MPG.d7e9dc5f52665bd989681@news.xmission.com> hutch@convergent-design.com (Jeffrey L. Hutchings) writes:
>
>What I can't understand is why the BETA tester's input
>was ignored. I know for a fact the everyone was screaming
>for them to keep the command line and the other features
>but they chose not to. Only Viewlogic knows why.
>
Depends on whether View's current mgmt. considers their beta
program to be part of the SQA process or merely a sales too.
_______________________________________________________________________________
|
AXENHAMMER SYSTEMS | Arthur R. Marriott
--Applied Technology-- | artm@eskimo.com
|
_______________________________________|_______________________________________
If we're not supposed to see boobs exposed on television,
I guess they're going to have to pull the plug on C-SPAN...
_______________________________________________________________________________
Article: 5614The latest Computer Design had a short story indicating that Quicklogic will start using TSMC as a foundry with a 0.5u, 3 metal process. This should result in even faster parts. Henry Thomas wrote: > > Kayvon Irani <kirani@cinenet.net> wrote in article > <33081250.4CF6@cinenet.net>... > > Hi every one: > > > > After Xilinx left the anti-fuse market a couple of months ago, Cypress > > also decides to stop marketing its anti-fuse line of FPGAs referring > > their anti-fuse customers to Quicklogic. It's hard to figure out the > > main reason behind this decision by reading Quicklogic and Cypress' > > press releases. Is anti-fuse running out of steam ? Does Cypress know > > some thing we don't know? > > From what I have heard from Cypress's Manufacturers Rep, SRAM based FPGAs > are where the money is and anti-fuse is a comparatively small market. > Cypress has a great deal of SRAM experience which they feel they can better > leverage in the SRAM FPGA market. It came as quite a shock to me as well - > I had been investigating the very favorable timing characteristics of the > anti-fuse products, particularly the new 38000 ultra-logic series. I > beleive that Quicklogic will still sell these components. -- Ed Beers email: sreeb@doctord.com Doctor Design, Inc. switchboard: (619) 457-4545 10505 Sorrento Valley Rd, #1 direct line: (619) 824-3031 San Diego, CA 92121-1608 fax: (619) 824-3131Article: 5615
Bill Harris wrote: > So spend a bunch of time and money building a power supply that will track on power-up and power down so that you won't > latch up an I/O cell which is being asked to do something that it wasn't designed to do. BTW, that rules out using a > switcher running off of the 5 volt supply to generate a local 3.3 volts. Folks don't configure their Xilinx parts until power is stable, so there is no need to worry about powerup tracking. Asserting *prog at powerdown tri-states all outputs, eliminating any concern about powerdown. So a 3.3V switcher running from 5V is just plain easy. And making the 3.3V rail track the 5V rail when running is also trivial. Such a small amount of power supply design effort seems worth it. Xilinx will have true 3.3V I/O shortly. Until then their app note shows an easy way to bridge the gap. Regards, ScottArticle: 5616
Anybody had any experience with the ACTEL RAM BASED FPGAs? Are they out yet? What packages will they offer? I think this is a smart move on their part but haven't heard much about them. Richard SchwarzArticle: 5617
TswvXyooj wrote:
> Has anyone run into this problem. Does anyone have a "set"
> script (or something like that) that will allow me to
> continue using Rising_Edge(clk) and Falling_Edge(clk)
> functions with Synopsys' tools? Thank-you in advance.
Although I'm not very familiar with Synopsys, you could use a function
like this (off the cuff, after a few glasses of wine at home, so expect
some error messages):
FUNCTION Falling_edge(signal clock : std_ulogic) : BOOLENA
BEGIN
IF (Clock'EVENT and Clock = '0') then
return TRUE
ELSE
return FALSE
END IF;
END;
Rising_edge should be trivial. If you define these in a package which
you include you should be fine.
Regards,
Ben Twijnstra
Article: 5618
(DEADLINE for early registration is MARCH 14)
Advance Program
1997 International Symposium on Physical Design
Embassy Suites at Napa Valley, Napa, California
April 14--16, 1997
http://www.cs.virginia.edu/~ispd97/
The International Symposium on Physical Design provides a new and high-quality
forum for the exchange of ideas and results in critical areas related to the
physical design of VLSI systems. The Symposium is an outgrowth of the
ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope
includes all aspects of physical design, from interactions with behavior-
and logic-level synthesis, to back-end performance analysis and verification.
This year's inaugural Symposium focuses on the challenges of high-performance
deep-submicron design, as well as the necessary interactions between physical
design and higher-level synthesis tasks. An outstanding slate of technical
papers has been selected for oral and poster presentation. These developments
are complemented by invited presentations that set forth the contexts and
visions for key areas -- process technology, system architecture, circuit
design and design methodology -- with an emphasis on their implications for
relevant R&D in physical design. The Symposium concludes with a panel of
leading experts who each present their unique perspectives as to the critical
R&D needs of the field.
%%==========================================================================%%
%% Monday, April 14 %%
%%==========================================================================%%
0830-0840 Chairs' Welcome
A. B. Kahng and M. Sarrafzadeh
0840-1010 Keynote Address
* Physical Design: Past and Future, T. C. Hu (UCSD), E. S. Kuh (UCB)
1010-1030 Break
1030-1230 Session 1: Placement and Partitioning
Chairs: D. Hill (Synopsys)
J. Frankle (Aristo Technology)
* Faster Minimization of Linear Wirelength for Top-Down Placement,
C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet,
K. Yan (UCLA, Cadence and IBM)
* Network Flow Based Multi-Way Partitioning with Area and Pin Constraints,
H. Liu, D. F. Wong (UT-Austin)
* Partitioning-Based Standard-Cell Global Placement with An Exact Objective,
D. J. Huang, A. B. Kahng (UCLA and Cadence)
* VLSI/PCB Placement with Obstacles Based on Sequence Pair,
H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.)
1230--1430 Lunch (Speaker)
* The Quarter Micron Challenge: Integrating Physical and Logic Design
R. Camposano (Synopsys)
1430--1600 Session 2: Synthesis and Layout
Chairs: R. Camposano (Synopsys)
C. Sechen (Washington)
* Timing Driven Placement in Interaction with Netlist Transformations,
G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich)
* Regular Layout Generation of Logically Optimized Datapaths,
R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven)
* Minimizing Interconnect Energy Through Integrated Low-Power Placement
and Combinational Logic Synthesis,
G. Holt, A. Tyagi (Iowa State)
1600--1630 Break
1630--1830 Session 3: Contexts (Invited)
* Design Technology Trends Based on NTRS Evolution,
P. Verhofstadt, C. D'Angelo (SRC)
* Microprocessor Architecture, Circuit, and Physical Design Trends,
A. Charnas (Sun)
1900--2100 Dinner (Speaker)
* Lithography and Dimensional Trends for Future Processes -- Implications
for Physical Design
P. K. Vasudev (Sematech)
%%==========================================================================%%
%% Tuesday, April 15 %%
%%==========================================================================%%
0830--1000 Session 4: Routing
Chairs: C. L. Liu (Illinois)
D. F. Wong (UT-Austin)
* On Two-Step Routing for FPGAs,
G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto)
* A Simple and Effective Greedy Multilayer Router for MCMs,
Y.-J. Cha (Electronic & Telecomm Research Institute),
C. S. Rim (Sogang U.), K. Nakajima (Maryland)
* Performance Driven Global Routing for Standard Cells,
J. Cong and P. Madden (UCLA)
1000--1030 Break
1030--1200 Session 5: Steiner Tree Constructions
Chairs: M. Marek-Sadowska (UCSB)
N. Sherwani (Intel)
* Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving
Tree Construction,
J. D. Cho (SungKyunKwan U.)
* Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence
Problem with Applications to VLSI Physical Design,
J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence)
* Provably Good Routing Tree Construction with Multi-Port Terminals,
C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia)
1200--1330 Lunch
1330--1500 Session 6: Back-End Design Methodology
Chairs: E. Yoffa (IBM)
M. Weisel (Intel)
* A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems,
L. Scheffer (Cadence)
* C5M - A Control Logic Layout Synthesis System for High-performance
Microprocessors,
J. Burns, J. Feldman (IBM)
* A VLSI Artwork Legalization Technique Based on a New Criterion of
Minimum Layout Perturbation,
F.-L. Heng, Z. Chen, G. E. Tellez (IBM)
1500--1545 Session 7: Poster Presentations
Chairs: G. Robins (Virginia)
J. D. Cho (SungKyunKwan U.)
* A Pseudo-Hierarchical Methodology for High Performance
Microprocessor Design,
A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo,
S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM);
T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott,
R. Weiss (Cadence)
* Concurrent Transistor Sizing and Buffer Insertion by Considering
Cost-Delay Tradeoffs,
J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State)
* Towards a New Benchmarking Paradigm in EDA,
N. Kapur, D. Ghosh, F. Brglez (NCSU)
* How Good are Slicing Floorplans?,
F. Y. Young, D. F. Wong (UT-Austin)
* Slicibility of Rectangular Graphs and Floorplan Optimization,
P. DasGupta, S. Sur-kolay (Indian Institute of Management)
* Power Optimization for FPGA Look-Up Tables,
M. J. Alexander (Washington State)
* A Matrix Synthesis Approach to Thermal Placement,
C. Chu, D. F. Wong (UT-Austin)
1545--1715 Session 8: Poster Session
Authors display and discuss one-on-one the posters presented in Poster
Presentation session.
1900--2200 Banquet
%%==========================================================================%%
%% Wednesday, April 16 %%
%%==========================================================================%%
0830--1000 Session 9: Performance Optimization
Chairs: W.-M. Dai (UCSC)
L. Jones (Motorola)
* EWA: Exact Wire Sizing Algorithm,
R. Kay, G. Bucheuv, L. Pileggi (CMU)
* Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers,
D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte)
* Closed Form Solution to Simultaneous Buffer Insertion/Sizing and
Wire Sizing,
C. C. N. Chu, D. F. Wong (UT-Austin)
1000--1030 Break
1030--1230 Session 10: Design Methodology Futures (Invited)
* CHDS: A Foundation for Timing-Driven Physical Design into the 21st Century,
D. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel)
* Physical Design 2010: Back to the Future?
A. R. Newton (UCB)
1230--1430 Lunch (Speaker)
* Physical Design Realities for Digital's StrongARM and Alpha Microprocessors
W. J. Grundmann (DEC)
1430--1700 Session 11: Core Directions (or, Do The Right Thing) (Invited)
* Physical Design Challenges of Performance
D. P. LaPotin (IBM Austin Research Lab)
* Panel: Physical Design R&D: What's Missing?
Moderator: G. Smith (Dataquest)
E. Hsieh (Avant!)
M. Hunt (Cadence)
S.-M. Kang (Illinois)
K. Keutzer (Synopsys)
D. P. LaPotin (IBM Austin Research Lab)
N. Sherwani (Intel Hillsboro)
1700 Symposium Closes
%%==========================================================================%%
%% Symposium Organization %%
%%==========================================================================%%
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee:
J. P. Cohoon (Virginia),
S. DasGupta (IBM),
S.-M. Kang (Illinois),
B. Preas (Xerox PARC)
Technical Program Chair: M. Sarrafzadeh (Northwestern)
Technical Program Committee:
C.-K. Cheng (UCSD),
W.-M. Dai (UCSC),
J. Frankle (Aristo Technology),
D. D. Hill (Synopsys),
J. A. G. Jess (Eindhoven),
L. Jones (Motorola),
Y.-L. Lin (Tsing Hua),
C. L. Liu (Illinois),
M. Marek-Sadowska (UCSB),
C. Sechen (Washington),
K. Takamizawa (NEC),
M. Wiesel (Intel),
D. F. Wong (UT-Austin),
E. Yoffa (IBM)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UCB)
Treasurer: S. B. Souvannavong
Sponsors:
ACM Special Interest Group on Design Automation, in cooperation with
IEEE Circuits and Systems Society
Additional Support From:
Avant! Corporation,
Cadence Design Systems, Inc.,
Intel Corporation,
Synopsys Inc., and the
U. S. National Science Foundation.
%%==========================================================================%%
%% Hotel Accommodations and Travel %%
%%==========================================================================%%
ISPD-97 is being held at the Embassy Suites at Napa Valley (formerly the
Inn at Napa Valley) in Napa, California. The hotel is located 55 miles north
of San Francisco, CA in the beautiful Napa Valley. Evans Airport Service
provides daily service between Embassy Suites at Napa Valley and San Francisco
International Airport (SFO) approximately every two hours. On Saturdays and
Sundays, the first departure from SFO is at 8:15am. A one-way fare is $18.00,
and advance reservations are required. Phone 1-707-255-1559 or
FAX 1-707-255-0753. The Embassy Suites at Napa Valley is located at:
1075 California Boulevard
Napa, CA 94559
Phone: 1-707-253-9540
Fax: 1-707-253-9292
Hotel Reservations: 1-800-362-2779
(Central Embassy Suites reservation service.)
A block of rooms is being held for the nights of Sunday through Wednesday
(April 13 through April 16). Room rates are $105 per night for single or
double occupancy. Any individual cancellations within 48 hours from the
date of arrival will be billed for (1) night's stay, plus tax.
+---------------------------------------------------------+
| Please make room reservations directly with the hotel |
| at 1-800-362-2779, mentioning ``GROUP CODE ACM''. |
+---------------------------------------------------------+
The number of rooms available at this rate is limited, and are only being
held through March 14. Early room reservation is highly recommended.
For attendees wishing to stay over Friday and Saturday night, a special rate
of $129 per night, subject to room availablity, has been arranged for
April 11--12 and April 17--19.
%%==========================================================================%%
%% ISPD-97 Advance Registration Form %%
%%==========================================================================%%
Name: _______________________________________________________
Company/University: _________________________________________
Responsibility/Title: _______________________________________
Address: ____________________________________________________
City: _______________________________ State: ________________
Country: ______________________ Postal Code: ________________
Phone: ________________________ Fax: ________________________
Email: ______________________________________________________
Food Choices:
[ ] Vegetarian meals only
[ ] Swordfish or [ ] Filet Mignon (Monday dinner)
Advance Late
(Through March 14) (After March 14)
ACM/IEEE Members [ ] $350 [ ] $425
Non-Members [ ] $425 [ ] $500
Full-Time Students [ ] $175 [ ] $225
Student ID is required if registering as a student.
ACM or IEEE Member No. _____________________________
Registration fee includes meals and Banquet. A limited number of
additional Banquet tickets are available.
_______ Extra Banquet tickets at $50/each.
Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/1997 International Symposium on
Physical Design''. Payment may also be made with credit card (circle):
Mastercard Visa American Express
Credit Card # _______________________________________________
Expiration Date: ______________ Total Payment: ______________
Name as it appears on credit card: __________________________
Signature: ___________________________ Date: ________________
Please mail or FAX (credit card only) your completed registration form to:
ISPD-97 Symposium Registration
Sally Souvannavong, Treasurer
P.O. Box 395
Pullman, WA 99163-0395
FAX: 1-509-335-3818
Email registration will not be accepted. Cancellations must be in writing
and must be received by March 31, 1997. Questions concerning symposium
registration should be directed to Sally Souvannavong at 1-509-334-3162,
Email: ispd97@eecs.wsu.edu.
%%==========================================================================%%
%% Additional Information %%
%%==========================================================================%%
Check in at Your Convenience:
The symposium registration desk will be open from 4pm to 6pm on Sunday,
April 13th. On Monday, the registration desk will open at 7:30am and
will remain open until 5:00pm.
Experience Springtime in Napa Valley:
Napa Valley weather is very pleasant in April, with an average high temperature
of 78 degrees F and low of 64 degrees F. Attractions include world-famous
wineries offering daily tours, golf and outdoor-recreation facilities, and
easy access to Marine World--Africa USA. Contact the Napa Valley Tourist
Bureau (1-800-523-4353) or Visitors Bureau (1-707-226-7459), or visit the
following websites for additional information:
ISPD-97 Website -- http://www.cs.virginia.edu/~ispd97/
Napa Valley Virtual Visit -- http://www.napavalley.com/cgi-bin/home.o
Conference and Visitors Bureau -- http://www.napavalley.com/nvcvb.html
Driving Directions from East Bay:
Take Hwy 80 to Hwy 37 west, 2 miles to Hwy 29 north, 12 miles to 1st Street
exit to California Boulevard (first left turn off freeway).
Driving Directions from San Francisco:
Take Hwy 101 to Hwy 37 east, 7 miles to Hwy 121 north, then east 15 miles
to Hwy 29 north, 2 miles to 1st Street exit to California Boulevard
(first left turn off freeway).
Article: 5619
(DEADLINE for early registration is MARCH 14)
Advance Program
1997 International Symposium on Physical Design
Embassy Suites at Napa Valley, Napa, California
April 14--16, 1997
http://www.cs.virginia.edu/~ispd97/
The International Symposium on Physical Design provides a new and high-quality
forum for the exchange of ideas and results in critical areas related to the
physical design of VLSI systems. The Symposium is an outgrowth of the
ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope
includes all aspects of physical design, from interactions with behavior-
and logic-level synthesis, to back-end performance analysis and verification.
This year's inaugural Symposium focuses on the challenges of high-performance
deep-submicron design, as well as the necessary interactions between physical
design and higher-level synthesis tasks. An outstanding slate of technical
papers has been selected for oral and poster presentation. These developments
are complemented by invited presentations that set forth the contexts and
visions for key areas -- process technology, system architecture, circuit
design and design methodology -- with an emphasis on their implications for
relevant R&D in physical design. The Symposium concludes with a panel of
leading experts who each present their unique perspectives as to the critical
R&D needs of the field.
%%==========================================================================%%
%% Monday, April 14 %%
%%==========================================================================%%
0830-0840 Chairs' Welcome
A. B. Kahng and M. Sarrafzadeh
0840-1010 Keynote Address
* Physical Design: Past and Future, T. C. Hu (UCSD), E. S. Kuh (UCB)
1010-1030 Break
1030-1230 Session 1: Placement and Partitioning
Chairs: D. Hill (Synopsys)
J. Frankle (Aristo Technology)
* Faster Minimization of Linear Wirelength for Top-Down Placement,
C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet,
K. Yan (UCLA, Cadence and IBM)
* Network Flow Based Multi-Way Partitioning with Area and Pin Constraints,
H. Liu, D. F. Wong (UT-Austin)
* Partitioning-Based Standard-Cell Global Placement with An Exact Objective,
D. J. Huang, A. B. Kahng (UCLA and Cadence)
* VLSI/PCB Placement with Obstacles Based on Sequence Pair,
H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.)
1230--1430 Lunch (Speaker)
* The Quarter Micron Challenge: Integrating Physical and Logic Design
R. Camposano (Synopsys)
1430--1600 Session 2: Synthesis and Layout
Chairs: R. Camposano (Synopsys)
C. Sechen (Washington)
* Timing Driven Placement in Interaction with Netlist Transformations,
G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich)
* Regular Layout Generation of Logically Optimized Datapaths,
R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven)
* Minimizing Interconnect Energy Through Integrated Low-Power Placement
and Combinational Logic Synthesis,
G. Holt, A. Tyagi (Iowa State)
1600--1630 Break
1630--1830 Session 3: Contexts (Invited)
* Design Technology Trends Based on NTRS Evolution,
P. Verhofstadt, C. D'Angelo (SRC)
* Microprocessor Architecture, Circuit, and Physical Design Trends,
A. Charnas (Sun)
1900--2100 Dinner (Speaker)
* Lithography and Dimensional Trends for Future Processes -- Implications
for Physical Design
P. K. Vasudev (Sematech)
%%==========================================================================%%
%% Tuesday, April 15 %%
%%==========================================================================%%
0830--1000 Session 4: Routing
Chairs: C. L. Liu (Illinois)
D. F. Wong (UT-Austin)
* On Two-Step Routing for FPGAs,
G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto)
* A Simple and Effective Greedy Multilayer Router for MCMs,
Y.-J. Cha (Electronic & Telecomm Research Institute),
C. S. Rim (Sogang U.), K. Nakajima (Maryland)
* Performance Driven Global Routing for Standard Cells,
J. Cong and P. Madden (UCLA)
1000--1030 Break
1030--1200 Session 5: Steiner Tree Constructions
Chairs: M. Marek-Sadowska (UCSB)
N. Sherwani (Intel)
* Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving
Tree Construction,
J. D. Cho (SungKyunKwan U.)
* Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence
Problem with Applications to VLSI Physical Design,
J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence)
* Provably Good Routing Tree Construction with Multi-Port Terminals,
C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia)
1200--1330 Lunch
1330--1500 Session 6: Back-End Design Methodology
Chairs: E. Yoffa (IBM)
M. Weisel (Intel)
* A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems,
L. Scheffer (Cadence)
* C5M - A Control Logic Layout Synthesis System for High-performance
Microprocessors,
J. Burns, J. Feldman (IBM)
* A VLSI Artwork Legalization Technique Based on a New Criterion of
Minimum Layout Perturbation,
F.-L. Heng, Z. Chen, G. E. Tellez (IBM)
1500--1545 Session 7: Poster Presentations
Chairs: G. Robins (Virginia)
J. D. Cho (SungKyunKwan U.)
* A Pseudo-Hierarchical Methodology for High Performance
Microprocessor Design,
A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo,
S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM);
T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott,
R. Weiss (Cadence)
* Concurrent Transistor Sizing and Buffer Insertion by Considering
Cost-Delay Tradeoffs,
J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State)
* Towards a New Benchmarking Paradigm in EDA,
N. Kapur, D. Ghosh, F. Brglez (NCSU)
* How Good are Slicing Floorplans?,
F. Y. Young, D. F. Wong (UT-Austin)
* Slicibility of Rectangular Graphs and Floorplan Optimization,
P. DasGupta, S. Sur-kolay (Indian Institute of Management)
* Power Optimization for FPGA Look-Up Tables,
M. J. Alexander (Washington State)
* A Matrix Synthesis Approach to Thermal Placement,
C. Chu, D. F. Wong (UT-Austin)
1545--1715 Session 8: Poster Session
Authors display and discuss one-on-one the posters presented in Poster
Presentation session.
1900--2200 Banquet
%%==========================================================================%%
%% Wednesday, April 16 %%
%%==========================================================================%%
0830--1000 Session 9: Performance Optimization
Chairs: W.-M. Dai (UCSC)
L. Jones (Motorola)
* EWA: Exact Wire Sizing Algorithm,
R. Kay, G. Bucheuv, L. Pileggi (CMU)
* Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers,
D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte)
* Closed Form Solution to Simultaneous Buffer Insertion/Sizing and
Wire Sizing,
C. C. N. Chu, D. F. Wong (UT-Austin)
1000--1030 Break
1030--1230 Session 10: Design Methodology Futures (Invited)
* CHDS: A Foundation for Timing-Driven Physical Design into the 21st Century,
D. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel)
* Physical Design 2010: Back to the Future?
A. R. Newton (UCB)
1230--1430 Lunch (Speaker)
* Physical Design Realities for Digital's StrongARM and Alpha Microprocessors
W. J. Grundmann (DEC)
1430--1700 Session 11: Core Directions (or, Do The Right Thing) (Invited)
* Physical Design Challenges of Performance
D. P. LaPotin (IBM Austin Research Lab)
* Panel: Physical Design R&D: What's Missing?
Moderator: G. Smith (Dataquest)
E. Hsieh (Avant!)
M. Hunt (Cadence)
S.-M. Kang (Illinois)
K. Keutzer (Synopsys)
D. P. LaPotin (IBM Austin Research Lab)
N. Sherwani (Intel Hillsboro)
1700 Symposium Closes
%%==========================================================================%%
%% Symposium Organization %%
%%==========================================================================%%
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee:
J. P. Cohoon (Virginia),
S. DasGupta (IBM),
S.-M. Kang (Illinois),
B. Preas (Xerox PARC)
Technical Program Chair: M. Sarrafzadeh (Northwestern)
Technical Program Committee:
C.-K. Cheng (UCSD),
W.-M. Dai (UCSC),
J. Frankle (Aristo Technology),
D. D. Hill (Synopsys),
J. A. G. Jess (Eindhoven),
L. Jones (Motorola),
Y.-L. Lin (Tsing Hua),
C. L. Liu (Illinois),
M. Marek-Sadowska (UCSB),
C. Sechen (Washington),
K. Takamizawa (NEC),
M. Wiesel (Intel),
D. F. Wong (UT-Austin),
E. Yoffa (IBM)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UCB)
Treasurer: S. B. Souvannavong
Sponsors:
ACM Special Interest Group on Design Automation, in cooperation with
IEEE Circuits and Systems Society
Additional Support From:
Avant! Corporation,
Cadence Design Systems, Inc.,
Intel Corporation,
Synopsys Inc., and the
U. S. National Science Foundation.
%%==========================================================================%%
%% Hotel Accommodations and Travel %%
%%==========================================================================%%
ISPD-97 is being held at the Embassy Suites at Napa Valley (formerly the
Inn at Napa Valley) in Napa, California. The hotel is located 55 miles north
of San Francisco, CA in the beautiful Napa Valley. Evans Airport Service
provides daily service between Embassy Suites at Napa Valley and San Francisco
International Airport (SFO) approximately every two hours. On Saturdays and
Sundays, the first departure from SFO is at 8:15am. A one-way fare is $18.00,
and advance reservations are required. Phone 1-707-255-1559 or
FAX 1-707-255-0753. The Embassy Suites at Napa Valley is located at:
1075 California Boulevard
Napa, CA 94559
Phone: 1-707-253-9540
Fax: 1-707-253-9292
Hotel Reservations: 1-800-362-2779
(Central Embassy Suites reservation service.)
A block of rooms is being held for the nights of Sunday through Wednesday
(April 13 through April 16). Room rates are $105 per night for single or
double occupancy. Any individual cancellations within 48 hours from the
date of arrival will be billed for (1) night's stay, plus tax.
+---------------------------------------------------------+
| Please make room reservations directly with the hotel |
| at 1-800-362-2779, mentioning ``GROUP CODE ACM''. |
+---------------------------------------------------------+
The number of rooms available at this rate is limited, and are only being
held through March 14. Early room reservation is highly recommended.
For attendees wishing to stay over Friday and Saturday night, a special rate
of $129 per night, subject to room availablity, has been arranged for
April 11--12 and April 17--19.
%%==========================================================================%%
%% ISPD-97 Advance Registration Form %%
%%==========================================================================%%
Name: _______________________________________________________
Company/University: _________________________________________
Responsibility/Title: _______________________________________
Address: ____________________________________________________
City: _______________________________ State: ________________
Country: ______________________ Postal Code: ________________
Phone: ________________________ Fax: ________________________
Email: ______________________________________________________
Food Choices:
[ ] Vegetarian meals only
[ ] Swordfish or [ ] Filet Mignon (Monday dinner)
Advance Late
(Through March 14) (After March 14)
ACM/IEEE Members [ ] $350 [ ] $425
Non-Members [ ] $425 [ ] $500
Full-Time Students [ ] $175 [ ] $225
Student ID is required if registering as a student.
ACM or IEEE Member No. _____________________________
Registration fee includes meals and Banquet. A limited number of
additional Banquet tickets are available.
_______ Extra Banquet tickets at $50/each.
Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/1997 International Symposium on
Physical Design''. Payment may also be made with credit card (circle):
Mastercard Visa American Express
Credit Card # _______________________________________________
Expiration Date: ______________ Total Payment: ______________
Name as it appears on credit card: __________________________
Signature: ___________________________ Date: ________________
Please mail or FAX (credit card only) your completed registration form to:
ISPD-97 Symposium Registration
Sally Souvannavong, Treasurer
P.O. Box 395
Pullman, WA 99163-0395
FAX: 1-509-335-3818
Email registration will not be accepted. Cancellations must be in writing
and must be received by March 31, 1997. Questions concerning symposium
registration should be directed to Sally Souvannavong at 1-509-334-3162,
Email: ispd97@eecs.wsu.edu.
%%==========================================================================%%
%% Additional Information %%
%%==========================================================================%%
Check in at Your Convenience:
The symposium registration desk will be open from 4pm to 6pm on Sunday,
April 13th. On Monday, the registration desk will open at 7:30am and
will remain open until 5:00pm.
Experience Springtime in Napa Valley:
Napa Valley weather is very pleasant in April, with an average high temperature
of 78 degrees F and low of 64 degrees F. Attractions include world-famous
wineries offering daily tours, golf and outdoor-recreation facilities, and
easy access to Marine World--Africa USA. Contact the Napa Valley Tourist
Bureau (1-800-523-4353) or Visitors Bureau (1-707-226-7459), or visit the
following websites for additional information:
ISPD-97 Website -- http://www.cs.virginia.edu/~ispd97/
Napa Valley Virtual Visit -- http://www.napavalley.com/cgi-bin/home.o
Conference and Visitors Bureau -- http://www.napavalley.com/nvcvb.html
Driving Directions from East Bay:
Take Hwy 80 to Hwy 37 west, 2 miles to Hwy 29 north, 12 miles to 1st Street
exit to California Boulevard (first left turn off freeway).
Driving Directions from San Francisco:
Take Hwy 101 to Hwy 37 east, 7 miles to Hwy 121 north, then east 15 miles
to Hwy 29 north, 2 miles to 1st Street exit to California Boulevard
(first left turn off freeway).
Article: 5620Any tips for a good Printout formatting tool ? (Bold, Italics, Font changes..) ie. Syntax highlighting / "-fonting" suitable for HP Laserjet (-3/4/5) output. Preferably usable under Windows 95. Thanks- -- ------------------------------------------------------------------------- Peter Fenn Email: PeterF@aztec.co.za 11 Ludwig Muhl Street Phone: (+27 21) 855-1354 Somerset West, 7130, South Africa Fax: (+27 21) 855-2807 -------------------------------------------------------------------------Article: 5621
Austin Cassidy (oz@vsprsun_18) wrote: : Hi, : I am a user of Synopsys and Mentor Graphics Autologic. I am currently developingsome teaching/labarotory materiel for MSc level work. Does anyone out there : know how to instantiate Xilinx elemnts directly into the VHDL code to add : elements like the osc4 (XC4000) library. The intention is then to run through : Mentor Autologic to synthesize the design.If anyone has an example of how to do this it would be great... It is easy in Synopsys.... http://erebor.cudenver.edu/local/ee5521/dcfpga/index.html for a complete design. The purisc.vhd files shows how to instantiate the osc, startup, ram and rom primitives. -Rich Auletta PS Easy once you know how :)Article: 5622
Henry Thomas (henry@odo.com) wrote: : From what I have heard from Cypress's Manufacturers Rep, SRAM based FPGAs : are where the money is and anti-fuse is a comparatively small market. : Cypress has a great deal of SRAM experience which they feel they can better : leverage in the SRAM FPGA market. It came as quite a shock to me as well - WOW! That would be great! Warp2 when combined with SRAM FPGAs would be fantastic for Universities! (For PLDs and CPLDs it is great, but one time programmable parts are "problematical" for universities.) They are the only tools I know of that work the way one expects VHDL synthesis tools to work. By that I mean VHDL in for simulation and synthesis, and VHDL (VITAL) out for post-synthesis simulation. No fuss, no muss every thing is there. Just add your favorite VHDL simulator (like Model Tech V-System). -Rich AulettaArticle: 5623
Apology I did not respond to this query at first, because I thought some expert would respond with a compendium of applications from some survey. Since there has been little response, I now believe this is the survey. The following is simply my experience at one company over the past 6 years. Past use = Small and Low Power At Diablo Research, we have been using FPGAs in combination with small microcontrollers for years to realize small battery operated digital radios. The FPGAs are used to do things that are too fast for the micro, such as bitsync, framesyncs, box car filters, and synthesizer lock signal processors. FPGAs also serve as port expanders for the small micros, and when 8051 type muxed adr/data buses are used, the FPGA provides the adr latch. Some times the FPGA even provide a frequency mixing function. If you put one freq on the 'D' of a flop and the other on the 'Clk,' the difference will be available at the Q. If the signals are noisy, (jittery) you may have to reclock the 'Q' with a divided down version of one of the input freqs to get rid of multiple output transitions. For years our main concerns, at Diablo have been small packages and low power. Every time we reevaluate the market Xilinx seemed to provide the best solution to meet these requirements. We currently use a XC3030LVQ64 in a gas meter radio that has to run on a Lithium battery for 10 years, while transmitting every 5 minutes. We also use a 3064ATQ144 for the other side of this link where power is not as limited. Currently we need FAST and BIG Recently, we've been doing a big, two way, VSAT system, and have been interested in exactly the opposite FPGA requirements, Large, and fast, with reasonable cost. Again, after evaluating the market, we settled on Xilinx XC4025E as the lowest cost per function we could find. All together we are designing three boards with a total of 16 of these chips. 13 different designs. We could have used chips that were 5 times the size! (We plan to eventually do some consolidation into ASICs, for the high volume boards.) The functions in this project are all DSP. FIR filter, Resampler, Decimator, Interpolator, BitSync, Scrambler, Convolutional Encoder, interleaver, Reed-Solomon encoder, and many more all running at 25MHz. and higher clock rates. When we started, there was a lack of existing libraries for efficient implementation of even basic functions like constant multipliers for FIRs and adders with outputs that grow by a bit and with optional clock enabled registered output, so all this had to be developed. We eventually gravitated toward doing floor planing of the data path (which is most everything) using RLOCs (relative location attributes) on the schematic. This allows building up a set of reusable blocks, with consistent timing, which can be combined with similar blocks from other engineers, into a single chip, or repartitioned to the next chip, if necessary, to save space. This works OK, but the engineers must agree up front on the shape of their tiles, so that the tiles will not overlap in the target chip. We're using ViewLogic schematic capture. The VHDL etc. tests we did at the beginning, just did not seem to generate efficient DSP blocks, such as high speed constant multipliers. We really don't have room for say, twice as many Xilinx chips on these boards. We unfortunately gave XBLOX a try, but abandoned it because the schedule called for completion in less than one live time, and XSimMake was incompatible, Wish 1 My first wish for my next DSP project would be to have a library of DSP parts all RLOCed and documented for function, CLB usage, and speed. I would hope for efficient adders, counters, accumulators, muxes, constant multipliers, complimenters etc. By efficient, I mean, for instance, a constant multiply of a 10bit 2's compliment variable by a constant +9 would require a single 11 bit adder, not a full multiplier, to produce the 14 bit product. I don't think I want paramitized XBLOX type parts, because, that requires some sort of compilation of the whole ckt, before functional simulation, and that takes a lot of time. Paramitized parts also permits less control of placement on the chip so would probably not result in a high percentage of chip utilization. Perhaps, if the parameterized part could be compiled once, then RLOCed and used as a macro, it would be nice. I just don't want to have to run something like XsimMake on the whole design, every time I change the schematic and need to simulate. This scheme might permit larger library parts, too. Whole parameterized FIR filters for instance, with parameters for speed, data path width, decimation ratio, coefficient values and precision, and perhaps even, rounding or truncation controls, both after the multipliers, and at the output. Distributed arithmetic architectures could even be substituted where lower speeds are acceptable. Compile once, to a macro, then instantiate at will, with separate RLOC_ORIGINs Wish 2 My next wish would be for ViewLogic's ViewTrace, digital simulator waveform viewer, to be able to display DSP signals as graphical wave forms. A 10bit 2's compliment sine wave is much friendlier when represented graphically, than as hundreds of hex numbers. (I currently limp along using a crude file interface to MatLab to compensate for this weakness of ViewTrace. (IMHO Logic Analyzers should offer graphical display capability also.)) Suggestion 1 The placement algorithm Xilinx uses is, shall we say, less than spectacular. I believe it could be improved if it had some concept of where the data path elements were. It could then first place the adjacent data path elements so that the data flows in straight horizontal paths. Only after the data path elements were placed, would the random logic be placed. (I think I was first exposed to this idea by Philip Freidin.) To inform PPR of the data path, perhaps an attribute could be added to the busses, logic blocks, or both, if they are considered, by the designer, to be part of a data path. (I think I was first exposed to this idea by Philip Freidin.) Suggestion 2 Xilinx's floor planner is not as efficient as using schematic RLOCs because it's not as easily reusable. Also, you need the whole design captured and mapped, before being able to floor plan it. Unfortunately, there is only one constraint file per design. It would be nice if there could be a 'relative' constraint file for each page. This would permit me to relatively place each small circuit using the graphical floor planner tool. I could continue this relative placement as I worked up the hierarchy, until at the top, I could graphically, absolutely, place the whole thing. This just gives the constraint file approach the same flexibility and reusability as RLOCs and has the added attraction of being able to use the graphical floor planner instead of pencil and paper. If this technology were available, I could do a quick sch capture of two or three alternative architectures of a small circuit. I could then graphically check to see which one actually lended itself to better floor planing, before I settled on the best one. Once chosen, the relative constraint could be saved to a file, and pointed to by an unconnected page attribute. (Floor plan before schematic capture!) I know this would require better communication between Xilinx and ViewLogic, but I can wish can't I. Thanks for reading this. If you made it this far, you must have some interesting applications and a wish list of your own. Don't be shy. Dave Decker ddecker@diabloresearch.com mush@jps.netArticle: 5624
Dear sir,
Does anybody knows how to use internal clock of XC4000.
I try by connecting OSC4 through a BUF and get the CLK output. I
can translate the SCH file and get the XNF file without any errors. But
when I run XPREP, surprisingly, the error message comes out like this.
------------------------------------------------------------------------
XNFPREP: ERROR 4718:
Symbol 'ISAINF/CLOCK/U222' (type = OSC4, output signal =
ISAINF/CLOCK/F8M) is illegally connected.
Only the F8M pin and up to 2 of the F500K, F16K, F490, and
F15 pins of an OSC4 can be used.
Pin Name
-----------
F500K
F16K
F490
F15
Do you think it has something to deal with the library? Or do I need
to setup some configuration? Please give me suggestion how to use
internal clock of XC4000. If you don't mind, please describe in detail
how to connect OSC4 to the CLK pad.
----------------------------------------------------------------------------
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