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Does anyone know if Xilinx PPR goes usefully faster on a Pentium Pro. I have heard DOS software runs slower but given that its 32 bit software my hunch is taht it should go quicker. Cheers ChrisArticle: 5626
Hello all. There is no documentation in all the ALtera specs about how to configure their FLEX10K devices via JTAG from an embedded uC - all details are missing. Does anyone use this option and can tell where the doc is hidden or show the details ? I'd expect something like loading a CONFIGURE instruction to the IR then shifting the bitstream into DR similar to the passive serial mode ? Any hits welcome. Thanks, Andreas -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V B6,26 - 68131 Mannheim - Germany Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756 e-mail:kugel@mp-sun1.informatik.uni-mannheim.deArticle: 5627
In article <5fb3t7$vkq@carbon.cudenver.edu>, rauletta@erebor.cudenver.edu says... >WOW! That would be great! Warp2 when combined with SRAM FPGAs would be >fantastic for Universities! (For PLDs and CPLDs it is great, >but one time programmable parts are "problematical" for universities.) Don't forget Cypress FLASH370i ISR (In System Reprogrammable) devices which are also supported by the WARP (v4.1). http://www.cypress.com/cypress/prodgate/cpld/flash370i.html >and VHDL (VITAL) out for post-synthesis simulation. No fuss, no muss every >thing is there. Just add your favorite VHDL simulator (like Model Tech >V-System). Mmmh, 4000 pounds simulator with a 69 pounds synthesiser ;-) What I don't understand is why Cypress wrote such an impressive VHDL synthesiser and then complements it with a horrible editor and a near useless simulator. There are so many good shareware editors and simulators around which they could possible interface to with very little effort. Hans. > >-Rich Auletta >Article: 5628
Hi,
We are using the XILINX XACT software on our HP 712 and 715 workstations
(HP UX 10.20) are having troubles with the system drivers to send data
over the RS-232 serial interface to the xchecker socket. We have already
sent emails to XILINX's technical support, CA, USA, with no
satisfactory reply.
Is there anyone who is using XACT and the xchecker on HP workstations
and knows where we could get the right device drivers?
XILINX doesn't and didn't provide us with any useful/successful
information regarding this problem.
The following summarizes the problem we have:
1)------------------------------------------------------------------
We have bee trying without any success to download a bitstream over
this cable
by using the xchecker command and specifying the righ port
name. We have also looked at your web page and searched for
relevant informations regarding the configuration of the
xchecker, for example the page content below, which does not
apply to HP workstation configuration. The available ports to
the RS-232 are (obtained with ioscan):
tty 0 2/0/4 asio0 CLAIMED INTERFACE Built-in
RS-232C
/dev/cul0p0 /dev/diag/mux0 /dev/mux0
/dev/tty0p0
/etc ll /dev/cul0p0 /dev/diag/mux0 /dev/mux0 /dev/tty0p0
crw-rw-rw- 1 root other 1 0x000001 Jan 14 10:06 /dev/cul0p0
crw------- 2 bin bin 1 0x000080 Dec 6 1995
/dev/diag/mux0
crw------- 2 bin bin 1 0x000080 Dec 6 1995 /dev/mux0
crw--w--w- 1 bin bin 1 0x000000 Dec 6 1995 /dev/tty0p0
2)---------------------------------------------------------------
The device drivers didn't exist:
ls -l /dev/ttya /dev/ttyb
The result should be the following:
crw-rw-rw- 1 root12,0 month date time /dev/ttya
crw-rw-rw- 1 root12,1 month date time /dev/ttyb
so we created the nodes with ionode, with no success.
3)---------------------------------------------------------------
Creating softlinks doesn't help neither, as XILINX suggested
(Xilinx technical support case #123599) :
ln -s /dev/tty0p0 /dev/tty00
ln -s /dev/tty1p0 /dev/tty01
with no success.
4)---------------------------------------------------------------
When using the xchecker program from the command line, and appending
options specifying to take an existing (on our workstations) device
driver, we get error messages from the xchecker program.
5)---------------------------------------------------------------
Any on-line documentation of XILINX doesn't help us any further,
i.e. we have read and already browsed through all on-line
documentation on that subject.
In addition, the "hardware set-up" was checked several times, i.e.
external power supply for the xchecker and right connections between
the workstation, the cable and the XILINX FPGA on the PCB. We have
also tried different xchecker cables to eliminate the assumption
of a deffectuous cable.
----------------------------------------------------------------
It seems to me that the necessary serial drivers are missing,
in order to exchange data over the serial RS-232 interface to the
xchecker. What do we have to do install or configure those drivers
properly?
Thanks and best regards, Anders
+----------------------------------------------------------------+
| Anders Kugler | University of Tuebingen |
| | Computer Graphics Lab |
| | WSI / GRIS |
| Phone: [+49] (7071) 29-76361 | Auf der Morgenstelle 10 |
| Fax: [+49] (7071) 29- 5466 | D-72076 Tuebingen - Germany |
+----------------------------------------------------------------+
| email: kugler@gris.uni-tuebingen.de |
| URL: http://www.gris.uni-tuebingen.de/~kugler |
+----------------------------------------------------------------+
Article: 5629If you just want to run the clock from the osc4 to a small amount of internal logic, just connect it up, no special buffers. If you have lots of destinations, and want to use a global clock net, then you should connect the output of the osc4 to the input of a BUFGS (NOT a BUFGP), and the output of the BUFGS goes to the clock pins of all the FFs. This will use a global clock net. If you are trying to get the clock out of the chip, then either connect directly to the osc4 or the BUFGS output to the input of an OBUF. The OBUF output goes off-chip. Philip Freidin. In article <5fds2u$cr0@news.asu.edu> orachat@imap2.asu.edu writes: > Dear sir, > Does anybody knows how to use internal clock of XC4000. > I try by connecting OSC4 through a BUF and get the CLK output. I >can translate the SCH file and get the XNF file without any errors. But >when I run XPREP, surprisingly, the error message comes out like this. > >------------------------------------------------------------------------ > > XNFPREP: ERROR 4718: > Symbol 'ISAINF/CLOCK/U222' (type = OSC4, output signal = > ISAINF/CLOCK/F8M) is illegally connected. > > Only the F8M pin and up to 2 of the F500K, F16K, F490, and > F15 pins of an OSC4 can be used. > > > Pin Name > ----------- > F500K > F16K > F490 > F15 > > Do you think it has something to deal with the library? Or do I need >to setup some configuration? Please give me suggestion how to use >internal clock of XC4000. If you don't mind, please describe in detail >how to connect OSC4 to the CLK pad. > >---------------------------------------------------------------------------- >Article: 5630
Chris Hart wrote: > > Does anyone know if Xilinx PPR goes usefully faster on a Pentium Pro. > I have heard DOS software runs slower but given that its 32 bit > software my hunch is taht it should go quicker. > > Cheers Chris This question can be answered by: http://www.xilinx.com/techdocs/1363.htm -- / 7\'7 Paulo Dutra (paulo@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive (800) 255-7778 \_\/.\ San Jose, California 95124-3450 USA (408) 879-6797Article: 5631
Robert H. Owen wrote: > > Don Husby wrote: > > > > But, they kept the feature where a schematic always comes up > > zoomed halfway out inside a small window within another small > > window. You still have to click in three different places to > > bring up your schematic to a reasonable view. > > Hah! but you must have 7.2 or earlier. 7.3 will zoom a sheet to the same > level as the last time you shut it down. Or you can do some exploring > and write a simple OLE controller as I did using Delphi 2.0 to not only > force a full image but to automatically load the last used file. Before > we dropped the product, I was about to expand it to allow me to start it > up with any chosen sheet. > > Robert H. Owen > remove the # to email. Can you elaborate on that bit about OLE, Robert? Having done NO OLE coding what do you reccomend for resources. Does Viewlogic provide help or hooks? Could you post an example script? Kevin Steele ksteele@silcom.comArticle: 5632
Does anyone make a Demo Board for the Altera 10K50?Article: 5633
In article <331AA1A0.6733@mp-sun1.informatik.uni-mannheim.de>, kugel@mp-sun1.informatik.uni-mannheim.de writes... >Hello all. > >There is no documentation in all the ALtera specs about >how to configure their FLEX10K devices via JTAG from an >embedded uC - all details are missing. > >Does anyone use this option and can tell where the doc >is hidden or show the details ? > >I'd expect something like loading a CONFIGURE instruction >to the IR then shifting the bitstream into DR similar to >the passive serial mode ? I would also be interested in any information on configuring FLEX 10K through the JTAG interface! Daniel Lang dbl@hydra0.caltech.eduArticle: 5634
Jeffrey L. Hutchings (hutch@convergent-design.com) wrote: : It appears that the people who wrote/ported the old program : new a great deal about CAD software but were horrible Windows : programmers. It looks like Workview Office was developed by OK Windows : programmers who know nothing about CAD. : What I can't understand is why the BETA tester's input : was ignored. I know for a fact the everyone was screaming : for them to keep the command line and the other features : but they chose not to. Only Viewlogic knows why. I agree with all of this with the difference that I switched from Workview DOS to PROseries. It was horrible! : Oh yeah. Wait till you try ViewSim. You'll love the : performance un-enhancement. And then try ViewSynthesis (if you can make it work).Article: 5635
In article <3312356E.30BE@xilinx.com>,
Eric Dellinger <ericd@xilinx.com> wrote:
>So, SRAM FPGA designs are about as secure as compiled, stripped
>programs. They
>are trivial to copy, but it is extremely difficult (if not impossible)
>to reconstruct
>semantics. Far less work to just do your own design, rather than rip
>one off...
Does this realization mean that Xilinx will be releasing documentation on
the contents of its bit streams? (Fears of reverse engineering being the
standard excuse, in the past, for not doing so.)
No, I'm not seriously expecting it, since it was always clear that this
was just an excuse, but it would be nice...
--
Committees do harm merely by existing. | Henry Spencer
-- Freeman Dyson | henry@zoo.toronto.edu
Article: 5636I was told last week that this still with Altera but is possible, just ask them and they will work with you! If you have any luck it would be good to know as we have yet to be convinced that Altera are really on our (engineers) side, Fatcory supported is the term they use I believe. In article <3MAR199709563823@hydra1.tyrvos.caltech.edu>, Daniel Lang <dbl@hydra1.tyrvos.caltech.edu> writes >In article <331AA1A0.6733@mp-sun1.informatik.uni-mannheim.de>, kugel@mp- >sun1.informatik.uni-mannheim.de writes... >>Hello all. >> >>There is no documentation in all the ALtera specs about >>how to configure their FLEX10K devices via JTAG from an >>embedded uC - all details are missing. >> >>Does anyone use this option and can tell where the doc >>is hidden or show the details ? >> >>I'd expect something like loading a CONFIGURE instruction >>to the IR then shifting the bitstream into DR similar to >>the passive serial mode ? > >I would also be interested in any information on configuring FLEX 10K >through the JTAG interface! > >Daniel Lang dbl@hydra0.caltech.edu > -- David AtkinsArticle: 5637
Have you looked at Application Note 59 - Configuring FLEX 10K devices ?
The datasheet mentions App note 39 - JTAG Boundary Scan testing in
Altera devices. I haven't seen that one but it sounds close.
Steve.
===================================================================
Very funny Scotty. Now beam down my clothes.
-------------------------------------------------------------------
TLA Microsystems Ltd. PO Box 15-680, New Lynn
Electronic Product Design Auckland, New Zealand
Microcontroller Specialists Ph. +64 9 820-2221
steveb@kcbbs.gen.nz Fax. +64 9 820-1929
===================================================================
Article: 5638If you are using or going to use 68HC16 microcontroller, you may be interested to look at HC16BGND, an advanced programmer’s interface that helps you to develop, test, and refine your assembly language programs for MOTOROLA’s 68HC16 microcontrollers. The key features include: - Run under MS Windows - Interface through PC’s parallel port - Motorola suggested 10 pin target connector - Download and debug HC16 assembly language program in S19 or HEX format - trace through your code by step through or step over - set up to 100 breakpoints - On-screen editing of register and data memory - On-fly assembly of instruction using mnemonics in program memory - Open infinite Register, Program, and Data windows - Watch window so that you can watch important variables - Exchange data through Windows clipboard - File I/O which can be used to automatically read a hex input file into the file and write the result to an output file. - Easy to use. Just click on the menu with left mouse or click on the windows’ area. Everything is self-explained - Convenient and easy to install due to its parallel port interface. You can use laptop to do an on-site demonstration of you products - Low cost - 30 day money back guarantee and one year product warranty For more information or need a demo program, see http://users.why.net/wctech/hc16bgnd.htm, or FTP to FTP.WHY.NET/FTP/PUB/USERS/WCTECH, or send email to WCTECH@WHY.NET Larry Chen WC TechnologyArticle: 5639
Mark Garaway <mgaraway@deltanet.com> wrote: : I have just received my order from APS for the APS-X84-FBV which is the : X84 board and the XILINX Foundation Base System. I finally got mine, too, today. Now I need to install and check it out.... Danny Kumamoto mailto:dnk@pobox.com http://www.pobox.com/~dnk TEL: +1 512-918-3640 Postal: 13492 Research Blvd., Suite 120-295, Austin, TX 78750-2254, U.S.A.Article: 5640
Steve Baldwin wrote: > > Have you looked at Application Note 59 - Configuring FLEX 10K devices ? > > The datasheet mentions App note 39 - JTAG Boundary Scan testing in > Altera devices. I haven't seen that one but it sounds close. > > Steve. > > =================================================================== > Very funny Scotty. Now beam down my clothes. > ------------------------------------------------------------------- > TLA Microsystems Ltd. PO Box 15-680, New Lynn > Electronic Product Design Auckland, New Zealand > Microcontroller Specialists Ph. +64 9 820-2221 > steveb@kcbbs.gen.nz Fax. +64 9 820-1929 > =================================================================== AP NOte 39 covers all JTAG functions EXCEPT CONFIGURATION ! AP note 59 covers all config modes except via JTAG ! So these don't help at all. I have the Altera CDROM and I looked at all docs related to configuration or JTAG: there are no details about that topic. Any more hints ? Andreas -- Andreas Kugel, Karolinenstr. 4 76135 Karlsruhe, Germany Phone: (49) 721 377865, Fax (49) 721 937 49 12 E-mail: akugel@t-online.deArticle: 5641
Steve Baldwin wrote: > > Have you looked at Application Note 59 - Configuring FLEX 10K devices ? > > The datasheet mentions App note 39 - JTAG Boundary Scan testing in > Altera devices. I haven't seen that one but it sounds close. > > Steve. > > =================================================================== > Very funny Scotty. Now beam down my clothes. > ------------------------------------------------------------------- > TLA Microsystems Ltd. PO Box 15-680, New Lynn > Electronic Product Design Auckland, New Zealand > Microcontroller Specialists Ph. +64 9 820-2221 > steveb@kcbbs.gen.nz Fax. +64 9 820-1929 > =================================================================== AP NOte 39 covers all JTAG functions EXCEPT CONFIGURATION ! AP note 59 covers all config modes except via JTAG ! So these don't help at all. I have the Altera CDROM and I looked at all docs related to configuration or JTAG: there are no details about that topic. Any more hints ? Andreas -- Andreas Kugel, Karolinenstr. 4 76135 Karlsruhe, Germany Phone: (49) 721 377865, Fax (49) 721 937 49 12 E-mail: akugel@t-online.deArticle: 5642
Steve Baldwin wrote: > > Have you looked at Application Note 59 - Configuring FLEX 10K devices ? > > The datasheet mentions App note 39 - JTAG Boundary Scan testing in > Altera devices. I haven't seen that one but it sounds close. > > Steve. > > =================================================================== > Very funny Scotty. Now beam down my clothes. > ------------------------------------------------------------------- > TLA Microsystems Ltd. PO Box 15-680, New Lynn > Electronic Product Design Auckland, New Zealand > Microcontroller Specialists Ph. +64 9 820-2221 > steveb@kcbbs.gen.nz Fax. +64 9 820-1929 > =================================================================== AP NOte 39 covers all JTAG functions EXCEPT CONFIGURATION ! AP note 59 covers all config modes except via JTAG ! So these don't help at all. I have the Altera CDROM and I looked at all docs related to configuration or JTAG: there are no details about that topic. Any more hints ? Andreas -- Andreas Kugel, Karolinenstr. 4 76135 Karlsruhe, Germany Phone: (49) 721 377865, Fax (49) 721 937 49 12 E-mail: akugel@t-online.deArticle: 5643
Steve Baldwin wrote: > > Have you looked at Application Note 59 - Configuring FLEX 10K devices ? > > The datasheet mentions App note 39 - JTAG Boundary Scan testing in > Altera devices. I haven't seen that one but it sounds close. > > Steve. > > =================================================================== > Very funny Scotty. Now beam down my clothes. > ------------------------------------------------------------------- > TLA Microsystems Ltd. PO Box 15-680, New Lynn > Electronic Product Design Auckland, New Zealand > Microcontroller Specialists Ph. +64 9 820-2221 > steveb@kcbbs.gen.nz Fax. +64 9 820-1929 > =================================================================== AP NOte 39 covers all JTAG functions EXCEPT CONFIGURATION ! AP note 59 covers all config modes except via JTAG ! So these don't help at all. I have the Altera CDROM and I looked at all docs related to configuration or JTAG: there are no details about that topic. Any more hints ? Andreas -- Andreas Kugel, Karolinenstr. 4 76135 Karlsruhe, Germany Phone: (49) 721 377865, Fax (49) 721 937 49 12 E-mail: akugel@t-online.deArticle: 5644
Steve Baldwin wrote: > > Have you looked at Application Note 59 - Configuring FLEX 10K devices ? > > The datasheet mentions App note 39 - JTAG Boundary Scan testing in > Altera devices. I haven't seen that one but it sounds close. > > Steve. > > =================================================================== > Very funny Scotty. Now beam down my clothes. > ------------------------------------------------------------------- > TLA Microsystems Ltd. PO Box 15-680, New Lynn > Electronic Product Design Auckland, New Zealand > Microcontroller Specialists Ph. +64 9 820-2221 > steveb@kcbbs.gen.nz Fax. +64 9 820-1929 > =================================================================== AP NOte 39 covers all JTAG functions EXCEPT CONFIGURATION ! AP note 59 covers all config modes except via JTAG ! So these don't help at all. I have the Altera CDROM and I looked at all docs related to configuration or JTAG: there are no details about that topic. Any more hints ? Andreas -- Andreas Kugel, Karolinenstr. 4 76135 Karlsruhe, Germany Phone: (49) 721 377865, Fax (49) 721 937 49 12 E-mail: akugel@t-online.deArticle: 5645
Hans Tiggeler (ees1ht@ee.surrey.ac.uk) wrote: : In article <5fb3t7$vkq@carbon.cudenver.edu>, rauletta@erebor.cudenver.edu : says... : >WOW! That would be great! Warp2 when combined with SRAM FPGAs would be : Don't forget Cypress FLASH370i ISR (In System Reprogrammable) devices which : are also supported by the WARP (v4.1). : http://www.cypress.com/cypress/prodgate/cpld/flash370i.html True - we have been having great success with the non ISR version of the 374 part. But! :) I want to be able to include SRAM's in the design ala Xilinx (synchronous dual-ported SRAMs). For pedagogical reasons :) Also, the PLD/CPLD architecture is not that efficient for more complex designs. And simply not big enough! : Mmmh, 4000 pounds simulator with a 69 pounds synthesiser ;-) What I don't : understand is why Cypress wrote such an impressive VHDL synthesiser and then : complements it with a horrible editor and a near useless simulator. There are : so many good shareware editors and simulators around which they could : possible interface to with very little effort. Nova is a jedec simulator and is included for historical reasons - and is more than sufficient for anything one could imagine doing in a 16V8, 20V8, or 20V10. In fact to test a 16v8 it is very quick. For simple designs a waveform editor has a lot of advantages over a 4000 pound gorilla of a simulator. Warp 4.1 supports a range of simulators for post synthesis simulation, both VHDL and Verilog. I think the notion here is point tools. The FPD vendor supplies the synthesis tools. The customer uses a general purpose simulator. For both pre and post synthesis simulation - and of course Warp includes static timing tools for FPGAs. I think the assumption that a user of Warp2 will have already invested in a HDL simulator is a reasonable one. And expected. Supplying tools that can work together is the whole notion behind CFI's goal of having open EDA tools, and standard languages such as VHDL and Verilog. If you look at say the Xilinx Foundation series they are very close to the same model as Warp2. And I think also Synopsys FPGA Express. It is not clear to me from the web ads if and what sort of simulator they each include or support. As to an editor, it clearly has some problems. I suggest using lemmy the windows 95/NT vi clone :) I take that back! Please don't start a "my editor iis better than your editor" wars. I mean the GNU emacs port to NT! Warp2 has really matured and does what it advertizes very well - so well in fact undergraduates can successfully use it independently to produce first time working designs for their senior design projects... that fill a 374 Now if I could just figure out how to feed the VHDL output of the Synopsys behavioral compiler into Warp2.... -Rich Auletta Electrical Engineering University of Colorado at DenverArticle: 5646
Steve Baldwin wrote: > > Have you looked at Application Note 59 - Configuring FLEX 10K devices ? > > The datasheet mentions App note 39 - JTAG Boundary Scan testing in > Altera devices. I haven't seen that one but it sounds close. > > Steve. Steve, AP NOte 39 covers all JTAG functions EXCEPT CONFIGURATION ! AP note 59 covers all config modes except via JTAG ! So these don't help at all. I own the Altera CDROM and I looked at all docs related to configuration or JTAG: no details about that topic. There are exactly two statements in all the docs: 1) JTAG configuration of FLEX10K is possible 2) You must use the ALTERA bitblaster to use -> Very useless information Any more hints ? Andreas -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V B6,26 - 68131 Mannheim - Germany Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756 e-mail:kugel@mp-sun1.informatik.uni-mannheim.deArticle: 5647
ICCIMA'98
International Conference on Computational Intelligence
and Multimedia Applications
9-11 February 1998
Monash University, Gippsland Campus, Churchill, Australia
C A L L F O R P A P E R S
The International Conference on Computational Intelligence and
Multimedia Applications will be held at Monash University on 9-11
February 1998. The conference will provide an international forum for
discussion on issues in the areas of Computational Intelligence and
Multimedia for scientists, engineers, researchers and practitioners.
The conference will include sessions on theory, implementation and
applications, as well as the non-technical areas of challenges in
education and technology transfer to industry. There will be both oral
and poster sessions. Several well-known keynote speakers will address
the conference.
Conference Topics Include (but not limited to):
Artificial Intelligence
Artificial Neural Networks
Artificial Intelligence and Logic Synthesis
Functional decomposition
Pattern Recognition
Fuzzy Systems
Genetic Algorithms
Intelligent Control
Intelligent Databases
Knowledge-based Engineering
Learning Algorithms
Memory, Storage and Retrieval
Multimedia Systems
Formal Models for Multimedia
Interactive Multimedia
Multimedia and Virtual Reality
Multimedia and Telecommunications
Multimedia Information Retrieval
Special Sessions:
Artificial Intelligence and Logic Synthesis: intelligent algorithms
for logic synthesis; functional decomposition in machine learning,
pattern recognition, knowledge discovery and logic synthesis;
evolutionary and reconfigurable computing with FPGAs. Chair: Lech
Jozwiak, Eindhoven University, Netherlands.
Multimedia Information Retrieval: segmentation of audio, image and
video; feature extraction and representation; semi-automatic text
annotation techniques; indexing structure; query model and retrieval
methods; feature similarity measurement; system integration issues;
prototype systems and applications. Chair: Guojun Lu, Monash
University, Australia.
Pre-Conference Workshops and Tutorial:
Proposals for pre-conference workshops and tutorials relevant to the
conference topics are invited. These are to be held on Saturday 7th
February and Sunday 8th February at the conference venue. People
wishing to organise such workshops or tutorials are invited to submit
a proposal at the same time as submission deadline for papers. The
accepted proposals will be advertised.
Special Poster Session:
ICCIMA'98 will include a special poster session devoted to recent
work and work-in-progress. Abstracts are solicited for this session
(2 page limit) in camera ready form, and may be submitted up to 30
days before the conference date. They will not be refereed and will
not be included in the proceedings, but will be distributed to
attendees upon arrival. Students are especially encouraged to submit
abstracts for this session.
Invited Sessions
Keynote speakers (key industrialists, chief research
scientists and leading academics) will be addressing
the main issues of the conference.
Important Dates:
Submission of papers received latest on: 7 July 97
Notification of acceptance: 19 September 97
Camera ready papers & registration received by: 24 October 97
Submission of Papers
Papers in English reporting original and unpublished research results
and experience are solicited. Electronic submission of papers via
e-mail in postscript or Microsoft Word for Windows format directly to
the General Chair are acceptable and encouraged for the refereeing
process. If not submitting an electronic version, please submit three
hard copy originals to the General Chair. Papers for refereeing
purposes must be received at the ICCIMA 98 secretariat latest by 7
July 1997. Notification of acceptance will be mailed by 19 September
1997.
Page Limits
Papers for refereeing should be double-spaced and must include an
abstract of 100-150 words with up to six keywords.
The accepted papers will need to be received at the ICCIMA 98
secretariat by 24 October 1997 in camera ready format. As a general
guide the camera ready paper will need to be in a single-spaced two
column page format using 10 point fonts. A final preparation format
for the camera-ready papers will be provided upon notification of
acceptance. Camera ready papers exceeding 6 pages (including abstract,
all text, figures, tables and references etc.) will be charged an
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Evaluation Process
All submissions will be refereed based on the following criteria by
two reviewers with appropriate background.
originality
significance
contribution to the area of research
technical quality
relevance to ICCIMA 98 topics
clarity of presentation
Referees report will be provided to all authors.
Check List
Prospective authors should check that the following items are attached
and guidelines followed while submitting the papers for refereeing
purpose.
* The paper and its title page should not contain the name(s) of
the author(s), or their affiliation
* The paper should have attached a covering page containing
the following information
-title of the paper
-author name(s), Affiliation, mail and e-mail addresses, phone
and fax numbers
-Conference topic area
-up to six keywords
* The name, e-mail, phone, fax and postal address of the contact
person should be attached to the submission
Visits and Social Events
Industrial and sight seeing visits will be arranged for
the delegates and guests. A separate program will be
arranged for companions during the conference.
General Chair:
Henry Selvaraj
Gippsland School of Computing
& Information Technology
Monash University,
Churchill, VIC, Australia 3842
Henry.Selvaraj@fcit.monash.edu.au
Phone: +61 3 9902 6665
Fax: +61 3 9902 6842
International Programme Committee:
Abdul Sattar, Griffith University, Australia
Andre de Carvalho, University of Sao Paulo, Brazil
Bob Bignall, Monash University, Australia
Brijesh Verma, Griffith University, Australia (Programme Chair)
Dinesh Patel, Surrey University, UK
Henry Selvaraj, Monash University, Australia
Hyunsoo Lee, University of Yonsei, Korea
Jan Mulawka, Warsaw University of Technology, Poland
Jong-Hwan Kim, Korea Advanced Institute of Science &
Technology, Korea
Lech Jozwiak, Eindhoven Univ. of Tech, Netherlands
Marek Perkowski, Portland State University, USA
Michael Bove, MIT Media Laboratory, USA
Mikio Takagi, University of Tokyo, Japan
Nagarajan Ramesh,Tencor Instruments, USA
Ramana Reddy, West Virginia University, USA
Regu Subramanian, Nanyang Tech University, Singapore
Sargur Srihari, State University of New York, USA
Shyam Kapur, James Cook University, Australia
Sourav Kundu, Kanazawa University, Japan
S. Srinivasan, IIT, Madras, India
Subhash Wadhwa, IIT, Delhi, India
Tadeusz Luba, Warsaw University of Technology, Poland
Vishy Karri, University of Tasmania, Australia
Xin Yao, University of New South Wales, Australia
International Liaison
Asian Liaison:
Regu Subramanian, Network Technology Research
Centre, Nanyang Technological University, Singapore
U.S. Liaison:
Marek Perkowski, Portland State University, USA
European Liaison:
Tadeusz Luba, Warsaw University of Technology,
Poland
Organising Committee:
Bob Bignall, Monash University, Australia
Baikunth Nath, Monash University, Australia
Vishy Karri, University of Tasmania, Australia
Syed M. Rahman, Monash University, Australia
Bala Srinivasan, Monash University,Australia
Cheryl Brickell, Monash University, Australia
Andy Flitman, Monash University, Australia
Lindsay Smith, Monash University, Australia
Further Information:
Conference Email :
iccima98@fcit.monash.edu.au
Conference WWW Page:
http://www-gscit.fcit.monash.edu.au/~iccima98
Article: 5648Paulo Dutra wrote: > > Chris Hart wrote: > > > > Does anyone know if Xilinx PPR goes usefully faster on a Pentium Pro. > > I have heard DOS software runs slower but given that its 32 bit > > software my hunch is taht it should go quicker. > > > > Cheers Chris > > This question can be answered by: > > http://www.xilinx.com/techdocs/1363.htm > > -- > / 7\'7 Paulo Dutra (paulo@xilinx.com) Unfortunately this tech note doesn't quite answer the question Chris asked, especially the 'usefully' part. Does anyone have any idea of the kind of performance improvement, specifically run time for PPR, you get from changing to a 200 MHz P6 from a 166 MHz P5, as a ballpark percentage? This information would help us determine if it is worthwhile upgrading our PCs at this time. ta very much, Syms.Article: 5649
Chris Hart wrote:
> Does anyone know if Xilinx PPR goes usefully faster on a Pentium Pro.
> I have heard DOS software runs slower but given that its 32 bit
> software my hunch is taht it should go quicker.
Just a factoid:
I once tested a Pentium-100 against a PPRO-200.
The design was a 4010 with abt. 92% of the FlipFlops used and no
completely free CLBs. There were _lots_ of synthesized XBLOX
devices; the rest was schematics.
Compilation time fell from 48 to 13 minutes for netlist generation
to loadable bit file. I tried this only once (why wait?) and did not
enforce equal seed numbers for the placer.
The machines both had 32M of ram; the P100 had everything on its
local SCSI disks; the PPRO200 accessed the XILINX software via
Novell Netware + Ethernet. Disks probably play no role in this
cpu bound application. Software was Xact 6.01 under DOS without
Windows.
Your mileage may vary.
Gerhard
--
Gerhard Hoffmann on the air: dk4xp
in the air: D-1441
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