Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Aage Farstad wrote: > = > Can anybody give me a hint of what's wrong with my newsreader? Every > time I try to open a message from this guy, my newsreader (netscape3.0)= > says: No Such article, Perhaps the article has expired! He is the only > one treated this way! > = The same happens to me! I am also using Netscape 3.0 now. Bj=F8rn BL. -- = _______________________________________________________________________ | s-mail: e-mail: | || | | Bjorn B. Larsen, Ph. D. Bjorn.B.Larsen@iet.hist.no | ||__ |__ | Sor-Trondelag College http://www.hist.no/~bbl | || \| \| Gunnerus gate 1 | ||__/|__/|_ N-7005 TRONDHEIM tel: +47 - 7389 6288 | | NORWAY fax: +47 - 7389 6286 | |_____________________________________________________________________|Article: 5226
Hello, I'm using a Xilinx 4013E PG223 chip and currently the rest of the hardware is to be mounted with wire wrap sockets. Problem so far is I'm unable to find an 18x18,223 wire wrap socket. Are these just not available? Any other suggestions? Thanks, Scott McIntosh gtd750a@prism.gatech.eduArticle: 5227
Scott D. Davilla (davilla@mail.4pi.com) wrote: > In article <32E7C653.3D49@ids.net>, Ray Andraka <randraka@ids.net> wrote: > If you're looking to take the free PCI dev kit and turn a quick PCI > design, forget it. While the design looks ok and will work to understand Well, I am currently working exactly on the PCI dev kit, and I aggree with you about its many bugs. It helped me a little with understanding the basic behaviour of the PCI bus, but is some miles away from following the PCI specification. Julio de Melo ------------------------------------------------------------------------ Prof. Julio de Melo Tel: 55-31-499-5477 Departamento de Engenharia Eletronica 238-1955 Escola de Engenharia da UFMG 499-4848 Rua Espirito Santo, 35 - Sala 303 Home: 55-31-296-4338 30160-030 Belo Horizonte, MG Fax: 55-31-499-5480 BrazilArticle: 5228
Aage Farstad wrote: > > Hi all, > > Can anybody give me a hint of what's wrong with my newsreader? Every > time I try to open a message from this guy, my newsreader (netscape3.0) > says: No Such article, Perhaps the article has expired! He is the only > one treated this way! > > Best Regards Aage Farstad > > aage.farstad@ffi.no Yeah, me too. I assume it is the Steve Knapp at Xilinx. I fired him an email suggesting he look at it too. No answers yet. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 5229
Hello,
I am currently using Actel Designer 3.1 on a Pentium PC. Whenever I try
to open the Windows Programming (APS) program, I get a pesky error
claiming that the software can't find certain libraries and other files.
This occurs primarily after the machine has been powered up for the first
time. Once I force my way through the error screens (which sometimes
works), the software seems to run fairly well. When the failure occurs, it
causes the PC to lock up completely sometimes, causing me to reboot (and
hence the cycle starts over again).
Wondering if anyone else has had problems with the Actel Designer 3.1
software...
Thanks.
Please reply via email to: larry@metraplex.com
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 5230Rick Filipkiewicz wrote: > > Probably the major difference between the two types is that CPLDs, or > ``fat PALs'', have very simple and predicatable pin-to-pin > timing. This means that, within fairly tight bounds, recompiling & > rerouting a design won't cause speed varitions in the resulting > device. FPGAs on the other hand have a large amount of internal > resource and variable routing delays. Keeping a given performance > level over design changes can be difficult and is highly dependent on > the efficacy of the vendor's floor planning and place/route tools. > This isn't rock solid true. The routing in some of the bigger CPLDs gets a little less predictable when you consider the paths through the global routing blocks to connect groups of macrocells. Still more predictable than the autoplaced and routed FPGAs. On the otherhand, FPGA route timing is deterministic if enough effort is put in handcrafting the design. This is particularly true with the Atmel/NSC/CLi architecture. > I think a rule of thumb might be to use FPGAs for ``rigid'' devices > like data paths, arithmetic units etc. or for non-speed critical bits > of random logic. CPLDs are better suited to the high clock rate > control logic that might have to be rebuilt frequently during the > prototype phase. > > CPLDs are also a lot cheaper! > > But I can pack much much more function into an FPGA! I use FPGAs for most stuff. I save the CPLDs for relatively simple things (usually with lots of combinatorial) requiring fast pin to pin times. Examples of where I use CPLDs instead of FPGAs are for fast microprocessor interfaces and for the configuration controllers for reconfigurable computers. The big handicap with CPLDs is the small number of available registers (and if you don't use the input registers in many devices, the actual number available is significantly less than the number of registers quoted on the datasheet). -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 5231
Steve Casselman wrote: > > Ed Vogel wrote: > > > > I am considering the design of a dynamically reconfigurable logic > > platform. It is more in line with tinkering than a serious product > > application. Has anyone else tried to build an in circuit programmable > > interface inside an FPGA or CPLD? > > > > I realize that Lattice offers something of this sort(pseudo JTAG port) > > but I want to go one step further; to make connections between "user > > defined" muxes surrounding "user defined" logic blocks. In short I want > > to waste the resources provided for me by the chip manufacturer and third > > party tool designers to functionally design and program an FPGA or CPLD > > in favor of using those resources to build a "scaffolding" inside to > > facilitate the construction of dynamically reconfigurable logic. I > > realize this is wasteful. I want control over routing delays and > > repeatability without consulting a third party. It also would allow > > greater flexibility in interfacing to C compiler outputs. Just curious. . > > . > Well....:) I just read a simular paper where the design was > reconfigurable > switches and 2-bit processors. You want to prototype a FPGA in an FPGA. > Sounds > very feasible for a small device. Now if you wanted to emulate an > emulator > that might be a different story. > > You might look to my newest most favorite page > http://dec.bournemouth.ac.uk/dec_ind/decind6/drhw_page.html > For all you old timers: check this page out it is really very good. > > Steve Casselman > http://www.vcc.com/hotann.html > The IBM PC of Reconfigurable Computing (TM) Thanks for the link to that page. It is one I hadn't seen before. I think what Ed was looking for was if anyone had done a configuration controller in either an FPGA or a CPLD. If that is what he is asking, then the answer is yes. I've done several designs using a pld to control the configuration of one or more FPGAs. The most recent uses a Lattice device as a configuration controller for four FPGAs. The host processor writes a single 32 bit word to the Lattice to describe which of 16 configurations stored in an eeprom is to be loaded into each of the four FPGAs. The Lattice then takes care of loading the configurations, checking for errors and interrupting the host when the configuration is done or faulted. A simple extension allows an FPGA to trigger the reconfiguration or even supply the pointer to the next desired program. The FPGAs each have independent configuration controls and reside on a common databus so that each device can be reconfigured independently of the others. Another case used an NSC CLAy31 and an SRAM program store to control configuration of a tiled array of 4 CLAy31s and provide a host interface. That design is described in my paper "A dynamic hardware video processing platform" presented at SPIE's Photonics East last Novemeber (that paper can be found on my website). Of course, there is the Xilinx 6200 family, which has a microprocessor style interface that allows direct access to the configuration built right on the chip. Steve Casselman's company, VCC, has a PCI board available that uses the 6200 for a reconfigurable computing platform. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 5232
joerg and todd, i know you're targetting actel, but you may find my autologic/xilinx experience interesting. early last year, i was dismayed to discover that al2, as well as other synth tools, do not know how to infer counters. i had assumed such inference to be necessary to obtain optimal speed results. xilinx had gone to pains to develop high speed counter macros in their library which take advantage of special high speed carry circuits in the xilinx devices (ripple carry but faster than CLA implementations according to xilinx). upon further investigation, i discovered that mentor (who built the synth library with xilinx) had put in a hook which allowed al2 to map your code into some of the special xilinx architectural features. for counters, this allows mapping to a fast incrementer. you might want to see if this has been done for the actel library as well. for xilinx, this appears in the alui gui under: setup > technology environment macro_mapping = (XBLOX_MAPPING, None) this isn't counter inference, but at least your undissolved operators (in this case "+") have a chance of being mapped into a fast architectural feature. by the way, if counter inference is important to you, i hear exemplar's (http://www.exemplar.com) new leonardo can infer counters and RAM. hope this helps. _ Lance Gin "off the keyboard, over the bridge Delco Systems-GM Hughes Electronics through the gateway, C43LYG@dso.hac.com nothing but NET!"Article: 5233
In article <32F1B27D.4596@ffi.no>, Aage Farstad <aage.farstad@ffi.no>
writes
>Hi all,
>
>Can anybody give me a hint of what's wrong with my newsreader? Every
>time I try to open a message from this guy, my newsreader (netscape3.0)
>says: No Such article, Perhaps the article has expired! He is the only
>one treated this way!
I get them OK with my newsreader (Turnpike).
Leon
--
Leon Heller, G1HSM
leon@lfheller.demon.co.uk
Tel: +44 (0) 118 947 1424 (home)
+44 (0) 1344 385556 (work)
Article: 5234Ray Andraka wrote: > > Aage Farstad wrote: > > > > Hi all, > > > > Can anybody give me a hint of what's wrong with my newsreader? Every > > time I try to open a message from this guy, my newsreader (netscape3.0) > > says: No Such article, Perhaps the article has expired! He is the only > > one treated this way! > > > > Best Regards Aage Farstad > > > > aage.farstad@ffi.no > Yeah, me too. I assume it is the Steve Knapp at Xilinx. I fired him > an > email suggesting he look at it too. No answers yet. > > -Ray Andraka, P.E. > Chairman, the Andraka Consulting Group > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://www.ids.net/~randraka Strange, but his posts show up in dejanews. ScottArticle: 5235
larry@metraplex.com wrote: > > Hello, > > I am currently using Actel Designer 3.1 on a Pentium PC. Whenever I try > to open the Windows Programming (APS) program, I get a pesky error > claiming that the software can't find certain libraries and other files. > This occurs primarily after the machine has been powered up for the first > time. Once I force my way through the error screens (which sometimes > works), the software seems to run fairly well. When the failure occurs, it > causes the PC to lock up completely sometimes, causing me to reboot (and > hence the cycle starts over again). > > Wondering if anyone else has had problems with the Actel Designer 3.1 > software... > > Thanks. > > Please reply via email to: larry@metraplex.com > -------------------==== Posted via Deja News ====----------------------- > http://www.dejanews.com/ Search, Read, Post to Usenet had lots of trouble with it and some other versions at first. actel seems to have shipped lots of different scsi cards (adaptec, western digital, trantor, who knows). i have several pentiums running activator 2s's (which I assume you have) and they run fine under windows 3.1, 3.11, and win '95. haven't tried win 'nt. anyways, my path to success was getting the up to date adaptec card for windows programming. rk p.s. when i was in trouble i programmed via dos (aps2) and not a dos shell in windows and it worked perfectly until i was able to get the new adapters. and i found consistent results with having the activator powered when the pc was powered; with some cards the order didn't matter (western digital) and some it did (adaptec). frequently i would boot the computer with the activator off to change adapters and then turn on the activator which was bad. also, rebotting pc didn't work, had to power cycle it. p.s.s. another gotcha was on one system i forgot the /z parameter on the scsi device driver line in config.sysArticle: 5236
Wayne Turner wrote: > > In article <5cs4oq$cf5@borg.svpal.org>, garyk@svpal.svpal.org (George Noten) wrote: > >Wayne Turner (waynet@goodnet.com) wrote: > > [snip] > >: What is their option? Build a fab to make FlashLogic? They are put in the > >: same situation as you are. Obsolescence happens. > > > > They could absorb part of the costs. Or think twice before they bought > > the part. Or think three times before they converted it from EPROM to > > FLASH. > > 1. They are absorbing part of the costs by making a large end-of-life buy on > wafers. > > 2. Do you think they would have bought the part if they knew 2 years down the > road that Sharp wasn't going to want to make it anymore? > > 3. Converted? What the hell are you talking about? It was FLASH when Intel > owned it, it was just called FlexLogic. When Altera bought it they had to > change the name because they already had the FLEX 8000 family and didn't want > it to be confused. So they named the part according to what it really was: > FLASH. Hence the name FlashLogic. The Intel part was EPROM based, Altera re-engineered it to Flash, then dropped it less than a year later. The Flash based EPX880 was a direct drop in replacement for the IFX780, so customer support shouldn't be based on the 880 part but on the 780 as well which was available for 4-5 years. > > Perhaps you should come back after you've read up a bit. Likewise! ;^) > > >: > Yes, but this part never got out of "preliminary" category and there are > >: > no customers that were using it for years. > > > >: Does it matter how long people were using it? > > > > Yes. The longer the part is available the more designs are utilizing it. > > And how long was it out? See above regardign the 780. > > >: If it does, how long had people > >: been using FLASHlogic, considering it has only been around for a few years > >: (and owned by Altera for less than two)? > > > > For our company it was long enough to use it in about half of our products. > > What is the product life? The parts will be available to be shipped for > another year and a half. Is that not long enough notice? Not really. Some designs are rather low volume but long lived where a redesign is a major undertaking. As it stands now, I have a design that was based on the 780 that I now use the 880 on. Now the 880 is being obsoleted. I either have to redesign the product, or guess the size of the market in 6 months. Either way, due to the loss of the FlashLogic 880 part, I have just incured a rather major expense. > > >: No, it wasn't. If your wafer supplier won't make the wafer anymore, what can > >: you do if they are the only fab with that technology? > > > > Don't make customers pay for it. Especially if there are so few of them as > > we are being told. > > You didn't answer the question. > > Wayne -- Dean Brown DKBArticle: 5237
In article <32F2441F.3A7E@prism.gatech.edu>, Scott McIntosh <gtd750a@prism.gatech.edu> writes... >Hello, > I'm using a Xilinx 4013E PG223 chip and currently the rest >of the hardware is to be mounted with wire wrap sockets. Problem >so far is I'm unable to find an 18x18,223 wire wrap socket. Are >these just not available? Any other suggestions? Try one of these companies Advanced Interconnections, West Warwick, RI (401) 823-5200 McKenzie Technology, Freemont, CA (510) 651-2700 Mill-Max Mfg. Corp., Oyster Bay, NY (516) 922-6000 They all make a HUGE number of PGA sockets including several variations on the 18x18 223 pin PGA socket. Daniel Lang dbl@hydra0.caltech.eduArticle: 5238
(apologies if this is a multiple send) Peter Alfke wrote: > > The Xilinx 1996 Data Book lists the power consumption ov various > ingredients as mW/ MHz or mW/million transitions per second ( not the > same thing! ). > It is up to the user to estimate the internal activity. <deleted> > > Peter Alfke, Xilinx Applications About a year ago after experiencing burned fingers from a maxed out 30,000 gate 4013 design,(well, lots of RAM) I suggested to Xilinx that it would be real easy to build a utility that would give approximate energy per netlist node transition info (in picojoules) from the xnf netlist and speed file and an added power file?. Xdelay could do this (I claim). From this, one could manually estimate the power from the node transition frequencies. Or wait a year or two for the affordable simulation people to realize that power dissipation is a hot feature and provide hooks to get power info, if it was available in some standard form. I also pointed out that the need will get worse with higher speed, density, utilization etc. So far, no sign of progress, but ultimately customer pressure will prevail. I don't think that leaving it totally up to the customer to go through the guts of the design and figure out the buffers, shortlines, longlines etc. and relate them back to the netlist and the expected stimulus will cut it anymore. I mean, WHO can DO this? It will be TOO easy to make a dense, fast design that just burns too much power. If you don't have the tools, you are stumbling in the dark. Anyway, I would suggest that Xilinx take this issue more seriously and that Peter have a delightful weekend. regards, tom burgessArticle: 5239
Ilan Ron wrote: > > Hi there ! > We're currently assessing our choice of neat generation FPGA family. > One of the major subjects that's been hard to estimate was power > dissipation, especially within the XILINX and ORCA devices. > > So, I call upon any of you , who has some actual experience with those > devices (mainly in the neighborhood of 20k to 40k gates at clock rates > of 40-60MHz)to share their power dissipation results. > > Further more -any contributing insight about actual > disappointment/appreciation of these devices is welcomed. > > Best regards, > Ilan Ron (intended as a reply to Peter's reply, but my news server is insane) Peter Alfke wrote:> > The Xilinx 1996 Data Book lists the power consumption ov various > ingredients as mW/ MHz or mW/million transitions per second ( not the > same thing! ). > It is up to the user to estimate the internal activity.<deleted> > > Peter Alfke, Xilinx Applications About a year ago after experiencing burned fingers from a maxed out (2.5W@32 MHz) 30,000 gate 4013 design,(well, lots of busy RAM) I suggested to Xilinx that it would be real easy to build a utility that would give approximate energy per netlist node transition info (in picojoules) from the xnf netlist and speed file and an added "power" (R, C, V) file? Xdelay could do this (I claim). From this, one could manually estimate the power from the node transition frequencies. Or wait a year or more for the affordable simulation people to realize that power dissipation is a hot feature and provide hooks to get power info, if it was available in some standard form. I also pointed out that the need will get worse with higher speed, density, utilization etc. So far, no sign of progress, but ultimately customer pressure will prevail. I don't think that leaving it totally up to the customer to go through the guts of the design and figure out the buffers, shortlines, longlines etc. and relate them back to the netlist and the expected stimulus will cut it anymore. I mean, WHO can DO this? It will be TOO easy to make a dense, fast design that just burns too much power. If you don't have the data, you are stumbling in the dark. I might also suggest a PPR min_power option that avoids skew on combinatorial inputs to minimize power consuming output glitches. Doubtless a nightmare to implement. Anyway, I would suggest that Xilinx take this issue more seriously. I think that the customer benefits v.s. effort ratio is high in this case. regards, tom burgessArticle: 5240
Perhaps this whole business illustrates how some FPGA vendors are dependent on someone else's silicon foundry. We all know that many/most FPGAs (including Xilinx) are made by Sharp, Seiko/Epson, etc but I am sure few people realised that if one of these foundries decide to drop something, you can say bye bye to your FPGAs. Somehow I cannot believe that Xilinx in particular would rely on such an arrangement, however. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5241
Ed, Check http://www.erols.com/aaps There is a kit there which could make your life easier! Richard Ed Vogel <epv@pcsi.cirrus.com> wrote in article <32F0F9D3.18E2@pcsi.cirrus.com>... > I am considering the design of a dynamically reconfigurable logic > platform. It is more in line with tinkering than a serious product > application. Has anyone else tried to build an in circuit programmable > interface inside an FPGA or CPLD? > > I realize that Lattice offers something of this sort(pseudo JTAG port) > but I want to go one step further; to make connections between "user > defined" muxes surrounding "user defined" logic blocks. In short I want > to waste the resources provided for me by the chip manufacturer and third > party tool designers to functionally design and program an FPGA or CPLD > in favor of using those resources to build a "scaffolding" inside to > facilitate the construction of dynamically reconfigurable logic. I > realize this is wasteful. I want control over routing delays and > repeatability without consulting a third party. It also would allow > greater flexibility in interfacing to C compiler outputs. Just curious. . > . >Article: 5242
Synopsis is great, but still a bit steep in the pricing for a kit. If you want a good all around XILINX package with VHDL,Schematic capture, Post route simulation, VHDL on line multi media tutorial, ABEL HDL, with PC ISA FPGA Test board which also works stand alone, XILINX download cables and with FPGA, --software works with gate counts to 20,000 all for $2800.00 !!! Plus lower prices if you are willing to limit your chip capabilities or not use VHDL! see http://www.erols.com/aaps Steven K. Knapp <optmagic@ix.netcom.com> wrote in article <01bc0ede$d1b8a980$68e31fcc@#optmagic>... > > > Tim Hubberstey <tim_hubberstey@mindlink.bc.ca> wrote in article > <tim_hubberstey.95.32F030CF@mindlink.bc.ca>... > > I recommend that you look at the Synopsys FPGA compiler for the PC (I > can't > > remember the exact name). We do our design work in VHDL and until > recently had > > been using Viewlogic but we found it to be such a pain to work with (both > > > Windows and Unix versions!) that we dumped it completely and switched (at > > > great expense) to Synopsys. Our gate counts immediately dropped by at > least > > 30% and the timing improved by a similar margin. > > > The PC equivalent of the Synopsys FPGA compiler is called FPGA Express. > You can find out more information at: > > http://www.synopsys.com/products/fpga_pc/fpga_pc.html > > Synopsys is quite liberal with demo CD-ROMs and it's definitely worth a > look. For us non-university folks, it about $13,000 list price with one > language supported and one device optimizer. > -- > Steven Knapp > E-mail: optmagic@ix.netcom.com > Programmable Logic Jump Station: http://www.netcom.com/~optmagic >Article: 5243
If you want a good all around XILINX package with VHDL,Schematic capture, Post route simulation, VHDL on line multi media tutorial, ABEL HDL, with PC ISA FPGA Test board which also works stand alone, XILINX download cables and with FPGA, --software works with gate counts to 20,000 all for $2800.00 !!! Plus lower prices if you are willing to limit your chip capabilities or not use VHDL! see http://www.erols.com/aaps Andreas Doering <doering@iti.mu-luebeck.de> wrote in article <32F03F36.2D72@iti.mu-luebeck.de>... > Stuart Clubb wrote: > > > > Using your 2/3 rule, Why not try Lucent OR2C15A. They've been shipping > > since February 1996, they're in 0.35-micron. They might even be lower > > cost than the above two. > > > Because the cost of the development software is > very high. At least last time I asked, it was said to be 10K $. > You can buy a lot of 10K100 for that. > Andreas >Article: 5244
Muzok, I have used both Altera and XILINX and AT&T FPGAs. The Altera FPGAs do not have internal tristates. The XILINX and AT&T do. The XILINX chips don count the tristates in their logic count, so they are essentially free. One problem I will caution you on is that the TRISTATE equations in an HDL language might not be directly migratable to an ASIC platform. This can be worked around, and I have used the tristates in XILINX chips with great success. I have used EXEMPLAR GALILEO and it works well. I also have access to Synplicity and it does well. I work in VHDL which I found to be quick to learn. Also if you want a good all around XILINX package with VHDL,Schematic capture, Post route simulation, VHDL on line multi media tutorial, ABEL HDL, with PC ISA FPGA Test board which also works stand alone, XILINX download cables and with FPGA, --software works with gate counts to 20,000 all for $2800.00 !!! Plus lower prices if you are willing to limit your chip capabilities or not use VHDL! see http://www.erols.com/aaps muzok <muzok@pacbell.net> wrote in article <32ee0c92.228340855@SantaClara01.news.internex.net>... > hi, > I have a small controller which has an internal tristate bus. The design is in > Verilog. Which FPGAs support synthesis of such a design ? I am considering Altera > Flex10K family. Does it have internal them? Also which synthesis tool do you > suggest? I am considering Exemplar Galileo or Synplicity. Any preferences ? > > thanks > > muzo > > NT Kernel Driver Development Consulting > Please reply to muzok@pacbell.net >Article: 5245
>>>>>>> SPAM DELETED BY ARCHIVE OWNER (better late than never)Article: 5246
jim granville <Jim.Granville@xtra.co.nz> writes: >Aage Farstad wrote: >> >> Hi all, >> >> Can anybody give me a hint of what's wrong with my newsreader? Every >> time I try to open a message from this guy, my newsreader (netscape3.0) >> says: No Such article, Perhaps the article has expired! He is the only >> one treated this way! >> >> Best Regards Aage Farstad >> >> aage.farstad@ffi.no > >Mine too, >Seems Mr Knapp has the ULTIMATE in security - WRITE ONLY MEMORY :-) ]From: "Steven K. Knapp" <optmagic@ix.netcom.com> ]Subject: Re: Safety Critical Apps -> Xilinx Checker. ]Newsgroups: comp.arch.fpga,comp.lsi,comp.lsi.testing,sci.electronics,comp.arch ]Date: 29 Jan 1997 16:51:50 GMT ]Organization: Netcom ]Message-ID: <01bc0e04$36b4ae00$f181b6c7@#optmagic> Mal-formed Message-ID. I'd be surprized if that is causing netscape to barf, though. ]X-Newsreader: Microsoft Internet News 4.70.1155 Uh huh. -- Frank Cringle, fdc@cliwe.ping.de voice: (+49 2304) 467101; fax: 943357Article: 5247
I am currently using products from Aries, for both the WW socket and a ZIF that plugs into it. For the WW socket, their partnumber would be (I think) 224-PGM-18-18005-20 or -21 or -30 or -31. -2x is two level wrap, -3x is three level wrap. -x0 is Gold collet, tin shell, -x1 is Gold collet, gold shell. You can order these products through CalSwitch 1-800-225-7924 The -31 parts will be around $50 each in small qty. A suitable ZIF socket is probably 361-PRS-19-001-1-0 which is a 19 by 19 array, and will require some modification to match up the WW socket. Check with CalSwitch. Expect it to cost about $80. Philip In article <32F2441F.3A7E@prism.gatech.edu> Scott McIntosh <gtd750a@prism.gatech.edu> writes: >Hello, > I'm using a Xilinx 4013E PG223 chip and currently the rest >of the hardware is to be mounted with wire wrap sockets. Problem >so far is I'm unable to find an 18x18,223 wire wrap socket. Are >these just not available? Any other suggestions? > >Thanks, > Scott McIntosh > gtd750a@prism.gatech.eduArticle: 5248
This is just a test. I updated my news package in the hopes that this will fix the 'No such article' problem. -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5249
In article <32f51952.49206535@news.alt.net> zx80@dgiserve.com (Peter) writes: > >Perhaps this whole business illustrates how some FPGA vendors are >dependent on someone else's silicon foundry. > >We all know that many/most FPGAs (including Xilinx) are made by Sharp, >Seiko/Epson, etc but I am sure few people realised that if one of >these foundries decide to drop something, you can say bye bye to your >FPGAs. > >Somehow I cannot believe that Xilinx in particular would rely on such >an arrangement, however. >Peter. Xilinx AND Altera normally are not as exposed as this little episode has demonstrated, because they run their products in multiple fabs with multiple foundary partners. What this episode demonstrates is the problem of using non mainstream process technology. I would guess that the situation is far worse for AntiFuse FPGA vendors, since the technology is far from mainstream, and it is unlikely that multiple foundaries can be supported with the process modifications needed to support the fuses, and that the independent fabs will run it the same way. Philip Freidin
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z