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Job: HW Project Leaders/Managers - FPGA/ASIC/PCI/VME ------------------------------------------------------ Small privately held company building high performance multi-processor systems seeks individual to lead hardware development team. If you have a background in FPGA's, ASIC's, VME, PCI, multi-processor or real-time systems as a designer and project leader or manager and are looking to make a step up, this opportunity might be right for you. Company is located in the Boston area ( 495 belt ), is a fulltime position reporting to V.P. of Engineering, offers top pay, full benefits and potential for equity. For more information please email resume or brief summary of background to lwatts@world.std.com All replys will receive a rapid response and be kept in confidence.Article: 5151
David Hobarth wrote: > > Anyone have any ideas on how to "manually" configure an FPGA outside > of a development environment such as orcad/viewlogic/etc.? I already > talked to Xilinx and they won't release that kind of data for their > 4xxxEX series (or for the 3xxx or 4xxx series, for that matter), and > the 6200 series they recommended has no such data in the data sheet as > I was told. I understand their position on security, but that doesn't > get me anywhere. Any solutions? Look at the http://www.xilinx.com/partinfo/db96.htm#FPGA for the data sheet on the xc6200. All the programming info is there. If you want to program at the bit level only the 6200 is safe. In fact you can even load random bit files into the 6200 as in Adriane Thompson's genetic algorithm research using a XC6216. Steve Casselman Virtual Computer Corp.Article: 5152
> Steve - > It's obvious that the XC6000 wins the reconfiguration part of the > performance equation, but how about the computing side? It has been > some months since I looked for info on the relative performance > of, say, a 16-bit adder or counter implemented in a XC4000 vs. XC6000 > device. Since you are now in a position of having worked with both, > do you have any numbers? > The first XC6200s come in a -2 speed grade. There is also a one nanosecond direct delay between neighbors. So for a ripple carry adder the delay would be 3ns per adder bit which puts a 16 bit adder at ~20MHz. If you care to use more logic you can make a pipelined adder at flip-flop toggle rate (i think ~175MHz-200MHz). It takes three cells to make a full adder. So in a 6216 there are 4K (4096) cells. So I can make a 1365 bit adder. This would take 682 X4000 CLBs or around a 26x26 (4020) 4000 series. I can pipeline ripple carry with 4 cells per bit which would give me a part with the arithmetic density of a 22x22 4000 series FPGA. If you look at Adriane Thompson's genetic algorithm research using a XC6216 you will see that there is more to the XC6200 than just another FPGA as I said before the XC6200 needs a new name and we think it is Reconfigurable Processor Unit (RPU). Since Xilinx XC6216 reference design is the first standard platform for reconfigurable computing we think that it is like the IBM PC of reconfigurable computing. The part is open, the board is open and low cost. The board comes with free VHDL and XACT-Step 6000 as well as some public domain software. We all believe that the FPGA sits between the ASIC and the microprocessor. Well I like to put the 6200 between the FPGA and the microprocessor (very close to the FPGA but with more versatility). Steve CasselmanArticle: 5153
hi, I have a small controller which has an internal tristate bus. The design is in Verilog. Which FPGAs support synthesis of such a design ? I am considering Altera Flex10K family. Does it have internal them? Also which synthesis tool do you suggest? I am considering Exemplar Galileo or Synplicity. Any preferences ? thanks muzo NT Kernel Driver Development Consulting Please reply to muzok@pacbell.netArticle: 5154
Donald Gillies <gillies@cs.ubc.ca> wrote: >ees1ht@ee.surrey.ac.uk (Hans Tiggeler) writes: >>Given the price of S/DRAM memories why not use a majority voting >>system such as TMR (Triple Modular Redundancy). The system can handle >>multiple bit upsets and is very easy to implement. I have currently a >>system running in an Actel1020 (17% used!). Of course the drawback is >>that you have to either triplicate your memory or add a statemachine >>to perform three memory read cycles per CPU read cycle. > >I would suspect that the answer is: power. Very few spacecraft have >power to burn on triplicated anything, if it can be avoided. Triplicated RAM won't eat more than a few watts, though, and the simplicity of operation of not having to scrub memory nearly as often would be immensely useful. I would guess that we'll see someone fly something along the lines of triplicated voting RAM on a smallsat as an experiment first, but I wouldn't be suprised to see it fly on commercial birds sometime soon either. -george william herbert Retro Aerospace gherbert@crl.comArticle: 5155
Steve Wiseman (steve@sj.co.uk) wrote:
: I actually got to speak to a Xilinx chap, they were, without exception
: competent and helpful. More of a problem were the problems with the
: Viewlogic software bundled with the Xilinx tools. This was obviously
: well behind what Viewlogic were shipping to 'real' customers, with no
: clear path for tech support. Bug-free is not a term I would use. I've
: now defected to Altera, where I'm happy. The tools work, there's one
: phone number for tech support, and no passing the buck. I like that. (I
: also get about 2-3 times as much VHDL-generated FPGA per £GBP, which
: seems to make my customers happy, too)
: Message to tool-builders.
: If your documentation / manuals are wrong / inadequate then your
: customers _will_ require tech support. If that is not available, your
: customers will rant.
Here is my experience:
1) Xilinx vs Altera support: I work mostly with Xilinx and usually get
response from them the same day or, sometimes, next day. If I send email
to Xilinx support they usually respond by email within 3-4 days or less.
Similar email request to Altera was answered in 10 days. However, I think
that they are basically equivalent if you are talking about support over
the long term and not separate cases.
2) *THE BIG DIFFERENCE* : real-life example from the last month.
Altera just discontinued their FLASHlogic family and gave its customers
6 months to decide on orders and quantities and then 1 more year for
shipments. NOBODY KNEW IT WAS COMING !!!!!. Quite a surprise that will
cost our company a lot of money.
Xilinx discontinued their 2000 Series FPGA in the following way:
a) for quite some time (about a year) it was not recommended for new designs
b) the customers have time till January 1999 to make orders and till July
1999 for the last delivery.
This is the proper way to do it.
3) ViewLogic DOS : as close to bug-free as any other tool, nicely integrated
schematic editor/simulator, good support for Xilinx (e.g. attribute mechanism
for schematic). Decent documentation
ViewLogic PROseries (Windows 3.1) : same schematic editor, some nice tools
for integration with VHDL, the VHDL part of the system (especially synthe-
sizer) is *extremely* buggy. It took me a month of talking to customer sup-
port and looking for workarounds (the second sometimes faster) to generate
a netlist for XC4004A. Terrible documentation (luckily I have the old DOS
stuff). Non-standart VHDL (the famous VLBIT stuff) etc., etc.
I already got the new WorkView Office for Win95 but I am afraid that lear-
ning the new '95 bugs will take more time that dealing with the old bad
Win3.1.
George.
NOHAU Corporation.
Campbell, CA.
Article: 5156Ron G. Minnich <rminnich@sarnoff.com> wrote in article > Do the Altera interfaces now do PCI Master mode? they did not a year ago. > In fact they were not enough of a pci interface to be that useful -- we had to > do our own. If you're not tied to Altera, Xilinx also offers a PCI interface that does support master mode. It's part of their System-Level Integration (SLI) products. There's information available at: http://www.xilinx.com/products/logicore/lounge/pcim/pcim.htm There's also PCI design consulting help available from HighGate Design (highgate@highgatedesign.com) and from Darkroom Technologies (darkroom@ix.netcom.com). -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5157
Back in the mid-1980s, there was a small bipolar IC house called Bipolar Integrated Technology (or BIT). They specialised in high-speed arithmetic devices. One of their devices was a 64-bit IEEE (and integer) multiply/divide/square root chip. The divide algorithm is a Robertson non-restoring radix-4 (2 bits per micro-cycle) structure which will also perform square root operations with a modest amount of added logic. I was the primary architect of the BIT FP devices, which was my 15 minutes of fame (in a *very* small circle of friends!). You can check out the divide algorithm in K. Hwang's "Computer Arithmetic" book, a reference book for anyone building high-speed arithmetic implementations. Publisher is John Wiley & Sons. The square root algorithm is based on a paper published by Greg Taylor (there are lots of Greg Taylors running around, make sure you've found the right one) in the early 80s. The square root was a non-restoring 1-bit per cycle algorithm. I forget the details, so please don't ask me for any... I believe Greg Taylor was, at the time, working at Sun Microsystems. In article <32ECDBF1.59E2@vnet.ibm.com>, jparedes@vnet.ibm.com says... > There's a neat way I seem to remember that didn't use multiplication, > but sort of imbedded the multiplication in a bunch of shift-adds (okay > well, that's what mutiplication is anyway..). You can make it pretty > fast by using a sort of modified CLA scheme. I have to look it up if you > like. You set up a Divide Array, similar to a Multiply array and it > performs pretty good. Wow, it's been a long time since I've seen that > stuff, now I really want to look it up... :) Anyway, let me know if you > would like the algorith/hardware layout. > > Jose -- **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 5158
The Xilinx XC4000E/EX family supports internal tri-state busses. There is more information on the XC4000E/EX family at: http://www.xilinx.com/products/fpgaspec.htm#XC4000 The way that you code the design has a direct impact on how the design is implemented. If you code it one way, you'll get muxes instead of busses. I'd recommend downloading the HDL Design Guide for FPGAs at: http://www.xilinx.com/appnotes/hdl_dg.pdf It's an Acrobat document is around 2 Mb but it has lots of useful information. I haven't used Synplicity (http://www.synplicity.com/) before but Exemplar package is quite good (http://www.exemplar.com/). muzok <muzok@pacbell.net> wrote in article <32ee0c92.228340855@SantaClara01.news.internex.net>... > hi, > I have a small controller which has an internal tristate bus. The design is in > Verilog. Which FPGAs support synthesis of such a design ? I am considering Altera > Flex10K family. Does it have internal them? Also which synthesis tool do you > suggest? I am considering Exemplar Galileo or Synplicity. Any preferences ? > > NT Kernel Driver Development Consulting > Please reply to muzok@pacbell.net >Article: 5159
For completeness, I'll also include the Altera FLEX10K (http://www.altera.com/html/products/f10k.html) but the HTML data sheet states "Tri-state emulation that implements internal tri-state nets," whatever that implies. Also Lucent's ORCA devices (http://www.lucent.com/micro/fpga/docs.html#datasheet) also support internal tri-state. -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Steven K. Knapp <optmagic@ix.netcom.com> wrote in article <01bc0cb5$fdeccde0$63e31fcc@#optmagic>... > The Xilinx XC4000E/EX family supports internal tri-state busses. There is > more information on the XC4000E/EX family at: > > http://www.xilinx.com/products/fpgaspec.htm#XC4000 > muzok <muzok@pacbell.net> wrote in article > <32ee0c92.228340855@SantaClara01.news.internex.net>... > > hi, > > I have a small controller which has an internal tristate bus. The design > is in > > Verilog. Which FPGAs support synthesis of such a design ? I am > considering Altera > > Flex10K family. Does it have internal them? Also which synthesis tool do > you > > suggest? I am considering Exemplar Galileo or Synplicity. Any preferencesArticle: 5160
George Herbert wrote: > > Donald Gillies <gillies@cs.ubc.ca> wrote: > >ees1ht@ee.surrey.ac.uk (Hans Tiggeler) writes: > >>Given the price of S/DRAM memories why not use a majority voting > >>system such as TMR (Triple Modular Redundancy). The system can handle > >>multiple bit upsets and is very easy to implement. I have currently a > >>system running in an Actel1020 (17% used!). Of course the drawback is > >>that you have to either triplicate your memory or add a statemachine > >>to perform three memory read cycles per CPU read cycle. > > > >I would suspect that the answer is: power. Very few spacecraft have > >power to burn on triplicated anything, if it can be avoided. > > Triplicated RAM won't eat more than a few watts, though, > and the simplicity of operation of not having to scrub memory > nearly as often would be immensely useful. > **** First, I think a lot of systems would like to save the few watts. But **** space would be perhaps a more valuable commodity. Many of the new **** spacecraft are eliminating redundancy and going single string - putting **** in TMR would be extremely difficult to do for memory, for the majority **** of unmanned applications. For flip-flops inside gate arrays or FPGA's **** where gates are relatively cheap, TMR is more frequently implemented **** in the systems I've seen since the voter is cheap. But many systems **** don't want pay for that; that's why there's such a strong interest **** in a rad-hard fpga. But for memories, if you go to the trouble to **** put in all of the chips for tmr, you could, assuming a 16-bit reference **** system and x8 memory chips, use a SEC/DED Hamming code and double the **** amount of usual memory, and get a more powerful code because of the **** larger Hamming distance. Trading off the same amount of user memory **** for Hamming code protected memory and TMR protected memory, you would **** have to scrub more often for TMR protected memory since there are **** twice as many bits, doubling the system's cross-section. Fortunately, **** even for relatively soft, large memories, it turns out that the scrub **** rate needed for good seu-reliability is not very high. **** **** the best bang for the buck i've seen flown is with some of the more **** sophisticated codes like Reed-Solomon which has excellent correcting **** power for multiple bit errors with a very small overhead. But these **** apps are mostly for bulk store. > I would guess that we'll see someone fly something along the lines > of triplicated voting RAM on a smallsat as an experiment first, > but I wouldn't be suprised to see it fly on commercial birds > sometime soon either. **** any specifics? i've been seeing lots of EDAC and Reed-Solomon and **** some Golay codes but haven't seen any proposals for TMR memory **** other than inside gate arrays in a long time. > > -george william herbert > Retro Aerospace > gherbert@crl.com **** an interesting point about TMR vs. single string is the result that **** by some measures the TMR system actually has less reliability. For **** instance, assuming a perfect voter, the TMR reduces the MTTF over **** the single string system by about 16%. The TMR system has a higher **** reliability for short missions but for long missions, there is a **** cross over point, based on the failure rate of the element, where **** simplex systems have a better reliability. It turns out that after **** the first failure in a TMR system, the failed component and one of **** the working components should both be 'discarded' to improve **** reliability. **** rkArticle: 5161
Peter, > Perhaps you are using the DOS versions of Viewlogic. No, I'm using Workview Office 7.2 under NT 4.0 WS. It's excellent! AustinArticle: 5162
In article <32E898E4.7B5B@ingsun1.univ.trieste.it>, Vanni FADONE <fadone@ingsun1.univ.trieste.it> wrote: >I'm gathering some material about implementing division with FPGAs; in >particular I'd like to use Xilinx XC40xx. >Can anybody help me? >I know there is an article regarding it on the "Journal of VLSI Signal >Processing" (v 7 n 3 May 1994 p 271-285), but I can't find it. The >authors of that article are M.E.Louie and M.D.Ercegovac (UCLA). > >If you think you've something of interesting for me, please e-mail it to >me. >I would appreciate any help you may be able to provide. >Thanks in advance. CORDIC is used in VLSI implementations. With it you can do division as well as sqrt and trig functions using shift/add. Ray Andraka has a paper on doing a vector magnitude processor using CORDIC and bit serial processing in FPGA. http://www.ids.net/~randraka/pages/papers.htm See ya, -ingo -- /* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */Article: 5163
Hi there !
We're currently assessing our choice of neat generation FPGA family.
One of the major subjects that's been hard to estimate was power
dissipation, especially within the XILINX and ORCA devices.
So, I call upon any of you , who has some actual experience with those
devices (mainly in the neighborhood of 20k to 40k gates at clock rates
of 40-60MHz)to share their power dissipation results.
Further more -any contributing insight about actual
disappointment/appreciation of these devices is welcomed.
Best regards,
Ilan Ron
Article: 5164
ANNOUNCEMENT
Bournemouth University Page of
Dynamically Reconfigurable Hardware
at
http://dec.bournemouth.ac.uk/dec_ind/decind6/drhw_page.html
is now available !
The page aims to provide links to various subjects related to
Dynamically Reconfigurable FPGAs.
The Contents:
Terminology
Dynamically Reconfigurable Devices and Technology
Applications
Reconfigurable Computing
Evolvable Hardware and Embryonics
Synthesis for Dynamically Reconfigurable Logic
Other FPGA links
Please let me know your comments and suggestions for improvements.
Thank you.
Milan Vasilko
=====
Milan Vasilko (Mr.)
mvasilko@bournemouth.ac.uk
-
Dept of Electronics
Bournemouth University
Talbot Campus, Fern Barrow
Poole, Dorset BH12 5BB
UNITED KINGDOM
-
tel: +44-(0)1202-595 560
fax: +44-(0)1202-595 314
=====
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 5165In article <5cj5kl$c7b@borg.svpal.org>, garyk@svpal.svpal.org (George Noten) wrote: >Steve Wiseman (steve@sj.co.uk) wrote: >: I actually got to speak to a Xilinx chap, they were, without exception >: competent and helpful. More of a problem were the problems with the >: Viewlogic software bundled with the Xilinx tools. This was obviously >: well behind what Viewlogic were shipping to 'real' customers, with no >: clear path for tech support. Bug-free is not a term I would use. I've >: now defected to Altera, where I'm happy. The tools work, there's one >: phone number for tech support, and no passing the buck. I like that. (I >: also get about 2-3 times as much VHDL-generated FPGA per £GBP, which >: seems to make my customers happy, too) > >: Message to tool-builders. >: If your documentation / manuals are wrong / inadequate then your >: customers _will_ require tech support. If that is not available, your >: customers will rant. > >Here is my experience: >1) Xilinx vs Altera support: I work mostly with Xilinx and usually get >response from them the same day or, sometimes, next day. If I send email >to Xilinx support they usually respond by email within 3-4 days or less. >Similar email request to Altera was answered in 10 days. However, I think >that they are basically equivalent if you are talking about support over >the long term and not separate cases. Pretty weird to email, since you can call and someone will answer the phone. >2) *THE BIG DIFFERENCE* : real-life example from the last month. >Altera just discontinued their FLASHlogic family and gave its customers >6 months to decide on orders and quantities and then 1 more year for >shipments. NOBODY KNEW IT WAS COMING !!!!!. Quite a surprise that will >cost our company a lot of money. Neither did Altera. Sharp gave a last time buy notice on wafers for FlashLogic. As you know, it's a rather complex process (being both FLASH and SRAM) and no one else seems interested in making the wafers at the volumes they sell at. As for Xilinx, they came to my design group two years ago saying that anti-fuse is the future; they already dumped it. >Xilinx discontinued their 2000 Series FPGA in the following way: > a) for quite some time (about a year) it was not recommended for new designs > b) the customers have time till January 1999 to make orders and till July > 1999 for the last delivery. >This is the proper way to do it. It is if it is under your control. Altera still ships devices from the mid-1980s because there is demand due to existing product. The normal method for obseleting a device is much as you've stated. This one wasn't up to them. >3) ViewLogic DOS : as close to bug-free as any other tool, nicely integrated >schematic editor/simulator, good support for Xilinx (e.g. attribute mechanism >for schematic). Decent documentation Kind of disagrees with the previous poster. What other tools have you tried? >ViewLogic PROseries (Windows 3.1) : same schematic editor, some nice tools >for integration with VHDL, the VHDL part of the system (especially synthe- >sizer) is *extremely* buggy. It took me a month of talking to customer sup- >port and looking for workarounds (the second sometimes faster) to generate >a netlist for XC4004A. Terrible documentation (luckily I have the old DOS >stuff). Non-standart VHDL (the famous VLBIT stuff) etc., etc. >I already got the new WorkView Office for Win95 but I am afraid that lear- >ning the new '95 bugs will take more time that dealing with the old bad >Win3.1. I don't envy you there ;) WayneArticle: 5166
In article <01bc0cb9$c2188080$63e31fcc@#optmagic>, "Steven K. Knapp" <optmagic@ix.netcom.com> wrote: >For completeness, I'll also include the Altera FLEX10K >(http://www.altera.com/html/products/f10k.html) but the HTML data sheet >states "Tri-state emulation that implements internal tri-state nets," >whatever that implies. Also Lucent's ORCA devices >(http://www.lucent.com/micro/fpga/docs.html#datasheet) also support >internal tri-state. Altera implements them as a mux. BTW, you have an excellent web site. WayneArticle: 5167
Xilinx 3k and 4k both have internal tri-state busses. They can also be split in the middle so you can double the number of tri-state lines in the chip if you need to. I have done chips that I put half the bits on the left side, and half the bits on the right so I could use a smaller/cheaper chip, and get a 32 bit bus in a 4005! Worked great! By the way, the internal tri-state busses in the Xilinx parts are not taken into consideration when they give a 'gate count'. These are basically free logic (if you are going by gate counts that is...). They are quite fast too. Austin Franklin ..darkroom@ix.netcom.com.Article: 5168
You might check with AMD and see if their latest version of PALASM handles that device. They convert JEDEC files back into PALASM source language.Article: 5169
The Xilinx 1996 Data Book lists the power consumption ov various ingredients as mW/ MHz or mW/million transitions per second ( not the same thing! ). It is up to the user to estimate the internal activity. There is an Altera app note that estimates power by relating everything to a 16-bit counter. That is easy but can be misleading: In a binary counter, half the total power is obviously dissipated in the first flip flop, the other half in the sum of all the other flip-flops. So, if your application is a binary counter, a 10 MHz clock results in max 5 million transitions per second in the first flip flop, and equally as much in all the rest, for a total of 10 million flip-flop transitions per second spread over 16 flip-flops. That is the same as if one eighth ( 12.5% ) of the flip-flops were toggling on every rising clock edge. 12.5% of all flip-flops toggling is true for 16-bit counters, but says little about other types of logic. In heavily pipelined DSP applications the percentage will be higher, in random control appications, the percentage will be lower. Obviously, 3.3 V logic reduces power by 56% compared to 5 V ( using nominal voltage values ) Commercial-grade Xilinx FPGAs are tested and guaranteed at 85 degrees C junction temperature. Specifying CMOS programmable devices - with unknown clock rates and thus unknown power dissipation - at a given ambient temperature is irresponsible ( deceiving or stupid are more appropriate words ), but you can still read that kind of nonsense in the product literature. At higher temperatures ( up to 125 degr. junction ), the user must consider the fact that delays increase 0.35 percent per degree C. Manufacturers usually give extensive data on junction-to-case thermal resistance for various levels of airflow. ( Page 10-8 in the Xilinx Data Book ). Peter Alfke, Xilin ApplicationsArticle: 5170
On 27 Jan 1997, George Herbert wrote: > Donald Gillies <gillies@cs.ubc.ca> wrote: > >ees1ht@ee.surrey.ac.uk (Hans Tiggeler) writes: > >>Given the price of S/DRAM memories why not use a majority voting > >>system such as TMR (Triple Modular Redundancy). The system can handle > >>multiple bit upsets and is very easy to implement. I have currently a > >>system running in an Actel1020 (17% used!). Of course the drawback is > >>that you have to either triplicate your memory or add a statemachine > >>to perform three memory read cycles per CPU read cycle. > > > >I would suspect that the answer is: power. Very few spacecraft have > >power to burn on triplicated anything, if it can be avoided. > > Triplicated RAM won't eat more than a few watts, though, > and the simplicity of operation of not having to scrub memory > nearly as often would be immensely useful. > > I would guess that we'll see someone fly something along the lines > of triplicated voting RAM on a smallsat as an experiment first, > but I wouldn't be suprised to see it fly on commercial birds > sometime soon either. > > > -george william herbert > Retro Aerospace > gherbert@crl.com > > > It seems to me that to fail operational, you need FOUR rams. The assumption is that the rams do not have a parity bit and so a parity error is not noted on a read access. After one fails in a 3way vote, there are only two left and the system can only detect an error. Therefore, starting with four and losing one (assuming a single point failure), you still have three left and enough to still fail operational. And the system still needs to fix the data that is bad. It seems simpler in terms of hardware (and thus more reliable since fewer things can go wrong) to encode error correction in the data in the ram even if it complicates the software. ######################################################################## Alvin E. Toda aet@lava.net sr. engineer Phone: 1-808-455-1331 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html 1363-A Hoowali St. Pearl City, Hawaii, USAArticle: 5171
NEWLY RELEASED APPLICATION NOTE We are pleased to announce that our new application note, 'Device Control via the PC' is finally available. This application note covers such topics as PC control of lamps and motors using solid state and mechanical relays, device control using both BJT and power MOSFET transistors, stepper motor control using a transistor array IC, as well as PWM motor control using the L293 H-Bridge. Connection to the PC is made via our inexpensive EDE300 PC Interface IC. Code examples are also provided. Feel free to download a copy today; it is available at http://www.netins.net/showcase/elab in the 'Integrated Circuits' section under 'EDE300'. Todd Peterson E-Lab Digital Engineering, Inc. P.S. - While you're there, visit our Electronics Resource Directory, a freely useable directory containing over 500 categorized hot-links of value to the electronics community.Article: 5172
I am looking for people with knowledge of scientific and medical imaging. Specifically I am interested in your opinion on the future applications for fibre channel to scientific and medical imaging. Also, do you see any application to the VME market. Any referrals to experts in this area are greatly appreciated. Thanks, Lisa Solomon LSRsearch@aol.comArticle: 5173
In article <32EE7BAC.6635@xilinx.com>, peter@xilinx.com wrote: >The Xilinx 1996 Data Book lists the power consumption ov various >ingredients as mW/ MHz or mW/million transitions per second ( not the >same thing! ). True. >It is up to the user to estimate the internal activity. True. >There is an Altera app note that estimates power by relating everything >to a 16-bit counter. That is easy but can be misleading: Wrong. Which app note is that? The app note I use (AN 74) is a power analysis worksheet for each device family that lets you put in the pertinent values such as clock speed, number of LEs used, number of flops transitioning per average clock edge, etc. All of these together are needed to determine the internal power consumption of the device. One can then calculate the power consumption for the I/O (since this is based upon the load, and is also explained in AN 74) and get the total power consumption for the device. I see nothing about 16-bit counters in it. [...] WayneArticle: 5174
The latest version of Palasm is palasm 4.0 v1.5, and you can download if for free at http://www.amd.com. It should be able to do what you want.
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