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I wrote: >Nope, sorry, that might be justice, but it's not the law. :-) Only >trademarks can actually lapse if not actively used. Patents, copyrights, >and trade secrets remain in force... I'm told there's a partial exception to this: apparently it's now possible, with certain exceptions, to fight off a patent-infringement suit on the grounds that the patent owner either isn't moving to market the invention or is moving too slowly. On the other hand, lawsuits can be expensive even if you win... -- The operating systems of the 1950s will be out | Henry Spencer next year from Microsoft. -- Mark Weiser | henry@zoo.toronto.eduArticle: 7526
My design is use ORCA2c26 it is PLACE&ROUNT ok. It is work about 18Mhz But is Fail in 5v 0.8um 2Metal 1Poly ASIC. So I want to try use ORCA Library builtin delay To Simulation. How can I do ? Thank you.Article: 7527
aslic <aslic@tpts1.seed.net.tw> 次寫入到主題 <01bcc318$96082980$69c4af8b@leader>... > > How to get Viewsim of delay file for Orca Cell > like viewsim.var for postsim > > > My design is use ORCA2c26 it is PLACE&ROUNT ok. It is work about 18Mhz But is Fail in 5v 0.8um 2Metal 1Poly ASIC. So I want to try use ORCA Library builtin delay To Simulation. How can I do ? Thank you.Article: 7528
Hello, I have to make choose the right programmable logic device for my system design. Is there an home page where all the Xilinx,Altera,Lucent,...product are listed and roughly but ONESLTY compared ? (speed, cost, performance with finite states machines, arithmetic,... ..TOOLS !!!....) Thank you ______ __ / ____ \ / /_ Marco Cavadini Electronics Laboratory ETH-Zurich / /_/ _\_\/ / _\_ TEL: +41(0)1 6322749 mailto:cavadini@ife.ee.ethz.ch /___/\__._)_/\__._) FAX: +41(0)1 6321210 http://ife.ee.ethz.ch/~cavadiniArticle: 7529
Ingo Cyliax wrote: > In article <5vsf24$co$1@amdint2.amd.com>, > John Archambeault <johna@dvorak.amd.com> wrote: > ... > > I got around this by hooking up the LDC_ (Low During > Configuration) pin from the Xilinx FPGA to the EEPROM. Please, don't do that. It works under "normal" circumstances, but if your system ever aborts the configuration process, the SPROM is not being reset and will continue from the latest address location, which of course creates a garbage configuration. There is a warning about this on page 5-3 left column in the Xilinx Data Book. Use the active Low INIT output as an active Low RESET input to the SPROM ( any manufacturer's SPROM ). That keeps the SPROM reset right until the moment when it is needed. This is not a new trick. We have documented and recommended this for years, and it must have been designed in into millions of systems. Peter Alfke, Xilinx ApplicationsArticle: 7530
In article <5vsf24$co$1@amdint2.amd.com>, John Archambeault <johna@dvorak.amd.com> wrote: ... > I got around this by hooking up the LDC_ (Low During Configuration) pin >from the Xilinx FPGA to the EEPROM. However, I was curious (and I'm sure so is >Eric) if anyone knows how to program that single bit on the ATMEL part. ... > BTW: I also used the BP microsystems PROM burner. I use one of the BP 'universal' programmers to program AT17c128/256, and the reset polarity is a sub-menu off the device menu. It's aprox.in the same place as the "secure" sub-menu in PLD mode. At least in the latest version of bp.exe from their web-site (www.bpmicro.com). See ya, -ingo -- /* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */Article: 7531
Due to explosive growth in our FPGA product line, this Microelectronics group of a $23billion Communications company is seeking a very talented engineer for a MTS FPGA Field Applications Engineering position. Locations-Santa Clara, Ca. and Boston, Ma. Applicants should have at least 3 years exp in the design and development of integrated circuits, either FPGA or ASIC. Expertise in VHDL or Verilog HDL is required. BSEE or MSEE required. We are looking for a seasoned digital circuit designer with the interpersonal skills to perform the presentation and customer relationship roles. Duties include: Working with engineers to implement/optimize designs Presentations to engineers and managers Working with engineers to teach them tool flows Educating customers on methods and techniques Converting existing designs from competitors products to there FPGAs Providing feedback for future products, features, and tools Evaluting and prioritizing opportunities Providing detailed technical info/assistance FAE will be set up in a virtual office or will be located in leased executive/shared office facilities. Salary--$60-$90K base + 12 to 15% annual bonus and Field Sales Incentive Plan + Car Total packages have been over100k for the right person. THIS IS A VERY LUCRATIVE COMPENSATION PACKAGE FOR A TALENTED DESIGNER WHO IS READY TO "COME OUT FROM BEHIND THE DESK". THESE POSITIONS WON'T LAST LONG!!! -- Eddie Amara- Executive Recruiter SpencerSearch,Inc. "We Specialize in Recruiting Premier Talent for Exceptional Companies in the Semiconductor Industry" Home Page-http://www.spencersearch.com Voice 972-378-0280 Fax 972-378-0279 Email amaraju@onramp.net =====================================================================Article: 7532
Yes it is configured by instantiating a clock boost primitive in your design. Please note, this feature is currently available on the 10K100 (100K gates) part only. Bob Bauman Michael David Scott <qwerty@WPI.EDU> wrote in article <5vphp3$mhj$1@bigboote.WPI.EDU>... > I was reading the specs on the newm Altera devices. On of the items which > caught my eye was the internal PLL. Will this be configured by a high > level description language or via some switches in Maxplus II? > > If via HDL, would that make it harder to use other simulation tools in > conjuction with Maxplus 2? > > Mike Scott >Article: 7533
Eric Ryherd <"vauto@tiac.net"@tiac.net> wrote:
>Anyone have experience with these?
>We've been literally "Blowing" thru tubes of Xilinx 17256Ds with
>our XC40xx FPGA developments and are searching for a way to save
>a few bucks.
>
>What PROM burner is required to program them... I only have a Xilinx
>HW130 but would buy a new prom burner if the price is right...
Check out http://www.equinox-tech.com/micropro.htm It's a great
little gadget. It may be the same hrdware as the Atmel programmer as
the price is about the same and the Equinox one uses an Atmel FPGA.
Anyway, I have been using one to program AT89C52 and AT17C128 for over
a year with no problems.
You can define the reset polarity manually or let the software
recognise the target from the file.
Note that the software for it works with Windows 3.1, 3.11 or 95 but
not NT :-( There is a dos version which I expect is still available
but it's comms crap out on anything over a P166.
Happy blowing (and re-blowing :-) )
Julian
--
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk error: smartass.sig not found
Hardware development eng. August Systems Ltd
---------------------------------------------------------------------
Article: 7534The Programmable Logic Jump Station at 'http://www.optimagic.com' may have some of the information that you are looking for. In specific, look at the summary data at 'http://www.optimagic.com/summary.html' and the company information at 'http://www.optimagic.com/companies.html'. We don't have any side-by-side comparison data because not much exists. There is a page available from the PREP benchmarking group at 'http://www.prep.org/data.htm'. This was an attempt to do some comparisons. However: 1. Not all of the vendors and devices are represented. 2. The data is quite old (July 1995) Unfortunately, selecting a technology is somewhat of a religious argument. Some people love Xilinx and hate Altera. Others love Altera and will never touch Xilinx. Others tend to use multiple vendors and choose the best device for the job. "The right choice" depends a lot on your application. -- Steven Knapp OptiMagic, Inc. E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.com Marco Cavadini <cavadini@ife.ee.ethz.ch> wrote in article <34223BC8.3F52138@ife.ee.ethz.ch>... | Hello, I have to make choose the right programmable logic | device for my system design. Is there an home page | where all the Xilinx,Altera,Lucent,...product are listed and | roughly but ONESLTY compared ? | | (speed, cost, performance with finite states machines, arithmetic,... | ..TOOLS !!!....) | | Thank you | ______ __ | / ____ \ / /_ Marco Cavadini Electronics Laboratory ETH-Zurich | / /_/ _\_\/ / _\_ TEL: +41(0)1 6322749 mailto:cavadini@ife.ee.ethz.ch | /___/\__._)_/\__._) FAX: +41(0)1 6321210 http://ife.ee.ethz.ch/~cavadini |Article: 7535
Due to explosive growth in our FPGA product line, this Microelectronics group of a $23billion Communications company is seeking a very talented engineer for a MTS FPGA Field Applications Engineering position. Locations-Santa Clara, Ca. and Boston, Ma. Applicants should have at least 3 years exp in the design and development of integrated circuits, either FPGA or ASIC. Expertise in VHDL or Verilog HDL is required. BSEE or MSEE required. We are looking for a seasoned digital circuit designer with the interpersonal skills to perform the presentation and customer relationship roles. Duties include: Working with engineers to implement/optimize designs Presentations to engineers and managers Working with engineers to teach them tool flows Educating customers on methods and techniques Converting existing designs from competitors products to there FPGAs Providing feedback for future products, features, and tools Evaluting and prioritizing opportunities Providing detailed technical info/assistance FAE will be set up in a virtual office or will be located in leased executive/shared office facilities. Salary--$60-$90K base + 12 to 15% annual bonus and Field Sales Incentive Plan + Car Total packages have been over100k for the right person. THIS IS A VERY LUCRATIVE COMPENSATION PACKAGE FOR A TALENTED DESIGNER WHO IS READY TO "COME OUT FROM BEHIND THE DESK". THESE POSITIONS WON'T LAST LONG!!! -- Eddie Amara- Executive Recruiter SpencerSearch,Inc. "We Specialize in Recruiting Premier Talent for Exceptional Companies in the Semiconductor Industry" Home Page-http://www.spencersearch.com Voice 972-378-0280 Fax 972-378-0279 Email amaraju@onramp.net =====================================================================Article: 7536
Due to explosive growth in our FPGA product line, this Microelectronics group of a $23billion Communications company is seeking a very talented engineer for a MTS FPGA Field Applications Engineering position. Locations-Santa Clara, Ca. and Boston, Ma. Applicants should have at least 3 years exp in the design and development of integrated circuits, either FPGA or ASIC. Expertise in VHDL or Verilog HDL is required. BSEE or MSEE required. We are looking for a seasoned digital circuit designer with the interpersonal skills to perform the presentation and customer relationship roles. Duties include: Working with engineers to implement/optimize designs Presentations to engineers and managers Working with engineers to teach them tool flows Educating customers on methods and techniques Converting existing designs from competitors products to there FPGAs Providing feedback for future products, features, and tools Evaluting and prioritizing opportunities Providing detailed technical info/assistance FAE will be set up in a virtual office or will be located in leased executive/shared office facilities. Salary--$60-$90K base + 12 to 15% annual bonus and Field Sales Incentive Plan + Car Total packages have been over100k for the right person. THIS IS A VERY LUCRATIVE COMPENSATION PACKAGE FOR A TALENTED DESIGNER WHO IS READY TO "COME OUT FROM BEHIND THE DESK". THESE POSITIONS WON'T LAST LONG!!! -- Eddie Amara- Executive Recruiter SpencerSearch,Inc. "We Specialize in Recruiting Premier Talent for Exceptional Companies in the Semiconductor Industry" Home Page-http://www.spencersearch.com Voice 972-378-0280 Fax 972-378-0279 Email amaraju@onramp.net =====================================================================Article: 7537
On Fri, 19 Sep 1997 10:46:00 +0200, Marco Cavadini <cavadini@ife.ee.ethz.ch> wrote: >Hello, I have to make choose the right programmable logic >device for my system design. Is there an home page >where all the Xilinx,Altera,Lucent,...product are listed and >roughly but ONESLTY compared ? Not that I know of. There are many ways to read a competitors data sheet. All vendors have products that may be suitable for one particular application, but may not be suitable for another. Your request is a bit like the "I want to buy a car, should I buy Ford, Chevrolet, Ferrari...?" question. More information is required, such as what your requirements are now, and may be in the future. What kind of designs will you be doing? What system clock speeds do you need? What density? What power consumption? What design flow? etc. etc. StuartArticle: 7538
On 18 Sep 1997 23:55:48 GMT, johna@dvorak.amd.com (John Archambeault) wrote: > Speaking of the Atmel EEPROM. It works great but it defaults to having >an active high RESET, whereas the Xilinx parts have an active low RESET. The >data sheets on the ATMEL 17C65 say that there is a bit you can program in the >EEPROM itself to invert the RESET pin so that it is effectively active low >(like the Xilinx FPGA.) > However, I was curious (and I'm sure so is >Eric) if anyone knows how to program that single bit on the ATMEL part. We use 17C64 devices and because at that time the (relative) cheap ATMEL burner wasn't available made our own hard- and software. The point of RESET polarity did cost us a lot of time but it is documented in the databook. When I sent an EMAIL to ATMEL they even sent me most of the sourcecode for their hardware. If you analyse the source you could get enough information to build your own hardware. RK For EMAIL remove DELETE from the adress !Article: 7539
Is there a source for an implementation of a simple asynchronous serial interface in an ALTERA FPGA ? I just tried the macro Function 8251 and it alone needed more than 500 logiccells. RK For EMAIL remove DELETE from the adress !Article: 7540
Joe Vornbrock wrote: > > > Anyone have experience with these? > We have used them on several projects and they work great! > > What PROM burner is required to program them... I only have a Xilinx > > HW130 but would buy a new prom burner if the price is right... > Atmel sells a burner for about $100, but you might want to look into > in-circuit re-programming. > That is what we do, and it is really nice. Can you give us details on how you handle the three states. My Xilinx data does not mention state i) ( funny that ? :-) i) isp program of FLASH 17xx ii) FPGA self boot load, from isp iii) FPGA run... thanks - jim -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Reusable object modules, for i2c, SPI and SPL bus interfaces = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55 = for more info, Email : DesignTools@xtra.co.nz Subject : c51ToolsArticle: 7541
johna@dvorak.amd.com (John Archambeault) wrote:
:
: Speaking of the Atmel EEPROM. It works great but it defaults to having
:an active high RESET, whereas the Xilinx parts have an active low RESET. The
:data sheets on the ATMEL 17C65 say that there is a bit you can program in the
:EEPROM itself to invert the RESET pin so that it is effectively active low
:(like the Xilinx FPGA.)
:
: I got around this by hooking up the LDC_ (Low During Configuration) pin
:from the Xilinx FPGA to the EEPROM. However, I was curious (and I'm sure so is
:Eric) if anyone knows how to program that single bit on the ATMEL part.
:
You can get the AT17C65 data sheet from Atmel's website.
FWIW, the AT17C65 is ISP, you can do it over a 2-wire bus, without a
special programmer. The protocol is essentially I2C.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger daveb@opera.iinet.net.au
servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7542Marco Cavadini wrote: > > Hello, I have to make choose the right programmable logic > device for my system design. Is there an home page > where all the Xilinx,Altera,Lucent,...product are listed and > roughly but ONESLTY compared ? > > (speed, cost, performance with finite states machines, arithmetic,... > ..TOOLS !!!....) > > Thank you > ______ __ > / ____ \ / /_ Marco Cavadini Electronics Laboratory ETH-Zurich > / /_/ _\_\/ / _\_ TEL: +41(0)1 6322749 mailto:cavadini@ife.ee.ethz.ch > /___/\__._)_/\__._) FAX: +41(0)1 6321210 http://ife.ee.ethz.ch/~cavadini A fellow named Dr. Stephen D. Brown has given talks and published books about this topic in the past, so you might try a literature search on that name. -- Barry A. Brown Hewlett Packard Co. **** Remove the "poop" from my spam-resistant email address *****Article: 7543
Hi Reinhard - Try the FreeCore Library at http://www.acte.no/freecore/ - you'll find a general purpose UART that's beautifully done in AHDL. Enjoy! Jim Horn Reinhard Kopka (kopka@sbox.tu-graz.ac.DELETE.at) wrote: : Is there a source for an implementation of a simple asynchronous : serial interface in an ALTERA FPGA ? : I just tried the macro Function 8251 and it alone needed more than 500 : logiccells. : RK : For EMAIL remove DELETE from the adress ! -- Jim & Celeste Horn The Horn Ranch (Critters R Us)Article: 7544
Hi there,
I've just latched on to fpgas and want to do my own processor and things
like that.
The problem is: I don't want to pay billions for software, and in fact, I
don't even want to spend time in learning how to use them. I want to
write my own configuration software, because I'm interested in the
possibilities of dynamic (in-system) reconfiguration. By dynamic here I
mean: not pre-architectured by in a design-program session.
But, alas, there are a few flies in this soup: data-bitstream-formats
seem to be closely guarded trade secrets. Only the Xilinx 6200 seems to
have its format published. And that's a quite expensive chip to start out
on.
My question: Is this true? Is there nothing one can do about it?
Has anybody tried hacking the format of any of these chips?
I know this may be getting a bit illegal here, but I'm not interested in
making money myself. I just want to do this as a hobby.
Thanks anyway for any answers,
Nikolaus Strater, Exeter UK
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 7545nstrater@mcmail.com wrote in article <874781985.3786@dejanews.com>... > But, alas, there are a few flies in this soup: data-bitstream-formats > seem to be closely guarded trade secrets. Only the Xilinx 6200 seems to > have its format published. And that's a quite expensive chip to start out > on. > > My question: Is this true? Is there nothing one can do about it? > Has anybody tried hacking the format of any of these chips? I'd guess the FPGA manufacturers could very well release that info but then the synthesis software houses couldn't charge $3000 for each fpga-type back-end module could they, and they would get pissed at the FPGA manufacturers then. Another reason is that if a lot of public-domain unsupported generation tools became available, the FPGA manufacturers tech-support could get swamped with all the complaints from the "broken" fpga's that are just badly programmed because a bit in the format was "hacked" wrongly. So they want only the real licensed tool companies to be able to program their chips. Even normal small PALCE22V10's programming algorithms are tradesecrets, I've only heard about the GAL16V8's having a public programming algorithm. It sucks, but that's the way it is I guess :( BjornArticle: 7546
In article <01bcc627$b638a100$f3f12fc2@zeus>, Bjoern Wesen <bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote: >I'd guess the FPGA manufacturers could very well release that info but then >the synthesis software houses couldn't charge $3000 for each... There is definitely a smell of financial considerations here. :-( It would sure be nice if the FPGA manufacturers would decide they were in the chip business and wanted to sell as many chips as possible, instead of trying to make money on the support software too. Some of them have started to come around, but not nearly far enough... >Another reason is that if a lot of public-domain unsupported generation >tools became available, the FPGA manufacturers tech-support could get >swamped with all the complaints from the "broken" fpga's that are just >badly programmed because a bit in the format was "hacked" wrongly... Oddly enough, some of said manufacturers also sell EPROMs, and print the programming algorithms for *those* chips in every datasheet... There is just a wee hint of inconsistency here. It couldn't have anything to do with the fact that EPROMs are a highly competitive market with many alternate sources, of course. :-) To be honest, there is *one* argument for the bitstream secrecy that does make some sense, on the RAM-based FPGAs. Customers want to maintain their chip designs as trade secrets, and that's a bit difficult when you can pick off (or read out) the bitstream easily enough. Fixing this, with an open-format bitstream, is awkward: either you include some fairly complex encryption hardware on the chip, so the bits can be encrypted, or you add EPROM/EEPROM/flash cells -- with all the extra process pain that causes -- so the bitstream never needs to be exposed externally. Just keeping the bitstream format secret looks like a cheap way out of this. -- The operating systems of the 1950s will be out | Henry Spencer next year from Microsoft. -- Mark Weiser | henry@zoo.toronto.eduArticle: 7547
Henry Spencer <henry@zoo.toronto.edu> wrote in article <EGu9z5.5AK%spenford@zoo.toronto.edu>... > >Another reason is that if a lot of public-domain unsupported generation > >tools became available, the FPGA manufacturers tech-support could get > >swamped with all the complaints from the "broken" fpga's that are just > >badly programmed because a bit in the format was "hacked" wrongly... > > Oddly enough, some of said manufacturers also sell EPROMs, and print the > programming algorithms for *those* chips in every datasheet... There is > just a wee hint of inconsistency here. It couldn't have anything to do > with the fact that EPROMs are a highly competitive market with many > alternate sources, of course. :-) But in what way can an EPROM fail? There is a much larger error margin with FPGA's because they are a thousand times more complex. Get one bit wrong in some place, and a routing goes haywire or a row of output cells decide to reconfigure as large dataword matchers. BjornArticle: 7548
John Archambeault <johna@dvorak.amd.com> wrote in article <5vsf24$co$1@amdint2.amd.com>... snip ------ > ...from the Xilinx FPGA to the EEPROM. However, I was curious (and I'm sure so is > Eric) if anyone knows how to program that single bit on the ATMEL part. > > Thanks, > John > > BTW: I also used the BP microsystems PROM burner ---snip I too am using a BP Microsystems programmer for these parts. The reset polarity can be set in the 'device' menu before programming. Nick BartonArticle: 7549
In article <01bcc678$cee3ebf0$f3f12fc2@zeus>,
Bjoern Wesen <bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote:
>Henry Spencer <henry@zoo.toronto.edu> wrote in article
><EGu9z5.5AK%spenford@zoo.toronto.edu>...
>> >Another reason is that if a lot of public-domain unsupported generation
>> >tools became available, the FPGA manufacturers tech-support could get
>> >swamped with all the complaints from the "broken" fpga's that are just
>> >badly programmed because a bit in the format was "hacked" wrongly...
>>
>> Oddly enough, some of said manufacturers also sell EPROMs, and print the
>> programming algorithms for *those* chips in every datasheet... There is
>> just a wee hint of inconsistency here. It couldn't have anything to do
>> with the fact that EPROMs are a highly competitive market with many
>> alternate sources, of course. :-)
>
>But in what way can an EPROM fail? There is a much larger error margin with
>FPGA's because they are a thousand times more complex. Get one bit wrong in
>some place, and a routing goes haywire or a row of output cells decide to
>reconfigure as large dataword matchers.
But if all customer support had to deal with was bitstream formats, their
job would be much easier. Which would you rather do, fix every windows (and
4 flavours of UNIX, DOS and NT) configuration problem which prevents your
vastly complex software from working and debug the customer's vhdl, verilog,
orcad, viewlogic and whatever other input format the software accepts, or
decompile a customer's bitstream to tell him that he has two outputs shorted
together (or whatever)?
I think it's pretty clear that they are just protecting their software
monopolies. Why else would Xilinx have bought neocad, for example? If you
don't know, neocad was a company which reverse engineered the bitstream
formats and came out with their own improved place & route software. Note
they didn't get sued, they just got bought. Keep that in mind if you do
successfully reverse-engineer the bitstream formats: your prize will be
Xilinx buying you for millions of dollars.
I really don't understand why PAL and GAL manufactures protect their
programming algorthms so well. They don't get very much (or any) money from
software sales. All I've heard is that the programming algorithm gives away
secrets about the design or manufacturing process of the GAL. This is
simply ridiculous, as any valuable trade secrets would be patented. Maybe
they're trying to hide the fact that they've infringed on someone else's
patents? Maybe their managers are just paranoid idiots?
Actually I think it's all a big conspiracy to prevent people with no money
from being any competition for the large sluggish, but cash (or at least
credit) rich corporations.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
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