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"Austin Franklin" <dar8kroom@ix.netcom.com> writes:
> They don't call the Mazda Miata the Miata in Portugal....you might want to
> look that one up too!
The same goes for the Nissan Pajero that wasn't terribly popular in
some regions of spain where they speak a certain dialect ...
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 7776
Achim Gratz wrote:
>
> "Austin Franklin" <dar8kroom@ix.netcom.com> writes:
>
> > They don't call the Mazda Miata the Miata in Portugal....you might want to
> > look that one up too!
>
> The same goes for the Nissan Pajero that wasn't terribly popular in
> some regions of spain where they speak a certain dialect ...
>
> Achim Gratz.
>
> --+<[ It's the small pleasures that make life so miserable. ]>+--
> WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
> E-Mail: gratz@ite.inf.tu-dresden.de
> Phone: +49 351 463 - 8325As well as the Chevy Nova in Spanish speaking
countries where "No Va" translates to "doesn't
go".
Adam Elbirt
Article: 7777
1998 IEEE/ACM International Workshop on Logic Synthesis
http://www.ee.princeton.edu/iwls98.html
Granlibakken Resort, Lake Tahoe, California
June 7-10 , 1998
(this is the week before DAC, to be held in San Fransisco )
Call for Participation
Submission Deadline Feb 20, 1998
(Papers submitted to IWLS are eligible for submission to ICCAD.)
Contents
1. Synopsis
2. Benchmarks
3. About IWLS
4. About Granlibakken
5. Executive Committee
6. Technical Program Committee
7. Sponsored by...
Synopsis
Logic Synthesis has traditionally focused on optimization techniques for
combinational and sequential circuits through the manipulation of
Boolean
equations and state machines. IWLS '98, the seventh workshop in this
series,
seeks presentations both on these topics and on new directions in
synthesis
for deep-sub micron technologies and synthesis and physical design.
Topics of interest include:
Interaction with physical design Area, timing, power
optimization
CMOS, ECL, GaAS Optimization Designer Experiences with
Synthesis
Two-level Logic Optimization Logic synthesis
systems
Multi-level Logic Optimization Incremental Synthesis/ECO
Support
FSM Optimization Asynchronous Logic
Synthesis
Sequential Circuit Optimization Formal
Verification
Retiming and resynthesis Optimization at the RTL
Level
Technology Mapping Timing
Verification
FPGA and PLD Synthesis Testing and Synthesis for
test
Don't-Cares and Boolean Relations Interaction with module
generators
Symbolic Synthesis Use of synthesis in new
applications
Synthesis in FPGA-Based Emulation Applications of
SAT
Authors may submit extended abstracts for their proposed presentation.
These
must be no less than 1000 words and no more than 2500 words. These
abstracts
are not intended to be complete papers, but rather should convey the
main
ideas of the proposed presentation. We encourage submissions in the
early
stages of research which may highlight important new problems without
necessarily providing complete solutions. The abstracts may be submitted
by
e-mailing self-contained Postscript files to stokl@watson.ibm.com by
Feb 20, 1998. Acceptance notices will be sent by March 31, 1998. A set
of workshop notes will be distributed at the conference. There will be
no
published proceedings.
Benchmarks
A benchmark set is being assembled by the CAD Benchmarking Laboratory.
To
contribute new benchmarks, or to obtain information about the existing
suite, please write: benchmarks@cbl.ncsu.edu.
About IWLS
IWLS has always intended to be a forum for open discussions of ideas. To
this
extend we have an open program with high acceptance rate, heavy use of
posters
and short talks for presentation, and large amounts of time in the
schedule
for poster presentations. In addition, IWLS '98 will again include focus
groups to simulate interaction between participants in yet another
format.
About Granlibakken
The Granlibakken Conference Center is located in Tahoe City on the west
shore of Lake Tahoe, 180 miles east of San Francisco. It boasts 160
rooms,
clustered into two- and three-bedroom condominiums. Each bedroom is an
attractive hotel room with private bath. Many of the clusters share a
kitchen, living room and dining room -- a miniature lobby for private
meetings. Organizations sending several people to the workshop may wish
to
rent entire two- and three-bedroom townhouses.
Granlibakken is within 10 minutes' drive of the West's premier ski
resorts:
Alpine Meadows and Squaw Valley USA. When California enjoys high
snowfall,
both areas remain open until Memorial Day. A wealth of hiking trails
snake
through the area. Weather permitting, Granlibakken's tennis courts and
pool
will be open for use.
The weather in early June is variable; warm, sunny days and cool clear
nights
are the rule.
Getting There
Granlibakken is easily reached from either the San Francisco Bay Area or
Reno, NV. Take Interstate 80 to Truckee. From there, follow State Route
89
south to Tahoe City. Turn right at the stop light in Tahoe City. After
1/4
mile, turn right on Granlibakken road and proceed to the end.
Contacts/Executive Committee
General Chair Rick Cadence mcgeer@cadence.com (510)
McGeer Berkeley Labs 647-2803
Vice Chair Fabio Cadence fabiob@cadence.com (510)
Somenzi Berkeley Labs 647-2818
Tech. Program Leon IBM (914)
Chair Stok stokl@watson.ibm.com 945-1817
Benchmark Franc (919)
Chair Brglez NCSU brglez@cbl.ncsu.edu 248-1925
Conference Kris Cadence (510)
Coordinator Lamanno Berkeley Labs krisl@cadence.com 647-2801
Technical Program Committee
Pranav Ashar NEC
Michel Berkelaar TU-Eindhoven
Robert K. Brayton UC Berkeley
Franc Brglez NCSU
Jordi Cortadella Universitat Politecnica de Catalunya
Masahiro Fujita Fujitsu Laboratories of America
Wolfgang Kunz University of Potsdam
Luciano Lavagno Politecnico di Torino/Cadence Berkeley Labs
Rick McGeer Cadence Berkeley Labs
Sharad Malik Princeton University
Shin-ichi Minato NTT
Massoud Pedram USC
Richard Rudell Synopsys
Tsutomu Sasao Kysushu Institute of Technology
Gabriele Saucier INPG
Ellen Sentovich Cadence Berkeley Labs
Narendra Shenoy Synopsys
Fabio Somenzi University of Colorado
Leon Stok (chair) IBM
Sponsor
Sponsored by the IEEE Computer Society, Technical Committee on VLSI. In
co-operation sponsoship by ACM/SIGDA is being sought
Article: 7778
Dean Brown wrote:
> Has anyone ever used Accolade's PeakVHDL VHDL simulator ? If so, I'm
> curious what your experience with it was, e.g. ease of use, run times,
>
> support of the VHDL language, etc. Any feedback would be welcome.
>
> Thanks
>
> Dean Brown.
> Santa Clara, CA.
We at APS are distributors of the PealVHDL simulator and PeakFPGA
synthesis. We package them with low cost router options under our
SynthAll packages. We are also harware designers who have used Modeltech
etc. The PeakVHDL simulator is an outstanding value. I used it recently
along with PeakFPGA to develop an FPGA design in a 4000/5200 208 QFP
series FPGA. One neat thing about the PeakVHDL and PeakFPGA is the
seamless integration of the simulator and synthesis tool. The synthesis
tool also supports XILINX, ALTERA,LUCENT, ACTEL, QUICK LOGIC, VANTIS,
and LATTICE., withmore (like ATMEL) coming. And the price is very
reasonable when compared to other tools. For instance:
XILINX PAK
Synth-All PeakFPGA Synthesis (XILINX, ALTERA,LUCENT, ACTEL, QUICK
LOGIC, VANTIS, and LATTICE)
PLUS
option1: VHDL Simulator
option2: XILINX M1 router (with download cables)
option 2a: APS-X84 FPGA development board
option 4 Pod-A-Lyzer 100 Mhz Logic Analyzer pod
ALL for........ $7500.00 !!!
Plus you qualify for low cost router upgrades if you want a Lucnet
router for instanc, or a lattice fitter, or a Vantis fitter, etc....
The other unique aspect of the PeakVHDL simulators is that we offer the
version three simulator for as little as $699.00 !!!
The full Version 4 simulator comes with VITAL support and sorce debugger
and sells for
around $1300.00 plus 500.00 for the VITAL support.
All these packages can be seen at http://www.associatedpro.com/aps
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: aaps@erols.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 7779
Hello,
I'd like to translate AHDL (Altera Hardware Description Language) files
into VHDL files. Do you know an option in Maxplus2, or a free conversion
tool which could perform this translation ?
I know Maxplus2 is able to generate a netlist in VHDL format after having
compiled/placed/routed a design, but this is not what I need. I just want
a VHDL transcription of my AHDL files.
Thanks in advance for your answers.
--
Jacques-Olivier Haenni http://diwww.epfl.ch/~johaenni/
Logic Systems Laboratory | johaenni@lslsun.epfl.ch
Swiss Federal Institute of Technology (EPFL) | Tel: (+41 21) 693 66 30
1015 Lausanne - Switzerland | Fax: (+41 21) 693 37 05
Article: 7780On 10 Oct 1997 15:23:41 +0100, Christy Looby <clooby@nmrc.ucc.ie> wrote: >brian@shapes.demon.co.uk (Brian Drummond) writes: [snip] >The quote in the reference above "..it is faster to travel to the right than >to the left, and slightly faster to travel down than up...(XC3100) .. Families >such as the XC4000 do not have this directionality, but are not as fast for >direct interconnect between neighbours." For the XC4000EX & XL (or at least, the XL, which I am now using), directionality DOES affect the speed. For the fastest possible connections, the destination CLB should be directly below, or directly to the right, of the the source CLB/FF. > This indicates the above question is unlikely to have a positive answer. > >The original poster's question about the XC4000 max pipelined speed can be >calculated by following the analysis of von Herzen.. or just work it out >by hand from a timing budget and the databook (which I don't have to hand) > >-- >Regards, <pre> >--------------------logo:Silicon Wafer---------------------------------- >Christy Looby, .--~~~~~--. E-mail: clooby@nmrc.ucc.ie >NMRC, Univ. College, .'/_N_M_R_C_\`. Phone +353 (0)21 904 064((Direct) >Lee Maltings, Cork, |_/_/_|_|_|_\_\_| Fax " " 270 271 >REPUBLIC OF IRELAND \_I_R_E_L_A_N_D_/ Nat'l-Microelctronic-Res'rch-Cntr > `-------------' (NMRC) >------------------------------------------------------------------------ >http://nmrc.ucc.ie http://www.ucc.ie/ucc/socs/squash/clooby.html </pre> Jason T. WrightArticle: 7781
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 7782
On Mon, 13 Oct 1997 16:18:58 +0200, Christian Schaefer <schaefer@ls12.informatik.uni-dortmund.de> wrote: >Hello, > >the Synopsys command "report_fpga" gives some statistics about >CLBs, function generators and flip flops. When we feed the designs >to XACT, they use significantly more CLBs than Synopsys reported. >Additionally, the XACT design statistics gives two values for >CLB utilization: the actual occupied CLBs and the "packed CLBs" >(often significant lower). > Actually, I have seen Xilinx use fewer CLBs than the Synopsys estimate. (But this is probably due to pruning back from unconnected nodes.) >What are the relations between Synopsys estimates, XACT "packed >CLBs" and the actual used number of CLBs? The XACT manual says >nothing about "packed CLBs". > >Christian. "Packed CLBs" indicates the minimal usage, assuming no rearranging needs to be done to meet timing (or other) criteria. The actual is almost always higher. Jason T. WrightArticle: 7783
2-4 Electrical Engineers needed for contract, temp-to-perm, or permanent basis with an Avionics firm in the beautiful Portland, Oregon area. Xilinx FPGA experience is a must as is schematic capture tool experience, OrCAD preferred. Very cool projects. For consideration and/or more detailed info, reply with or fax resume ASAP. -- Steven Rhodes MSI Consulting Portland, Oregon 503/222-1828 faxArticle: 7784
When you refer to 'applications', are you asking about design that go in
an FPGA or the software to build an FPGA design?
For software, you may be interested in the Software section on The
Programmable Logic Jump Station at
http://www.optimagic.com/software.html and
http://www.optimagic.com/lowcost.html.
For applications that go in an FPGA, you may find the Consultants
section (http://www.optimagic.com/consultants.html) and the Research
section (http://www.optimagic.com/research.html) interesting.
Plus, the various device manufactures have lists of cores, some
available from third-parties, available on their web sites. For
example, see the Xilinx LogiCORE AllianceCore program
(http://www.xilinx.com/products/logicore/logicore.htm) and the Altera
AMPP program (http://www.altera.com/html/programs/ampp.html).
-----------------------------------------------------------------------
Steven K. Knapp OptiMagic, Inc.
sknapp@optimagic.com http://www.optimagic.com
Great designs happen "OptiMagic"-ally
Thielemans - Van Heghe wrote in message
<01bcd6fe$25212e20$020ceec3@login.skynet.be>...
|Hello,
|
|Apart from the FPGA vendor sites, are there other design sites with
|applications available ?
|Thanks in advance !
Article: 7785When implementing numerical algorithms (e.g. DCT) on FPGA using VHDL, do I need to translate my algorithm into logic function before I can code it in VHDL? Or, is it possible to describe a numerical algorithm directly using VHDL and let the FPGA tool to synthese the required logic function? I have no experience on this. Thank for any help. C. F. FungArticle: 7786
Can someone tell me the address of the homepage which keeps record of all FPGA articles ever posted? I have once bookmarked this homepage but I have lost it due to hardisk crash. Thanx for your help.Article: 7787
jan, have you looked at the new Atmel AT40K as an implementation vehicle for CPUs? at first blush, it appears to have enough SRAM to to build decent-size register files. and you might even be able to implement a multiplier .... the Atmel app note says a fully-pipelined 8*8 multiplier is 350 cells. cheers atw not speaking for intel....Article: 7788
Check out CircuitOnline..Searchable directory of services designed for the electronics/semiconductor design and manufacturing: http://www.circuitonline.com CAD Tools, IC Design Services, VLSI Research, FPGA, MaegacellsArticle: 7789
I believe that you are looking for the comp.arch.fpga archive which is at http://www.super.org:8000/FPGA/arrive.html . However, I understand that more recent articles are no longer stored there. You should be able to find most of the more recent article using the DejaNews service, which is available at http://www.dejanews.com . These newsgroups, their archives, and other related material is available via The Programmable Logic Jump Station at http://www.optimagic.com/newsgroups.html . PHILIP TSANG wrote in message <01bcd926$5b37cee0$8d8249ca@default>... |Can someone tell me the address of the homepage which keeps record of all |FPGA articles ever posted? I have once bookmarked this homepage but I have |lost it due to hardisk crash. Thanx for your help. |Article: 7790
You can code your algorithms directly in VHDL and then synthesize to a given FPGA family. However, you may lose some efficiency. The resulting FPGA design will probably be larger and slower than if custom-crafted for the application. There are also some module generator packages that create the custom logic for a given FPGA family. In the case of the Xilinx tool, it also generates a VHDL instantiation code fragment so that you can add the function to a larger design. Some links of interest include: Xilinx press release that includes info on their DCT implementation. It's buried in the release. http://www.xilinx.com/prs_rls/reed_fft.htm . They also have other DSP functions (see http://www.xilinx.com/products/logicore/tblcores.htm#DSPFunctions ). Atmel's DSP Designer - http://www.atmel.com/atmel/news/19970707.html ----------------------------------------------------------------------- Steven K. Knapp 'Great designs happen "OptiMagic"-ally' OptiMagic, Inc. E-mail: sknapp@optimagic.com Web: http://www.optimagic.com Phone: 1-408-454-1811 |When implementing numerical algorithms (e.g. DCT) on FPGA using VHDL, do I |need |to translate my algorithm into logic function before I can code it in VHDL? |Or, is it |possible to describe a numerical algorithm directly using VHDL and let the |FPGA |tool to synthese the required logic function? | |I have no experience on this. Thank for any help. | |C. F. FungArticle: 7791
Hello, does somebody now the pinout of the Download Cable for In-System programming of LATTICE ispLSI? I have download the file "DLCABLE.PDF" from LATTICE ftp server, but there is no detailed pinout. Thanks in advance, Egon.Article: 7792
I have an old 1991 DOS Viewdraw & Viewsim. Totally bug-free and reliable. Works with both the old APR, and with the PPR from XACT6 which I bought about 2 years ago. I am now looking at the M1 place & route software, but this is NT only. (It also does not support XC3000 but that is another story - apparently the next version will). This makes the old Viewdraw stuff a pain to use because its DOS extender does not run in a NT DOS box. So I am looking at alternative schematic entry solutions which don't cost a fortune like Workview Office. Protel Schematic 3.2 is not too bad as Windows schematic entry progs go. It comes with loads of Xilinx library parts. But it will not (AFAIK) emit XNF directly. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 7793
Adam Elbirt (aelbirt@viewlogic.com) wrote: : Achim Gratz wrote: : > : > "Austin Franklin" <dar8kroom@ix.netcom.com> writes: : > : > > They don't call the Mazda Miata the Miata in Portugal....you might want to : > > look that one up too! For a similar reason that the old show "Joanny loves Chaci" was the most popular premiere ever to air in Korea. Go figure what Chaci means.Article: 7794
In article <3445200c.4725745@pop-news.metronet.de>, Egon Bild <ebild@metronet.de> writes >Hello, > >does somebody now the pinout of the Download Cable >for In-System programming of LATTICE ispLSI? I have >download the file "DLCABLE.PDF" from LATTICE ftp >server, but there is no detailed pinout. > >Thanks in advance, >Egon. It's not just a cable, but has some buffering built-in to the connector. The circuit is on the free Lattice CD-ROM. I can probably send you the image if you have problems getting the CD-ROM. Leon -- Leon Heller: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk Amateur Radio Callsign G1HSM Tel: +44 (0) 118 947 1424 See http://www.lfheller.demon.co.uk/rcm.htm for details of a low-cost reconfigurable computing module using the XC6216 FPGAArticle: 7795
db wrote:
>
> I am looking to simulate my VHDL FPGA design and would like to design a
> testbench that includes a VHDL model of an SRAM (32K x 8). Does anyone
> have a good way of doing this? I was thinking of using textio
> statements to use a file as the memory but am not quite sure how to go
> about doing this, and even then am not sure this wouldn't slow the
> simulator (ModelTech) to a crawl. Any suggestions would be
> appreciated....thanks!!
A better way would be to use an array as the memory, and load it from a
file at initialization.
The DLX Case Study in The Designer's Guide to VHDL includes a memory in
the test bench. See Section 15.3, which includes a memory that is
"preloaded" with a program. See also Figure 18-9 in Section 18.2. It
describes a version of the memory that is intialized from a text file
using textio. Source code for the examples can be found by following
the links from my web page.
Hope this helps.
Cheers,
PA
--
Peter J. Ashenden Email: petera@ececs.uc.edu
Visiting Scholar, Dept ECECS peter.ashenden@acm.org
University of Cincinnati Phone: +1 513 556 4756
PO Box 210030 Fax: +1 513 556 7326
Cincinnati OH 45221-0030, USA
http://www.cs.adelaide.edu.au/~petera/
(includes PGP public key)
Article: 7796A dynamic FPGA group of one the largest ASIC organizations in the world is looking for a Software Development Manager/Site Manager to manage a development team(10-15) in developing a complete FPGA implementation toolset which supports the companies FPGA product line. Resp-software development of CAD algorithms and design methodologies in the areas of CAE interfaces, technology mapping, placement, routing, timing analysis, and post-layout simulation. BSEE/CS or MSEE/CS---5 to 10 years exp in CAD development, UNIX knowledge, C/C++ exp, and FPGA knowledge is preferred. Some supervisory exp would be helpful. Location-Boulder, Co. Salary- To 125K + 12 to 15% bonus -- Eddie Amara- Executive Recruiter SpencerSearch,Inc. "We Specialize in Recruiting Premier Talent for Exceptional Companies in the Semiconductor Industry" Home Page-http://www.spencersearch.com Voice 972-378-0280 Fax 972-378-0279 Email amaraju@onramp.net =====================================================================Article: 7797
Michael David Scott wrote: > > Adam Elbirt (aelbirt@viewlogic.com) wrote: > > : Achim Gratz wrote: > : > > : > "Austin Franklin" <dar8kroom@ix.netcom.com> writes: > : > > : > > They don't call the Mazda Miata the Miata in Portugal....you might want to > : > > look that one up too! > > For a similar reason that the old show "Joanny loves Chaci" was the most > popular premiere ever to air in Korea. > > Go figure what Chaci means. Ciaci (pronounced chaci) in polish means AuntArticle: 7798
Egon Bild wrote: > > Hello, > > does somebody now the pinout of the Download Cable > for In-System programming of LATTICE ispLSI? I have > download the file "DLCABLE.PDF" from LATTICE ftp > server, but there is no detailed pinout. > > Thanks in advance, > Egon. for the 8 pin Amp .100 SIP connector: pin description 1 VCC 2 SDO (from the device) 3 SDI (to the device) 4 /ispEN 5 Key (plugged hole in connector) 6 MODE 7 GND 8 SCLK There should be a .1uf cap between /ispEN and ground on your board. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 7799
A dynamic FPGA group of one of the largest and most successful ASIC organizations in the world is looking for a Field Applications Engineering Manager. Will manage a team of FAEs that are involved in customer support of FPGAs including: technical evaluation, product planning, detailed design, design optimization, and system integration, training, presentations and benchmarking. BS or MSEE/CS/CE and 5+ years experience in applications(factory or Field) of PLDs, ASICs, or FPGAs required. A design background is also helpful. Experience with SOA CAD tools including Verilog or VHDL. Management or supervisory experience is also a plus. Strong communication and organizational skills are required. Location- Allentown, Pa. Salary- To 125K + bonuses -- Eddie Amara- Executive Recruiter SpencerSearch,Inc. "We Specialize in Recruiting Premier Talent for Exceptional Companies in the Semiconductor Industry" Home Page-http://www.spencersearch.com Voice 972-378-0280 Fax 972-378-0279 Email amaraju@onramp.net =====================================================================
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