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This is a followup to a followup to a thread I started about a week ago... > I received the following email response to a posting I submitted > on 6-feb to the comp.arch.fpga newsgroup. The reply was sent by Bryon > Moyer at Altera. The original posting described some nasty (but avoidable) > problems with in-system programming of Altera Max7000s devices. > > I appreciate Mr. Moyers' having taken the time to reply. > The email reply from Altera is included in its entirety, without editing: > > ================ Begin email reply from Altera ================= ... stuff deleted ... > Regards, > Bryon Moyer, Sr. Manager of Customer Applications, Altera Corp. > 101 Innovation Dr. MS 1203 San Jose CA. 95134 > (408) 544-6662 Voice (408) 544-6424 Fax email: bryon_moyer@altera.com > > ************************************************************************ > Mr. Elkind: > > I wanted to respond to your comments about the experience you had with > In-System Programming on MAX7000S parts, and to the information you were > given about solving the problem. > > The issue you experienced is not so much one of having a running global > clock signal, as much as it is one of having too much negative overshoot > (often confusingly referred to as "undershoot") on one of the global > clock signals. We have observed a few cases where such excessive > negative overshoot at the wrong frequency caused a failure to erase. In > all such cases, successfully eliminating excessive negative overshoot > (typically by adding a suitable series terminating resistor) eliminated > the behavior. Clarification accepted. Thank you. My comments: 1. In my direct experience, the free-running clock which is somehow related to this failure mechanism did *not* exhibit excessive under/overshoot. Now we are confronted with the question: what is "reasonable" undershoot? Arguably, the ISP programming circuitry should be able to sustain the same levels of undershoot as would the device in normal operation. It seems that this isn't always the case... 2. Series R term is a valuable tool, but doesn't work worth a darn for mult-load clock runs. Furthermore, it tends to slow/delay edges. In my case, the free-running clock was parallel terminated (at the end of the run). 3. Being somewhat ignorant of such things, it sounds like the input clamp diodes are sucking current out of the substrate at the clock edges, and that is wreaking havoc with the programming. If this is the case, it sounds like a nasty problem. How difficult is it to "isolate" part of the substrate from the rest of the die? > If you were informed by Altera that you needed to stop > the clock, that is incorrect information, and I apologize for the extra > work it might have put you through. Of course, stopping the clock would > work, but is not required. I will work to ensure that the correct > information is publicized within Altera. > As far as public notification is concerned, we are putting together an > application note detailing recommended design practices for successful > in-system programming. I was given several "try this" suggestions by the support guys. A formal application note should clear up this situation in short order. > Regarding future products, any changes will focus on tolerance of > excessive negative overshoot. The global clocks are already disabled > during programming; that is not a change. There are no plans to add CRC > checking to the programming algorithm. Thank you for the clarification. Perhaps the support engineer was referring to a different device series? Your response has been very helpful in correcting misinformation which I've inadvertently been spreading. > Note that where this situation occurs, removing the part from the board > and programming on a stand-alone programmer will allow the part to > recover. This is clearly not convenient from an ISP standpoint, but it > is a way to recover the parts as long as there hasn't been extreme > contention on the board. I've been practicing the removal of 208-pin QFPs, but caffeine has been my ruin! :=) > I hope this helps clarify the situation. Thank you for your time and attention, Mr. Moyer. **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 9001
Dear readers:
Altera 1998 data book states
"When power is applied to an Altera device, the device
initiates a Power-On Reset(POR).... The POR time is
the time required after VCC reaches the recommended
operating range to clear device registers, configure I/O
pins, and release tri-states. Once this initialization is
complete, the device is ready to begin logic operation.
The POR time does not exceed 100 ms. "
We are told by Altera Application support that the POR
time does not exceed 50 ms for their EEPROM based
CPLDs (MAX7000,MAX9000).
This time is still two orders of magnitude higher than
comparable Xilinx flash based CPLDs.
Any one has any ideas as to why initilization after
power-up on Altera's EEPROM CPLD takes that long?
Believe me in our application it makes a real difference!
Regards,
Kayvon Irani
Los Angeles
Article: 9002"Adam J. Elbirt" <aelbirt@viewlogic.com> wrote: >Geir, > >What really matters in this case is whether or not the synthesis tool is >smart enough to take advantage of the element for your given design. Some >are, some aren't, and there are a lot of factors that come into play. >Typically, each tool has a variety of settings that result in the usage of >different library elements. A typical example is a resource sharing option >that would use an ADDSUB component when turned on and one each of ADD and >SUB components when turned off. For situations like these, you need to >examine your synthesis tool outputs and typically tweak the appropriate >settings to try and get what you want. Even then, you may have to resort >to schematics to implement EXACTLY what you want for optimal performance or >area utilization. > >Adam > It's not only whether synthesis can use special elements of a particular FPGA, but also whether it's smart enough to minimize logic. When I checked out Alta Group's SPW, Synopsis's Behavioral, Exemplar, and Altera's DSP tools, a couple of years ago, None of them correctly recognized that a constant multiply by 9 of an 8 bit number, should use a 9 bit adder. Sure, they could be forced, kicking and screaming, to implement it this way, but schematics seemed far simpler. Schematic capture also provided an easy way to control the relative placement of the logic. this meant that I could build up libraries of minimized, preplaced DSP parts, for easy reuse. I'd rather spend 4 hours doing manual placement one time, than 40 hours of dubious automatic placement for every design change. I wonder if any of these tools have improved enough, in the last two years, that they would now instantiate a 9 bit adder. Would they also permit me to graphically, hierarchally, edit the placement of this adder with respect to the registers on its input and/or output? If so, I neet to re-evaluate Synthesis. Dave Decker Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 9003
Kayvon Irani <kirani@cinenet.net> writes:
> Any one has any ideas as to why initilization after
> power-up on Altera's EEPROM CPLD takes that long?
> Believe me in our application it makes a real difference!
Most likely because some types of EEPROM are slow to read and even
slower to write to. That's not to say that you couldn't have much
faster memory cells, but that would probably increase the cost of the
technology and/or the part.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 9004Kayvon Irani wrote in message <34E3D7F4.A0FCEA76@cinenet.net>... > Dear readers: > >Altera 1998 data book states >"When power is applied to an Altera device, the device >initiates a Power-On Reset(POR).... The POR time is >the time required after VCC reaches the recommended >operating range to clear device registers, configure I/O >pins, and release tri-states. Once this initialization is >complete, the device is ready to begin logic operation. >The POR time does not exceed 100 ms. " >We are told by Altera Application support that the POR >time does not exceed 50 ms for their EEPROM based >CPLDs (MAX7000,MAX9000). >This time is still two orders of magnitude higher than >comparable Xilinx flash based CPLDs. >Any one has any ideas as to why initilization after >power-up on Altera's EEPROM CPLD takes that long? >Believe me in our application it makes a real difference! POR is often a "legal cover-all" figure. A few years ago I worked for a microprocessor company and some work was undertaken on fast power-up on an existing 32-bit chip design to support low-power mode. The datasheets quoted 100mS POR - the app's engineers found that the micro powered up OK in about 20 to 100 clock cycles ISTR (about 1uS to 5uS), including a PLL stabilising. Check-out if they've actually measured it and it's not just a relic from the first version of the datasheet. --------------------- Stephen Maudsley Stephen.Maudsley@btinternet.com esgem limited Tel/Fax: +44-1453-521626 Mobile: +44-370-810991 ---------------------Article: 9005
Advanced RISC Machines has developed a board comprising an ARM based
micro-controller and two Xilinx FPGAs which are uncommitted and
available for user applications.
This board is at the preliminary prototype stage and we are now
looking for individuals to review our board specification so that we
can release a product that best fits our customers requirements.
A brief outline of the product:
- Full length PCI card
- ARM based micro-controller
- 1 DRAM SIMM slot (up to 32MB)
- 2 XC4000XL FPGAs (4013-4062 in 240QFP package)
- AMCC PCI Matchmaker chip
- Expansion connectors
- Can be used on the bench without PCI
Suitable candidates to be included in this review and possible
subsequent field trial would have some of the following experience:
- existing ARM development boards
- ARM software development toolkit (SDT)
- Xilinx FPGAs and development tools
- re-configurable computing
- ASIC prototyping
- embedded system design
For further information please go to the ARM web site at:
http://www.arm.com/Documentation/Feedback.html
At the box marked "Type of question" select:
Development Boards - Field Trials
Please fill in your details, including the word 'FPGA' in the subject
box and a short description of why you think you might be suitable to
take part in this review and/or field trial.
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 9006
> RWilson@oxfordnuclear.com wrote:
>
>
> We have been using the Altera classic line (EP1810LC-35T, EP910-30T,
> EPM5128LC) in several of our designs for years withour problems but,
> since the die-shrink, we have had these devices cause failures in several
> of our products. We have been pursuing Altera for help to no avail.
> They say they have no problem with the devices, but I have noticed that
> the asking price at distributors for the older lot codes has tripled for
> the 1810 device in a matter of a few months. This price hike would tell
> me that there is significant demand for older lot codes which means we
> are definitely not alone. Has anyone else using the classic line found
> solutions or gotten help from Altera ??
>
> -------------------==== Posted via Deja News ====-----------------------
> http://www.dejanews.com/ Search, Read, Post to Usenet
You might verify that your design is ABSOLUTELY 100% Synchronous. If not, a
die shrink will usually make the silicon significantly faster thus changing
the best case timing numbers. If a previous design worked because of the
inherent delays (known to you or not), it is conceivable that a faster part
would fail. We've fixed a number of these issues on Xilinx parts since they
too are continuously migrating their process geometries.
Best wishes
--
Ed McCauley
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA
(908) 996-0817
FAX: (908) 996-0817
Article: 9007I am trying to obtain some Philips P5Z22V10-7A or -DA or IDA devices. I need at least 15, but would be willing to buy a tube of 37. Also, just one or two for prototyping would be a real help. The best lead time I can get in the UK is 13 weeks (and I have some on order). Can anyone out there help? (I know these are a bit small to count as fpgas, but this seems the closest newsgroup.) In case you are wondering, these are just like normal 22V10s except that they have VERY low power consumption both static and dynamic. John WallikerArticle: 9008
The Programmable Logic News & Views web site has been updated with a summary of the December issue. http://www.plnv.com Murray DismanArticle: 9009
Princeton Information < www.princetoninformation.com > is seeking Ten (10) Senior Digital Design Engineers............ Digital FPGA Hardware Engineer -High Speed Digital Modem Technology Job Description: You will participate in the design and development of a flexible communications system breadboard utilizing FPGA's (ASIC) for Motorola's Celestri (tm) Modem Technology development program. These are specialized high-speed modems (Mbps) installed in satellites. Celestri is a multi-year, $13 billion project that will provide high-bandwidth packet switching - connections (e.g., internet) in outer SPACE!!! Celestial Data Communications for the 21st Century!!! BS/MS in Electrical Engineering +4 to 6 years of experience required. Familiarity with FPGA based design limitations and mitigation methods. Willingness to accept responsibility & technical challenge Ability to work independently and on a team Focus on customer satisfaction EMAIL your resume TODAY!!! ==> azjobs@usa.net Location: Phoenix/ Chandler, AZ Duration: Temp to Permanent Pay Rate: $55,000 => $85,0000 Also, Temp to Perm - "Try it you'll like it!" See our Website: < www.princetoninformation.com > Digital FPGA Hardware Designer - High Speed Digital Design - Modem Technology We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 4-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, Modem Technology development....... Experience with PLD's, FPGA's (ASIC), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. Our client is located in Chandler, Arizona. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail your resume TODAY===> azjobs@usa.netArticle: 9010
Kayvon Irani wrote: > Dear readers: > > Altera 1998 data book states > "When power is applied to an Altera device, the device > initiates a Power-On Reset(POR).... > This time is still two orders of magnitude higher than > comparable Xilinx flash based CPLDs. > Any one has any ideas as to why initilization after > power-up on Altera's EEPROM CPLD takes that long? > Believe me in our application it makes a real difference! There is a fairly well-kept secret regarding CPLDs: Although most of their configuration is directly EPROM, EEPROM, or Flash-based and thus does not require any lengthy power-on delay, some of the configuration bits, although stored in the non-volatile area, are then read out on power-up and loaded into latches. This applies to the miscellaneous signals around the macrocells, which cannot be conveniently or fast controlled from the well-structured non-volatile memory area. Certain CPLD manufacturers don't like to talk about that, because it smudges their pristine image of non-volatility. In reality, as Xilinx FPGAs have proven for the past 12 years, there is nothing wrong with storing configuration in latches. You just have to load them properly, and you have to detects Vcc dips. Hope that helps. Peter Alfke, Xilinx ApplicationsArticle: 9011
Maybe I should have posted this in comp.arch.cpld, but anyways...
Vantis (AMD) and Xilinx have a ISP programming interface built on
JTAG, which is great for production. Lattice have adopted this on
their newer parts (thank God), which also is good.
However, I'm using an older ispLSI1032E with an interface similar (but
not identical) to JTAG. Not good at all.
Is ther any software/equipment out there suitable for both programming
the ispLSI part and perform boundary scan testing using the same
simple connector. It's awkward to have two different interfaces for
this.
Thank you,
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 9012> > - Full length PCI card > - ARM based micro-controller > - 1 DRAM SIMM slot (up to 32MB) > - 2 XC4000XL FPGAs (4013-4062 in 240QFP package) > - AMCC PCI Matchmaker chip > - Expansion connectors > - Can be used on the bench without PCI Which ARM based Microcontroller? How about the DEC StrongARM, and then you could use the DEC 21285 StrongARM to PCI bridge chip....which, I believe, is far far far far far better than the AMCC Miss Match Maker. Austin Franklin darkroom@ix.netcom.comArticle: 9013
> I am trying to obtain some Philips P5Z22V10-7A or -DA or IDA ..... > In case you are wondering, these are just like normal 22V10s except > that they have VERY low power consumption both static and dynamic. Does this have to be from Philips? In case all you need is a low power 22V10, check out AMD's PALCE22V10Z - this is EECMOS, so it is reprogrammable. ICT and Lattice make the low power 22V10's too. AshokArticle: 9014
HELP!!! I'm using ORCAD Express' standard M1 library parts (XC9000). I run build and get no warnings or Errors from Orcad's compiler. But when it enters Xilinx's M1, I get -- "Running Logical Design DRC... ERROR:basnu:93 - logical block "BUSIF/U178" of type "CB16CLE" is unexpanded." U178 is an orcad library 16 bit counter. I've tried as many variations on the part as I can find, no diff. Surely, someone has come across something like this! Their online documentation is of no help here. Exactly WHAT does this error mean? And (more importantly) how can I fix this? TIA -- JeffArticle: 9015
Achim Gratz wrote: > Kayvon Irani <kirani@cinenet.net> writes: > > > Any one has any ideas as to why initilization after > > power-up on Altera's EEPROM CPLD takes that long? > Most likely because some types of EEPROM are slow to read and even > slower to write to. No,The storage cells in CPLD are directly involved in the operation, so they must be "read out" in a few nanoseconds, and they operate all in parallel. That's what has given CPLD their ( historic ) speed advantage. I gave a probable explanation for the slow POR in a different posting to this newsgroup. Peter Alfke, Xilinx >Article: 9016
Tell me about it.... You can try Avnet in the UK. But apparently Philips need to know your inside leg measurement before they will part with any. This is known as "Marketing". Philips also have a division in NZ which deals with these, and the programmers: www.coolpld.com coolrunner@pds.co.nz Unfortunately this is the only full-CMOS 22V10 I know of. >I am trying to obtain some Philips P5Z22V10-7A or -DA or IDA >devices. I need at least 15, but would be willing to buy a >tube of 37. Also, just one or two for prototyping would be a >real help. The best lead time I can get in the UK is 13 weeks >(and I have some on order). Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 9017
No, the AMD parts have input transition sensing, and have low power only if nothing is moving. They are not true CMOS. In the 16V8 business there are some other CMOS devices, and I think AMD do some. But not 22V10. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 9018
I would suggest a nice book that deals extensively with Wallace trees: 'Computer Arithmetic Systems" by Omondi, Prentice Hall. Regards, Anil.Article: 9019
my only comment would be: why the amcc pci chip? It seems to have a few bugs which make life real painful.... mud mud mud...mudding...mudder... For contact, post here, or to alt.anonymous.messages w/subject of Attn: mudArticle: 9020
On Fri, 13 Feb 1998 14:43:39 GMT, Aliens from the 3rd dimension made uclyjrw@ucl.ac.uk (John Ragnvald Walliker) write: >I am trying to obtain some Philips P5Z22V10-7A or -DA or IDA The best lead time I can get in the UK is 13 weeks. . . > >Can anyone out there help? >In case you are wondering, these are just like normal 22V10s except >that they have VERY low power consumption both static and dynamic. > >John Walliker > John - I've forwarded your email to a former colleague in the Programmable Products Group for Philips in Albuquerque, NM. Hopefully they can expedite things for you. The CoolRunner 22V10's use the same Fast Zero Power design technique that's used in the Philips CPLDs - Hence a cross reference at 7nS and 'zero' (uA) static power doesn't exist the last time I checked. The usual problem in these cases is either a rule that Pease talked about in his EDN column a few years ago -or- difficulty in getting the distributors to actually stock a new part (they don't like to carry inventory without a run-rate history without coercion...). Pease' comment was: Semiconductor availability comes in 2 flavors: The Parts are Available and the Customers aren't; and vice-versa... As an aside, comments to the Philips PLD group via their www.coolpld.com website *are* actually read and followed up on in real time! - Mark Aaldering former Philips Apps & Architecture Guy Now a Philips Consumer IC Systems Guy return address de-spammed... Mark Aaldering mma"at"netwiz"dot"net...Article: 9021
>> RWilson@oxfordnuclear.com wrote: >> >> >> We have been using the Altera classic line (EP1810LC-35T, EP910-30T, >> EPM5128LC) in several of our designs for years withour problems but, >> since the die-shrink, we have had these devices cause failures in several >> of our products. We have been pursuing Altera for help to no avail. >> They say they have no problem with the devices, but I have noticed that >> the asking price at distributors for the older lot codes has tripled for >> the 1810 device in a matter of a few months. This price hike would tell >> me that there is significant demand for older lot codes which means we >> are definitely not alone. The comment on Synchronous design is right on - with these older parts, I recall there being just 1 Synch clock. If you have more - then you are running asynch. With regard to price - a higher price does not necessarily mean a part problem. In those times in my life when I wore a marketing hat, we raised prices on parts heading towards end of life as a way of pushing people away from continued use, rather than just issuing an EOL notification. We felt this was offered a more gradual nudge rather than shooting a sole source part. - Mark Aaldering Mark Aaldering mma"at"netwiz"dot"net...Article: 9022
You may have a more elegant solution to this problem from Atmel. Check out...... http://www.atmel.com/atmel/products/prod2.htm bob elkind wrote in article ... >I received the following email response to a posting I submitted >on 6-feb to the comp.arch.fpga newsgroup. The reply was sent by Bryon >Moyer at Altera. The original posting described some nasty (but avoidable) >problems with in-system programming of Altera Max7000s devices. > >I appreciate Mr. Moyers' having taken the time to reply. >The email reply from Altera is included in its entirety, without editing: > >================ Begin email reply from Altera ================= >Dear Mr. Elkind: > >Your experience with Altera ISP was brought to my attention via the >newsgroup where you posted your message. I wanted to respond, both >directly to you as well as to the newsgroup. I was concerned not only >with the experience you had, but even moreso with the information you >received, much of which was incorrect. > >Please review the response below; I wanted you to see it personally >before posting to the newsgroup. If you have further questions, please >feel free to contact our hotline at (800) 800-EPLD or send an email to >sos@altera.com. > >Regards, >Bryon Moyer >Sr. Manager of Customer Applications >Altera Corp. >101 Innovation Dr. MS 1203 >San Jose CA. 95134 >(408) 544-6662 Voice >(408) 544-6424 Fax >email: bryon_moyer@altera.com > >************************************************************************ >Mr. Elkind: > >I wanted to respond to your comments about the experience you had with >In-System Programming on MAX7000S parts, and to the information you were >given about solving the problem. > >The issue you experienced is not so much one of having a running global >clock signal, as much as it is one of having too much negative overshoot >(often confusingly referred to as "undershoot") on one of the global >clock signals. We have observed a few cases where such excessive >negative overshoot at the wrong frequency caused a failure to erase. In >all such cases, successfully eliminating excessive negative overshoot >(typically by adding a suitable series terminating resistor) eliminated >the behavior. If you were informed by Altera that you needed to stop >the clock, that is incorrect information, and I apologize for the extra >work it might have put you through. Of course, stopping the clock would >work, but is not required. I will work to ensure that the correct >information is publicized within Altera. > >As far as public notification is concerned, we are putting together an >application note detailing recommended design practices for successful >in-system programming. > >Regarding future products, any changes will focus on tolerance of >excessive negative overshoot. The global clocks are already disabled >during programming; that is not a change. There are no plans to add CRC >checking to the programming algorithm. > >Note that where this situation occurs, removing the part from the board >and programming on a stand-alone programmer will allow the part to >recover. This is clearly not convenient from an ISP standpoint, but it >is a way to recover the parts as long as there hasn't been extreme >contention on the board. > >I hope this helps clarify the situation. > >===================== end of email reply ========================= > >**************************************************************** >Bob Elkind mailto:eteam@aracnet.com >7118 SW Lee Road part-time fax number:503.357.9001 >Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 >****** Video processing, R&ing0D, ASIC, FPGA design consulting *****Article: 9023
RWilson@oxfordnuclear.com wrote: > > We have experienced problems with their classic line (EP1810LC-35T, > EP910-30T, and EPM5128LC). Since the switch to the new die, the devices > program and verify OK but they flake out in certain applications. We > have actually had them generate enough heat to burn labels off of them. > Altera is not really helping us and claim we are the problem. We have > procured safety stock of old devices to protect our product lines until > we can reach a resolution. Interestingly, the market price for older > devices (pre die-change) has tripled in recent weeks. We are stumped. Problems on DIE revision are more common that many realise.. 1) You should check carefully that the algorithm has not changed - and get the confirmation from as reliable as source as possible. The reflex reaction of most FAE's is 'no, nothing has changed' 2) try as many different BRANDS of programmer as possible 3) Try and get ALTERA to program some, to your files, and give them some of the (unsecured) problem devices. That shoud help remove marginal algorithm possibilities. 4) Test the LATCH-UP characteristics of both die versions - jg -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Many reusable object modules - i2c, SPI, SPL, RC5, etc = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55. OptoISP for 89S, AVR, AT17K. = for more info, mailto:DesignTools@xtra.co.nz Subject : c51ToolsArticle: 9024
Actel's new MX line is very aggressively priced for that quantity, and their tools are available for free from their Web site at http://www.actel.com.
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