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Article: 8801
[ Editor's Note: Enclosed bellow is the note I just recieved for
EuroSNUG, the European version of SNUG. Typically about 150 users
attend this conference and it's usually held in conjuction with
ED&TC + EuroDAC. (It hasn't changed. ED&TC and EuroDAC have merged
into something called DATE'98 [Design Automation and Test Europe]. )
Through some friends within Synopsys, I've heard that EuroSNUG'98
is also going to have EPIC and Viewlogic products incorportated into
the agenda. I've also heard Synopsys plans to take the guests to
dinner plus some sort of casino event, partaking in the Paris nightlife.
And, keeping with the new Synopsys philosophy of Web-Customers-Only,
it appears that the only way to register for EuroSNUG'98 is by a form
only accessable on the Web (just like SNUG'98!!!) :^) - John ]
Synopsys invites you to the Seventh Synopsys Users Group
for European Users (SNUG Europe), February 26/27 1998, Paris, France.
The Seventh Annual Synopsys European Users Group Conference (SNUG Europe)
will take place early next year in Paris on Thursday and Friday, February
26/27 following DATE 1998 in Paris.
SNUG Europe will provide you with the opportunity to meet other Synopsys
users and share application ideas and experiences on your use of Synopsys'
tools and products. SNUG Europe is also a great opportunity to meet and
share your views with Synopsys executives, managers and corporate
applications engineers from Europe and the U.S.
The combination of SNUG Europe'98 and DATE conference and exhibition
provides a unique opportunity for the Synopsys user to extract the maximum
technical value from a visit to Paris. Synopsys will post updated details
on SNUG Europe 1998 at this address:
http://www.synopsys.com/news/events/eurosnug/esnug98_main.html
Please complete the Early Registration form below you find there and mail
it or fax it to Marilyn von Hoenning at Synopsys European Headquarters.
Marilyn von Hoenning
Synopsys European Headquarters
Stefan-George-Ring 6 Tel.: +49 89 99320 165
D-81929 Munich, Germany Fax: +49 89 99320 132
Early registration closes on Tuesday, February 3, 1998.
The Early registration payment fee is only US $200 (a saving of US $40).
If you have any questions on early registration please send an e-mail to
SNUGEurope@synopsys.com.
Address for SNUG Europe 1998 location is:
Le Meridien Hotels de Paris
81, Bld Gouvion Saint-Cyr
75848 Paris Cedex 17
Telephone: +33 1 40 68 34 34
Telefax: +33 1 40 68 31 31
Internet: http://www.forte-hotels.com
-----------------------------------------------------------------------------
__)) "Glass ceilings? Name ANY ex-goat farmer who's made management!"
/_ oo
(_ \ Holliston Poor Farm - John Cooley
%// \" Holliston, MA 01746-6222 part time Sheep & ex-Goat Farmer
%%% $ jcooley@world.std.com full time contract ASIC & FPGA Designer
Article: 8802
--------------FCB6B052DC34F2E19AE61099
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
I wish to create a DIVIDE BY N(where N is any integer between 1 and 32)
clock generation circuit. The source input clock frequency is 48Mhz and
wish to produce
clocks at 16Mhz, 8Mhz, and 2Mhz (50% duty cycle for each of these clocks
is
a design goal). If anyone has any information regarding this issue
please respond.
P.S. If you know of any BANDX devices which have this functionality also
reply
Walter C. Washington
--------------FCB6B052DC34F2E19AE61099
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<HTML>
<FONT FACE="Times New Roman,Times">I wish to create a DIVIDE BY N(where
N is any integer between 1 and 32) clock generation circuit. The source
input clock frequency is 48Mhz and wish to produce</FONT>
<BR><FONT FACE="Times New Roman,Times">clocks at 16Mhz, 8Mhz, and 2Mhz
(50% duty cycle for each of these clocks is</FONT>
<BR><FONT FACE="Times New Roman,Times">a design goal). If anyone has any
information regarding this issue please respond.</FONT><FONT FACE="Times New Roman,Times"></FONT>
<P><FONT FACE="Times New Roman,Times">P.S. If you know of any BANDX devices
which have this functionality also reply</FONT><FONT FACE="Times New Roman,Times"></FONT>
<P><FONT FACE="Times New Roman,Times">
Walter C. Washington</FONT></HTML>
--------------FCB6B052DC34F2E19AE61099--
Article: 8803The following is a collection of problems that I have had with not only version M1.4.12 (that I'm running now under NT in conjunction with WVOffice 7.4) but with several previous versions of XACT. 1. When the Viewlogic project data is stored on a Novell Network drive, the flow engine fails when trying to run hitop. All Xilinx binaries and license file are stored on a local drive. I was told by customer support (again) to copy the project onto a local drive and run it, and that Novell "is not a good network." This is unacceptable. We're a group of engineers and we share information over a network. Are we the only ones running data over a Novell net? 2. The DynaText documentation does not install correctly on a Network drive because the directory "usEnglish" has too many letters. I realize this is a shortcoming of the network, and since it is 1998, it should accept long names, but the reality is that it does not, and I had trouble once again with a piece of Xilinx software because of something small like that. 3. I cannot lock a pin onto a complemented NET on a .ucf file. Tried a "-" as I used to do with XACT: didn't work. Tried a "~" as done on Viewlogic netlists, and .ncd files!: Didn't work. Called customer support and was told to remove the ~ altogether, and that the software would find the net and recognize it as complemented: Guess what? Didn't work! Called back and explained the situation again, and after holding for a little while was told that this was a NEW problem and that it would have to be investigated. What is so unusual about complemented nets? Am I, again, the only one using them? I welcome any comments or guidance on how to solve the first or third "comments" Thanks for taking the time to read this, Marco RiveroArticle: 8804
============================================================================
CALL FOR PAPERS
The Sixth FPGA/PLD Design Conference & Exhibit
Pacifico Yokohama, Yokohama, Japan, June 24-26, 1998
============================================================================
SPONSORS | IMPORTANT DATES
*The Institute of Electronics, Information and | Submission: Feb 6,1998
Communication Engineers of Japan | Acceptance: Mar 17,1998
*Information Processing Society of Japan | Final version: May 8,1998
*Embassy of the United States of America (plan) |
*Semiconductor Industry Association (plan) |
*Distributers Association of Foreign |
Semiconductors (plan) |
*International Semiconductor Cooperation |
Center (plan) |
============================================================================
The Sixth FPGA/PLD Design Conference & Exhibit
Pacifico Yokohama, Yokohama, Japan, June 24-26, 1998
The "FPGA/PLD Design Conference & Exhibit" is the only conference and
exhibit on FPGA and PLD in Japan, which provides a forum to exchange
ideas and promote research on the fields of device technology, design
technology, EDA support tools, and applications for FPGA/PLD.
At the sixth conference and exhibit, we are planning to introduce more
practically technical information and leading edge technology trends
on "Devices, Designs, EDA tools, and Application for FPGA/PLD";
specially on the FPGA/PLD in the 21st century. To make more intensive
discussion possible on the current studies and the sprouting ideas,
the next conference will expand the number of user presentations and
tutorial sessions. For example subjects handled on these session is
such as FPGA/PLD device which enables entirely new functions,
developing "System on Chip" using IP, new design methodologies for
FPGA/PLD toward the 21st century, and killer applications for
FPGA/PLD.
We invite papers on the following topics and also welcome papers on
related fields, such as system LSI design, development, and
application. Papers on case studies of design or application
from industries are most welcome. We are looking forward to your
papers.
MAJOR TOPICS
* Device architectures
* Circuit design technology
* CAD/DA technology
* Development support technology with FPGA/PLD-compatible IP
* Developing System on chip with IP
* Compiler technology for embedded systems
* Emulation technology and rapid prototyping
* Hardware/Software codesign
* Reconfigurable computing
* Evolving hardwares
* All kinds of application using FPGA/PLD
* Other topics related to FPGA/PLD
PAPER SUBMISSION
Please send six (6) copies of extended abstract and the completed
application form to the address below. Your papers will be reviewed by
the program committee for selection. Besides technical contents, your
extended abstract is expected to contain a presentation outline
describing the background, goal, approaches, importance, and
originality. The extended abstract may not exceed four pages of A4
size papers, including the title, figures, and tables. Abstracts
exceeding four pages will not be accepted.
APPLICATION FORM
Fill in the application form with the title of the paper, name of
author(s), author(s) affiliation, abstract(about 100 words), and three
or less keywords, with the contact address of the
corresponding author; name, affiliation, postal code and address,
telephone number, FAX number, and E-mail address. We welcome
applications by E-mail or postal mail. Ask for application
forms(template) to the address below.
AWARD
Excellent papers will be awarded based on the decision made by the
program committee. The authors of excellent papers will be awarded at
the conference, and will be asked to give presentations at the special
session. Supplementary prizes will be also provided to the awarded
authors respectively. In addition, all applicants will receive a
three-day conference tickets for free.
SCHEDULE
* February 6, 1998(Friday): Deadline for submission of abstracts
and application forms
* March 17, 1998(Tuesday): Notification of acceptance
* May 8, 1998(Friday): Deadline for camera-ready papers
* June 24(Wed.)-26(Fri.), 1998: Conference
Send abstract/application forms or inquires to
Tetsuo HIRONAKA
Hiroshima City University
Ozukahigashi 3-4-1, Asaminami-ku, Hiroshima-shi, Hiroshima,
731-31, Japan
TEL:(082)830-1566 FAX:(082)830-1792
E-mail:hironaka@ce.hiroshima-u.ac.jp
ORGANIZERS/SPONSORS
Organizers: Execution committee of
The Sixth FPGA/PLD Design Conference & Exhibit
Sponsors: The Institute of Electronics, Information and
Communication Engineers (of Japan)
Information Processing Society of Japan
(plan) Embassy of the United States of America
(plan) Semiconductor Industry Association
(plan) Distributers Association of Foreign Semiconductors
(plan) International Semiconductor Cooperation Center
----------------------------------------------------------------------
Tetsuo HIRONAKA
Faculty of Computer Sciences Tel : +81-82-830-1566
Hiroshima City University Fax : +81-82-830-1792
Hiroshima, 731-31, JAPAN E-mail: hironaka@ce.hiroshima-cu.ac.jp
Article: 8805I believe you can compile an ABEL file in Synario and get out an AHDL output file. Ying ying@csua.berkeley.edu In article <34CD9B42.52C0@altatech.com>, Douglas L Datwyler <datwyler@altatech.com> wrote: >Does any one know of a RELIABLE ABEL to Altera-HDL conversion utility? > >Where is the FAQ for this news group? > >Thank you, > >Douglas L Datwyler >Alta Technology >datwyler@altatech.com -- ----------------------------------- http://www.csua.berkeley.edu/~yingArticle: 8806
CHAOS on the net and JINGLE OF COINS DEAR WEBMASTER; I am posting this message to your news group, because I see it as a general subject which disregarding your area of emphasis, may be interesting to some of your readers. Everyone is on the World wide web to promote an idea or view, Sell merchandises or receive some interesting information. In any case this information may be interesting and vital to promotion of their goal. I see it as a powerful general subject and can help anyone in any field including: Biology, sexology, mineralogy and so on . . If you still feel that I have intruded into your domain and therefore I am unwelcome, please send me one E-mail and mention it to me, In addition accept my full apology. If you are still mad, please send me a two-page E-mail and swear at me all the way to the bottom, and you may continue doing that until the end of 1998. Whatever you decide to do it is fine with me. If you approve this literature for posting, I am sure many of your readers will be glad that they have received access to it. NOW, LET'S READ ON. This news (search engine Loophole) may cause a chaos on the net, and make many, many rich. Millions of potential customers and prospects are looking for your product or idea on the major search engines, will they ever find it? You already have heard about changing your meta tags and your title, did it help you? Internet commerce is growing amazingly. Some merchants are ripping abundance and some precipitate without any possible financial result and with a heavy monthly bill. What is the difference between these two cases, When both are promoting or selling a same kind of merchandise or idea? The answer is simple; knowledge! It all comes to, knowing the right information and applying it effectively and smartly. There are some loopholes ( the way different search engines work) in the search engines and If you are involved in Internet commerce or planning to do so, This information can be the most powerful tool you will need and can make the difference between your success and failure. I have not seen it in any Internet book. Some professionals are aware of it but they are keeping it as a trade secret. If this information spread, it can cause a chaos on the Internet and search engines will be reevaluated. The first person equipped with it may rip abundance. It is simple but tremendously powerful. It will show you how to make your web page one of the top ones in the major search engine's list. I assume that you have read many books and pamphlets about this subject and all of them are pointing at changing your Title and Meta tags. Although those points are correct but none of them mentions all the points, or some of the most important secrets, therefore your effort may fail. Some writers may leave a point or two out intentionally, and for personnel gain, and some do not know about the whole tricks. *** This invitation will be seen by a handful of people randomly and the desperate, and the lucky one may knock. If you are interested to receive more information, please send us an E-mail with the phrase "more info" ( without quotation marks) in the subject area. Our reserved E-mail address is: wardog@denton.quik.com Thank you ****************************************************************** FREE SPEECH Congress shall make no law respecting an establishment of religion, or prohibiting the free exercise thereof, or abridging the freedom of speech, or of the press; or the right of the people peaceably to assemble, and to petition the Government for a redress of grievances. --- Amendment I, The US Constitution There are a few people on the Internet who complain whenever they received unsolicited mail. Many of these individuals are the same people who feel that the World Wide Web, Online Services and the Internet should have never been commercialized. These "computer hippies" resent the presence of businesses on the Internet. The vast majority of people appreciate short, informative messages about useful new products and/or services and do NOT want any "computer hippies" and immature nerds interfering with their ability to receive potentially valuable information on the Internet since that's what the Internet is supposed to be all about! Whether or not you like receiving E-mail, if you are a true American, then you will fight for anybody's right to do so. Most Americans and the vast majority of people on the Internet are opposed to imposed censorship in any form. We are continually amazed at how quickly people applaud the loss of their freedoms. Without freedom of speech, WE HAVE LOST EVERYTHING our society stands for. If you are irritated by unsolicited E-mails, JUST IGNORE THEM, THIS IS THE COST OF A FREE SOCIETY! PAY YOUR DUES! One thing that has to be said for E-mail over snail mail, is that no trees had to be cut down to send E-mail.Article: 8807
Knut Arne Vedaa wrote: > Hello, > > I'm going to implement ten 32-bits counters running at 20 MHz together > > with some logic to sequentially read the counters 8 bits at a time > from a microcontroller. > > I'm considering various PLDs for the task: Xilinx XC4006/XC4008, In Xilinx XC4000E or 'XL ( 3.3 V !) ten 32-bit counters take about 170 CLBs. That means, tightly packed they might fit into an XC4005, and they would use up only ten of the 18 columns in an XC4008. ( 55%) Lay-out or floorplanning is not an issue, since the carry structure forces the counter to be vertically aligned. Read-out and loading is then very easy through the horizontal Longlines and their 3-state drivers ( multiplexing for free ). You could pack 17 such counters ino the XC4008E or 'XL, and still have room for the read-out control. 20 MHz performance is trivial. And power consumption will be quite low, even at full speed. It's equivalent to 20 toggling flip-flops at 0.1 mW per MHz clock rate = 40 mW . Plus about 160 mW ( worst-case) global clock power @20 MHz., for a total of 200 mW = 40 mA at 5 V ( 100 mW for the 3.3-V solution). In SRAM-based FPGA you must not forget the clock power, since long counters consume very little power. ( Of course, a ripple-counter would eliminate almost all clock power...) In CPLDs you have much higher static power and you obviously need a device with 320 flip-flops, which is at or beyond their max capacity. Peter Alfke, Xilinx Applications Peter AlfkeArticle: 8808
--------------78A3F839266425CDF919972F Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Walter C. Washington wrote: > > > I wish to create a DIVIDE BY N(where N is any integer between 1 and > 32) clock generation circuit. The source input clock frequency is > 48Mhz and wish to produce > clocks at 16Mhz, 8Mhz, and 2Mhz (50% duty cycle for each of these > clocks is > a design goal). If anyone has any information regarding this issue > please respond. That's a trivial design. 28 years ago, I would have suggested two 74161's. Today you can do that in any programmable device worth its salt, including the lowliest PALs. You only need five flip-flops. Peter Alfke, Xilinx Applications --------------78A3F839266425CDF919972F Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <BODY BGCOLOR="#FFFFFF"> Walter C. Washington wrote: <BLOCKQUOTE TYPE=CITE> <P><FONT FACE="Times New Roman,Times">I wish to create a DIVIDE BY N(where N is any integer between 1 and 32) clock generation circuit. The source input clock frequency is 48Mhz and wish to produce</FONT> <BR><FONT FACE="Times New Roman,Times">clocks at 16Mhz, 8Mhz, and 2Mhz (50% duty cycle for each of these clocks is</FONT> <BR><FONT FACE="Times New Roman,Times">a design goal). If anyone has any information regarding this issue please respond.</FONT></BLOCKQUOTE> That's a trivial design. 28 years ago, I would have suggested two 74161's. Today you can do that in any programmable device worth its salt, including the lowliest PALs. You only need five flip-flops. <P>Peter Alfke, Xilinx Applications </BODY> </HTML> --------------78A3F839266425CDF919972F--Article: 8809
The Designer's Guide to VHDL by Peter Ashenden is the coolest book.. -- ~~~~~~~~~~~~~~~~~~~~ deepu@ece.vill.edu ~~~~~~~~~~~~~~~~~~~~~~~~~~~ | Deepu Talla | If it is not necessary to change | | | it is necessary not to change ... | | Phone: (610)225-0243 (R) | | | (610)519-7371 (O) | whatever, whoever, wherever, whenever| ~~~~~~~~~~~~~~~~ http://www.ece.vill.edu/~deepu ~~~~~~~~~~~~~~~~~~~Article: 8810
=======================================================================
CALL FOR PAPERS
The 19th IEEE Real-Time Systems Symposium
Madrid, Spain
December 2-4, 1998
Sponsored by The IEEE Computer Society Technical Committee on
Real-Time Systems
=======================================================================
SCOPE OF THE CONFERENCE
RTSS '98 will bring together a wide body of researchers and
developers, to advance the science and practice of real-time
computing. Papers on all aspects of real-time systems are welcome,
including (but not limited to) modeling and design methods, operating
systems, scheduling algorithms, databases, file systems, networks and
communications, programming languages, formal methods, architecture,
middleware and APIs, instrumentation, fault tolerance, software
engineering, performance analysis, embedded systems,
signal-processing, multimedia applications, process control, tool
support -- and a lot more. Of particular interest are case-study
reports on experimental results, from any core application area in
real-time systems.
=======================================================================
SUBMISSION GUIDELINES
Papers should describe original research (i.e., not published
elsewhere), and should not exceed 20 double-spaced pages (or
approximately 5000 words). All accepted submissions will appear in the
proceedings published by IEEE, with the committee recommending a
selection of the best papers for publication in a journal.
If possible, submissions should be made electronically, either in
postscript or PDF format. Additional details on submission guidelines
will be posted at the RTSS'98 Home Page:
http://www.cs.umd.edu/~rich/rtss98/
Electronic submissions are preferred; however postal submissions will
be accepted for review, provided they arrive by the Submission Deadline
of May 1, 1998. All authors taking this option should mail eight (8)
copies of their submitted papers to the Program Chair:
Richard Gerber Email: rich@cs.umd.edu
Department of Computer Science URL: www.cs.umd.edu/~rich
University of Maryland Phone: +1-301-405-2710
College Park, MD 20742 USA Fax: +1-301-405-6707
=======================================================================
IMPORTANT DATES
* May 1, 1998 -- Deadline for paper submissions
* July 25, 1998 -- Notification of acceptance
* September 1, 1998 -- Final paper due
* December 2-4, 1998 -- RTSS '98, Madrid, Spain
=======================================================================
EXHIBITION, WORKSHOP AND WORK-IN-PROGRESS SESSIONS
Exhibition and Show: RTSS '98 will include an industrial exhibition in
a centrally located space, for vendors to demonstrate state-of-the-art
systems, development tools and applications; where RTSS attendees can
engage in technical discussions with product engineers and developers;
and where company representatives meet (and potentially recruit) young
researchers specializing in real-time and embedded systems. To reserve
space for the exhibition, please contact the RTSS '98 Industrial
Chair, Dr. Alan Burns (burns@minster.cs.york.ac.uk).
Workshop: RTSS '98 will co-host a workshop on December 1, 1998,
directly before the conference. The focus of the workshop will be a
"hot topic" of special interest to researchers and developers of
real-time systems. Recent RTSS workshops were on topics such as
Middleware/APIs (1997) and Multimedia Systems (1996). More information
on the 1998 workshop topic will be announced shortly, and publicized
on the conference home page.
Work-in-Progress Session: As in previous years, RTSS '98 will include
a Work-In-Progress (WIP) session, featuring short presentations on new
and evolving work. Accepted WIP papers will be included in a special
proceedings, and distributed to RTSS'98 conference participants. The
proceedings will then be published electronically on the IEEE-CS
TC-RTS Home Page. WIP papers will be due approximately one month
before the Symposium.
=======================================================================
ORGANIZING COMMITTEE
General Chair: Kwei-Jay Lin, University of California, Irvine
Program Chair: Richard Gerber, University of Maryland
Finance Chair: Walt Heimerdinger, Honeywell Technology Center
Registration Chair: Linda Buss
Local Arrangements Chair: Angel Alvarez, Universidad Politecnica de Madrid
Local Treasurer: Juan A. de la Puente, Universidad Politecnica de Madrid
Publicity Co-Chairs:
Alejandro Alonso, Universidad Politicnica de Madrid (Europe)
Chao-Ju Jennifer Hou, Ohio State University (Americas)
Joseph Ng, Hong Kong Baptist University (Asia/Pacific)
Industrial Chair: Alan Burns, University of York
Ex-Officio: (RTS-TC Chair) Doug Locke, Lockheed Martin Corporation
=======================================================================
PROGRAM COMMITTEE
James Anderson (University of North Carolina)
Azer Bestavros (Boston University)
Sanjoy Baruah (University of Vermont)
Giorgio Butazzio (Scuola Superiore e Sant'Anna)
Gerhard Fohler (Malardalen University)
Michael Gonzalez Harbour (Universidad Cantabria)
Jeffrey Hollingsworth (University of Maryland)
Seongsoo Hong (Seoul National University)
Farnam Jahanian (University of Michigan)
Kevin Jeffay (University of North Carolina)
Hermann Kopetz (Vienna University of Technology)
Kim G. Larsen (Aalborg University)
Insup Lee (University of Pennsylvania)
Jane W.S. Liu (University of Illinois)
Keith Marzullo (University of California at San Diego)
Sang Lyul Min (Seoul National University)
Al Mok (University of Texas at Austin)
Ragunathan Rajkumar (Carnegie Mellon University)
Jennifer Rexford (AT&T Research)
Manas Saksena (Concordia University)
Bran Selic (ObjectTime, Ltd.)
Andy Wellings (University of York)
David Wilner (Wind River Systems)
Sergio Yovine (CNRS/VERIMAG)
Hui Zhang (Carnegie Mellon University)
=======================================================================
Article: 8811persons wishing to modify the Volume Serial Number may use the following process: re-boot in MS-DOS mode. (dos boxes can't write to the boot) DEBUG L 100 2 0 1 ; read a copy of the boot sector from #2 or C: D 100 ; dump 128 bytes, look for words FAT16 or FAT32 ( you can view the present serial number at the offsets listed below) ( W 100 0 5 1 ; write a copy to sector 5 of #0 or A: scratch floppy if you wish ) ( Later you can L 100 0 5 1 and W 100 2 0 1 to restore if you must ) E127 ; edit starting at byte CS:127 for FAT16 or FAT12 E143 ; edit starting at byte CS:143 for FAT32 ( enter desired serial number, in reverse byte order, follow each with <SPACE>) ( serial number 1234-5678 is entered as 78 56 34 12 ) W 100 2 0 1 ; write it back out notes: in a previous post in this ng, S.E.E. indicated difficulty with the FAT32 version, and had to format. S.E.E. placed his R/W buffer at 0x0 instead 0x100. this may have been the source of the problem, it has been customary to use 0x100, because the PSP and other things (stack) are placed below 0x100. it's not clear to me that these areas would be used by the L and W commands, though. my tests were successful with FAT12, FAT16, and FAT32 volumes. also, ? gives help in debug. regards to all xilinx M1 users. billArticle: 8812
The design has been synthesized by two different synthesis tools
(Synopsys design compiler, and Cadence Synergy). I even also tried
once with Synopsys FPGA-compiler.
The results are quite similar (only a few LE's difference at the end,
the number of FFs remain the same).
--
Koenraad SCHELFHOUT
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VH14 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 47 \ / /
mailto:ksch@sh.bel.alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
Article: 8813Knut Arne Vedaa wrote: > > Hello, > > I'm going to implement ten 32-bits counters running at 20 MHz together > with some logic to sequentially read the counters 8 bits at a time > from a microcontroller. > > I'm considering various PLDs for the task: Xilinx XC4006/XC4008, > Altera FLEX10K, Altera MAX9000, Atmel AT6000. > > I'd like to use the MAX9000 (EPM9560) because of its non-volatile ISP > feature, but I am unsure whether I will be able to fit the counters in > it. I am also unsure whether the counters will fit into the XC4006 or > XC4008 (this is an issue because Foundation only supports devices up > to XC4008). > > Since I am new to PLD technology, I would be happy to get some advice > on this. > > Thanks, > > Knut Arne Vedaa Also look at the ATMEL AT40K series. some notes - Wide counters fit better in TOGGLE FF's than D FF's - Counters alone consume 320 FF's, at the top end of CPLD Multiple CPLD may be another option. - READ is not trivial, if you want SYNC read, you'll need another 320 FF's, OR a SYNC load RAM, to capture the contents. - If you can tolerate Skew Read, a 10 wide MUX to 4 capture regs can suffice. - Metastable events between the READ and Count operations may also be a problem - is the uC BUS and 20MHz clock locked ? If you run at 20MHz, and read at nominal uC BUS rates, ( 1-3MHz ) Then a cascade capture system may be best - one set SYNC clocked at 20Mhz to capture / HOLD during READ, and the HOLD line synced from RDN, using metastable safe cascade FF's -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Many reusable object modules - i2c, SPI, SPL, RC5, etc = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55. OptoISP for 89S, AVR, AT17K. = for more info, mailto:DesignTools@xtra.co.nz Subject : c51ToolsArticle: 8814
Maybe it's just the way that I'm using it, but does anybody else out there think that 8.2 is a giant leap backwards from 8.1! For my project (60% full 10K50, 2 clocks 25 and 50 MHz) compile times have gone from about 0.5 hrs to about 3 hrs, cliques seem to be ignored, and I get 10 - 15 timing constraints not met (previously 5 not met). I'm just glad I can still use 8.1. -- Peter Rush. I speak for myself, not for Nortel.Article: 8815
knutarne.vedaa@hl.telia.no (Knut Arne Vedaa) wrote:
> I'm going to implement ten 32-bits counters running at 20 MHz together
> with some logic to sequentially read the counters 8 bits at a time
> from a microcontroller.
This could probably fit in a Lucent Orca 2C04 which is a 10x10 array
of PFUs (4-bit function blocks). Each counter would take 8 blocks an
leave 20 blocks for CPU interface and counter controls. Readout would
use the internal tri-state busses. These chips sell for ~$10.
On the off chance that the counters are all mutually exclusive (i.e.
only one counter will count per 50ns cycle, for example if you were
counting memory page hits or keeping statistics on a data stream) then
the whole thing could probably fit in about 25 PFU.
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8816Thomas, Maxplus II does allow timing driven compilation. If one chooses Global Project Timing Requirements, one can specify Tpd, Tsu, Tco and/or Fmax for the whole device. If one chooses Timing Requirements, one can specify the same parameters to individual nodes. -Simon Ramirez Consultant at COMSAT RSI, Orlando, FL 407-888-0050, extension 17 s_ramirez@msn.com Thomas Rock wrote in message ... >Here's my two cents worth: > >I've been consulting with a company for the past year now implementing >a several designs in Xilinx (4062) and Altera (10K70) components. Below >are several observances the design group has made relating to the pluses >and minuses of the respective parts and tools: > >1) Although according to the gate-count specs, the parts would appear to >be similar in capabilities, we found that a 70% full Xilinx part held >about 40% more logic than a 70% full Altera, for these particular >designs. > >2) The place and route times for Xilinx ran between 24 hours (68% full) >and 53 hours (70% full). It seemed odd that a relatively small change in >logic produced such a large change in place and route time. > >3) The place and route for Altera took approximately 1 1/2 hours (but see >item #4). A small change in utilization did not seem to make a large >impact in the place and route times. > >4) The Altera Maxplus II tool is not a timing driven tool. It is up to >the designer to manually create 'cliques' (i.e. groups) of registers. The >tool then places the registers in proximity to each other to reduce prop >delay. There are no provisions to tell the tool that a certain path has >lots of slack so that parts may be spread out. We found that doing a lot >of synthesis timing optimization was a waste of time because Maxplus II >would re-optimize things its own (twisted) way. Obviously, Maxplus II was >our biggest gripe with Altera. The Xilinx M1 tool, on the other hand, is >timing driven and did not require any manual intervention. > >5) The Altera FPGA's do not support internal tri-state buffers as does >Xilinx. They also implement combinational muxes poorly, as does Xilinx >(but tri-state buses in Xilinx make good muxes if the muxes are big). > >6) The RAM's within Xilinx are small, many and scattered throughout the >array. The Altera RAM's are large and few. So, if you have a lot of small >RAM's, Altera is probably not a good choice. Xilinx clocked RAM's also >seemed more usable for our particular application than did the Altera. > >7) In our application, the Altera parts ran noticeably hotter on the >board than the Xilinx (sorry - I don't have actual temperature data). >System clock was 33 MHz. > >8) Another irritating quirk of the Altera parts that we found was that >any unused I/O pins defaulted to *outputs*. We had designed the board >with extra connections from the board processor to the FPGA "just in >case". Since these 'unused' I/O defaulted to outputs, it caused the >processor to hang up royally. We needed to tell Maxplus that these pins >were inputs. The Xilinx M1 tool defaults unused I/O to inputs. > >9) Our particular design had several 'versions' (i.e. we left off some >functionality). We made one full-up design (VHDL) then, during synthesis, >deleted the parts we didn't want for that particular version. This caused >some hierarchical output ports to not be connected. This caused Maxplus >II to choke (i.e. it quit with an error message). Xilinx M1 had no >problem with it. This problem was reported to Altera customer support. > >10) We had a difficult time meeting timing on what should have been >simple counters within Maxplus. The FAE suggested that we change our >general VHDL counters to the Maxplus parameterized models to improve the >place and route process. This went against our desire to maintain general >VHDL code that could be more easily ported to an ASIC or other FPGA >technology. > >11) We found that hand-editing a Xilinx routed design was pretty easy and >straight-forward. We did not find Maxplus II to be a reasonable tool to >manually edit a layout. However, we only performed hand-routes on the >Xilinx because we didn't want to wait 1 to 2 days for an auto-route to >complete. > >To answer the first question, we performed a gate-count analysis of our >design and concluded, using the equivalent gate-count numbers from the >Altera data sheet, that it should fit in a 10K70 with room to grow. In >actuality, it turned out that less than half of the design fit. We >estimate that we got about 30K gates into the thing. We ended up putting >about 40% of the logic in the 10k70 (about 70% utilized) and the >remainder in a Xilinx 4062 (about 68% utilized). This is how we obtained >lots of side-by-side comparisons of the components. Disclaimer: These >utilization figures are based solely on our particular design. Your >mileage may vary. > >Hope this helps. > >Tom > > > >[This followup was posted to comp.lang.vhdl and a copy was sent to the >cited author.] > >In article <34C7E444.1970@ti.com>, gurrapu@ti.com says... >> Hello. >> >> Couple of days back I posted an article reagrding what device to use: >> Altera vs Xilinx. Our design requirement is a 2K-byte Sync RAM and >> approximately 22K gate-logic. >> >> I have almost decided to use 10K100 part which has 12 EABS, eight of >> which can be used for implementing the RAM. The remaining EABs and the >> 624 LABs will give me approximately 62K available gates. >> >> *) The data sheet says 10K100 has 62K-158K gates available. I never >> understood this.... If all EABs are used as memory, it gives me 24K >> gates and from 624 LABs, I get ~62K and hence, 86K.. Minimum is ~62K >> which is correct. Can somebody explain the maximum limit? >> *) However, can somebody tell me how to choode a device based on the >> gate count required? In other words, how much fetch factor we need to >> allow for FPGAs/ EPLDs. >> Can somebody share their experince in Xlinx and Altera devices? >> >> One more thing I'm concerned is our design has some blocks operating >> at 48 MHz. Is that Ok in Altera devices? What'd be the practical max CLK >> for altera devices assuming that I've all i/ps and o/ps registered. >> >> Thanks and regards, >> >> -- >> Srikanth Gurrapu, >> Texas Instruments, Inc. >> >> Ph: (972)-480-2318 (o) (972)889-9678 (h) >> Fax: (972)-480-2264 >> Email: gurrapu@ti.com >> >-- >Thomas Rock >thomas@x-tekcorp.comArticle: 8817
In comp.arch.fpga, Simon Ramirez wrote:
> Thomas,
> Maxplus II does allow timing driven compilation. If one chooses Global
> Project Timing Requirements, one can specify Tpd, Tsu, Tco and/or Fmax for
> the whole device. If one chooses Timing Requirements, one can specify the
> same parameters to individual nodes.
I've played with Global Project Timing Requirements and the optimize
for speed parameter in the Global Project Logic Synthesis menu.
Neither one seemed to have a perceivable affect on Fmax for my design.
The only way I could get good performance was to design my circuit so
it could be easily partitioned into Altera's cliques, or placed into
specific rows inside the floorplanner.
--
Greg Sajdak
Without question, the greatest invention in the history of mankind is
beer. Oh, I grant you that the wheel was also a fine invention, but
the wheel does not go nearly as well with pizza.
--Dave Barry
Article: 8818Koenraad Schelfhout VH14 8993 wrote: > The design has been synthesized by two different synthesis tools > (Synopsys design compiler, and Cadence Synergy). I even also tried > once with Synopsys FPGA-compiler. > The results are quite similar (only a few LE's difference at the end, > the number of FFs remain the same). > Cadence Synergy is being replaced with Synplicity's Synplify.Give that a try. I would be surprised if your combinatorial logic did not decrease by 30-40%. (The flip flops SHOULD always be the same from all vendors. -- Charles F. Shelor charles@efficient.com Efficient Networks, Inc 'ATM for the Desktop' 4201 Spring Valley, Suite 1200 http://www.efficient.com/ Dallas, TX 75244 (972) 991-3884Article: 8819
Thomas,
I like what you said here. It is basically very objective and I can tell
it is based on experience.
I agree with you on the Xilinx gate-count vs. Altera gate-count. Xilinx
is conservative and Altera is inflated.
I personally like the Altera MaxPlus II software for design. I think
that the simulator is much more tightly coupled, and simulation takes upa
significant percentage of the design time.
There are several other features that I like about Xilinx vs. Altera
silicon. First, the 4K family, while configuring, has weak pull ups,
whereas the 10K family is tri-stated. This means that Xilinx outputs are
weakly defined during configuration, which is good. This is significant to
me because the configuration time is relatively long (tens or hundreds of
milliseconds) and meanwhile, RAMs and other structures can be turned on and
contending on buses. This could cause a reliability problem.
Second, Xilinx IOB flip flops have both clears and presets, while Altera
IOE flip flops only have clears. This becomes an issue at power on for
signals that are active low outputs. They are normally preset to high at at
reset time, so the flip flop that outputs this signal winds up in the core,
not at an IOE. This in turn affects clock to output timing.
Third, Xilinx CLBs can be converted to Dual Port or Single Port RAMs,
whereas Altera EABs are only Single Port RAMs. This becomes significant
when doing FIFOs and other structures.
Along with wide decodes and internal tri-states, which are useful for
making muxes and other structures, I think that Xilinx 4K silicon is
superior to Altera 10K silicon, but I will limit this comparison to the 4K
XL family, which has pretty good routing resources. Previous 4K families
aren't as gifted and consequently, don't route as well.
So now you know that I prefer Xilinx silicon and Altera software.
One other thing comes to mind. A while back I contacted Xilinx to tell
them how I was going to approach my design using Xilinx silicon and
software. The tech support guy said that my approach would result in
relatively poor performance, because I was using totally a VHDL design. He
said that the general feeling at Xilinx was that schematic based design was
the best way to go in order to achieve my performance goals. I told him
that I was strictly a VHDL code designer and had been for a while. We left
it at that, but I was left wondering if my VHDL design entry method was
going to achieve my performance goals.
As it turns out, it did very well. I had to achieve a 37 MHz design
(which he knew), and the part came in at over 50 MHz! In retrospect, I
believe that he was making comparisons based on using Metamor, which is the
tool that Xilinx ships with their Foundation Series package. While the
Metamor is a good tool for small designs, it doesn't do very well with large
designs (greater than 10K 4K Xilinx gates). My approach has been to use
Synplify, a synthesizer made by Synplicity. I have found that this
synthesizer works very well for both Altera and Xilinx. In the end, my VHDL
design, which had 9 components in it that made extensive use of RAM16X1D and
RAM32X1S blocks, along with the usual state machines and address decoding,
fit into an XC4013XL device and I was able to drop down in speed grades to
achieve the 37 MHz with lots of performance margin (12 MHz) and cost saving.
If you consider this advice, it is free and worth every penny!
-Simon Ramirez
Consultant at COMSAT RSI, Orlando, FL
407-888-0050, extension 17
s_ramirez@msn.com
Thomas Rock wrote in message ...
>Here's my two cents worth:
>
>I've been consulting with a company for the past year now implementing
>a several designs in Xilinx (4062) and Altera (10K70) components. Below
>are several observances the design group has made relating to the pluses
>and minuses of the respective parts and tools:
>
>1) Although according to the gate-count specs, the parts would appear to
>be similar in capabilities, we found that a 70% full Xilinx part held
>about 40% more logic than a 70% full Altera, for these particular
>designs.
>
>2) The place and route times for Xilinx ran between 24 hours (68% full)
>and 53 hours (70% full). It seemed odd that a relatively small change in
>logic produced such a large change in place and route time.
>
>3) The place and route for Altera took approximately 1 1/2 hours (but see
>item #4). A small change in utilization did not seem to make a large
>impact in the place and route times.
>
>4) The Altera Maxplus II tool is not a timing driven tool. It is up to
>the designer to manually create 'cliques' (i.e. groups) of registers. The
>tool then places the registers in proximity to each other to reduce prop
>delay. There are no provisions to tell the tool that a certain path has
>lots of slack so that parts may be spread out. We found that doing a lot
>of synthesis timing optimization was a waste of time because Maxplus II
>would re-optimize things its own (twisted) way. Obviously, Maxplus II was
>our biggest gripe with Altera. The Xilinx M1 tool, on the other hand, is
>timing driven and did not require any manual intervention.
>
>5) The Altera FPGA's do not support internal tri-state buffers as does
>Xilinx. They also implement combinational muxes poorly, as does Xilinx
>(but tri-state buses in Xilinx make good muxes if the muxes are big).
>
>6) The RAM's within Xilinx are small, many and scattered throughout the
>array. The Altera RAM's are large and few. So, if you have a lot of small
>RAM's, Altera is probably not a good choice. Xilinx clocked RAM's also
>seemed more usable for our particular application than did the Altera.
>
>7) In our application, the Altera parts ran noticeably hotter on the
>board than the Xilinx (sorry - I don't have actual temperature data).
>System clock was 33 MHz.
>
>8) Another irritating quirk of the Altera parts that we found was that
>any unused I/O pins defaulted to *outputs*. We had designed the board
>with extra connections from the board processor to the FPGA "just in
>case". Since these 'unused' I/O defaulted to outputs, it caused the
>processor to hang up royally. We needed to tell Maxplus that these pins
>were inputs. The Xilinx M1 tool defaults unused I/O to inputs.
>
>9) Our particular design had several 'versions' (i.e. we left off some
>functionality). We made one full-up design (VHDL) then, during synthesis,
>deleted the parts we didn't want for that particular version. This caused
>some hierarchical output ports to not be connected. This caused Maxplus
>II to choke (i.e. it quit with an error message). Xilinx M1 had no
>problem with it. This problem was reported to Altera customer support.
>
>10) We had a difficult time meeting timing on what should have been
>simple counters within Maxplus. The FAE suggested that we change our
>general VHDL counters to the Maxplus parameterized models to improve the
>place and route process. This went against our desire to maintain general
>VHDL code that could be more easily ported to an ASIC or other FPGA
>technology.
>
>11) We found that hand-editing a Xilinx routed design was pretty easy and
>straight-forward. We did not find Maxplus II to be a reasonable tool to
>manually edit a layout. However, we only performed hand-routes on the
>Xilinx because we didn't want to wait 1 to 2 days for an auto-route to
>complete.
>
>To answer the first question, we performed a gate-count analysis of our
>design and concluded, using the equivalent gate-count numbers from the
>Altera data sheet, that it should fit in a 10K70 with room to grow. In
>actuality, it turned out that less than half of the design fit. We
>estimate that we got about 30K gates into the thing. We ended up putting
>about 40% of the logic in the 10k70 (about 70% utilized) and the
>remainder in a Xilinx 4062 (about 68% utilized). This is how we obtained
>lots of side-by-side comparisons of the components. Disclaimer: These
>utilization figures are based solely on our particular design. Your
>mileage may vary.
>
>Hope this helps.
>
>Tom
>
>
>
>[This followup was posted to comp.lang.vhdl and a copy was sent to the
>cited author.]
>
>In article <34C7E444.1970@ti.com>, gurrapu@ti.com says...
>> Hello.
>>
>> Couple of days back I posted an article reagrding what device to use:
>> Altera vs Xilinx. Our design requirement is a 2K-byte Sync RAM and
>> approximately 22K gate-logic.
>>
>> I have almost decided to use 10K100 part which has 12 EABS, eight of
>> which can be used for implementing the RAM. The remaining EABs and the
>> 624 LABs will give me approximately 62K available gates.
>>
>> *) The data sheet says 10K100 has 62K-158K gates available. I never
>> understood this.... If all EABs are used as memory, it gives me 24K
>> gates and from 624 LABs, I get ~62K and hence, 86K.. Minimum is ~62K
>> which is correct. Can somebody explain the maximum limit?
>> *) However, can somebody tell me how to choode a device based on the
>> gate count required? In other words, how much fetch factor we need to
>> allow for FPGAs/ EPLDs.
>> Can somebody share their experince in Xlinx and Altera devices?
>>
>> One more thing I'm concerned is our design has some blocks operating
>> at 48 MHz. Is that Ok in Altera devices? What'd be the practical max CLK
>> for altera devices assuming that I've all i/ps and o/ps registered.
>>
>> Thanks and regards,
>>
>> --
>> Srikanth Gurrapu,
>> Texas Instruments, Inc.
>>
>> Ph: (972)-480-2318 (o) (972)889-9678 (h)
>> Fax: (972)-480-2264
>> Email: gurrapu@ti.com
>>
>--
>Thomas Rock
>thomas@x-tekcorp.com
Article: 8820Check out the xilinx web site ... I think I saw something about this problem (and a solution?) there ... markArticle: 8821
Intro: ****** I design a PCI board. And on my board, I have a XC4008E (to control the PCI interface ) with an AT17CXXX Atmel EEPROM to download this interface FPGA at the power ON of the PC. I must make an In-System Programming: I must (to load new caracteristics configuration of the interface FPGA) , programm new data in the EEPROM via a software PC and the interface FPGA. I work directely with a 8 bit register [ CE/ ; RESET/OE/ ; DATA ; SER_EN/ ; SCLK ] and I will programm this register to run the serial data timing to the EEPROM. I must use a file.exo (EXORmacs format) to programm the new data in the EEPROM. example: -------------- my file.exo form is --Start of file S1130000FF4F406196FF7FF9FFF7EFDBFFDBBF6F28 S1130010FF6FFFBEFDBFFDFBF6FFF6EFDBFFDBBFAF S11300206FFF6FFFBEFDBFFDFBF6FFF6EFDBFFDBEF S11300303FFAF6FFF6EFDBFFDBBF6FFF6FFFBEFD9E S1130040BFFDFBF6FFF6EFDBFFDBBF6FFF6FFFBE0D S1130050FDBFFDFBF6FFF6FFFFFFFFFCFFFFFF7F89 -- -- ... -- S11350A03FFDFBF4FFF6FFFFFF42F8FFFFFF7FFF2A S11350B0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC S11150C0FFFFFFFFFFFFFFFFFFFFFFFFFFFFEC S9030000FC --End of file I have downloaded the ' Programming Specification for Atmel's FPGA Configuration E2PROMs AT17C65/128/256/512/010 ' application note on the atmel WEB site. Questions: ************ How use the file.exo (where are 'Device address', '1st address byte ... in my file.exo ?) ? Have you a software example to programm an AT17CXXX with a file.exo (or with an other format) ? Give me a feedback. Thank you for your help. Laurent GauchArticle: 8822
Intro: ****** I design a PCI board. And on my board, I have a XC4008E (to control the PCI interface ) with an AT17CXXX Atmel EEPROM to download this interface FPGA at the power ON of the PC. I must make an In-System Programming: I must (to load new caracteristics configuration of the interface FPGA) , programm new data in the EEPROM via a software PC and the interface FPGA. I work directely with a 8 bit register [ CE/ ; RESET/OE/ ; DATA ; SER_EN/ ; SCLK ] and I will programm this register to run the serial data timing to the EEPROM. I must use a file.exo (EXORmacs format) to programm the new data in the EEPROM. example: -------------- my file.exo form is --Start of file S1130000FF4F406196FF7FF9FFF7EFDBFFDBBF6F28 S1130010FF6FFFBEFDBFFDFBF6FFF6EFDBFFDBBFAF S11300206FFF6FFFBEFDBFFDFBF6FFF6EFDBFFDBEF S11300303FFAF6FFF6EFDBFFDBBF6FFF6FFFBEFD9E S1130040BFFDFBF6FFF6EFDBFFDBBF6FFF6FFFBE0D S1130050FDBFFDFBF6FFF6FFFFFFFFFCFFFFFF7F89 -- -- ... -- S11350A03FFDFBF4FFF6FFFFFF42F8FFFFFF7FFF2A S11350B0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC S11150C0FFFFFFFFFFFFFFFFFFFFFFFFFFFFEC S9030000FC --End of file I have downloaded the ' Programming Specification for Atmel's FPGA Configuration E2PROMs AT17C65/128/256/512/010 ' application note on the atmel WEB site. Questions: ************ How use the file.exo (where are 'Device address', '1st address byte ... in my file.exo ?) ? Have you a software example to programm an AT17CXXX with a file.exo (or with an other format) ? Give me a feedback. Thank you for your help. Laurent GauchArticle: 8823
hMETIS: A Package for Partitioning Circuits & Hypergraphs
---------------------------------------------------------
We would like to announce the release of hMETIS (version 1.0), a software
package that can be used for circuit and hypergraph partitioning.
hMETIS is a set of programs that implement various hypergraph partitioning
algorithms that are based on the multilevel paradigm.
The advantages of hMETIS compared to other circuit partitioning algorithms
are the following:
- Provides high quality partitions
The partitions produced by hMETIS are consistently 10% to 300% better than
those produced by other popular algorithms such as FM, KL, PARABOLI, PROP,
and CLIP-PROP, especially for circuits with over 100,000 cells, and circuits
with non-unit cell area.
- It is extremely fast
A single run of hMETIS is faster than a single run of simpler schemes
such as FM, KL, and CLIP. Furthermore, because of its very good average
cut characteristics, it can produce high quality partitionings in
significantly fewer runs.
Obtaining hMETIS
----------------
hMETIS is freely distributed. Information on how to get the package
is available on WWW at:
URL: http://www.cs.umn.edu/~metis
hMETIS has been written by George Karypis, at the Computer Science
Department of the University of Minnesota. If you have any questions or
problems obtaining hMETIS, send email to metis@cs.umn.edu.
hMETIS is copyrighted by the Regents of the University of Minnesota.
-------------------------------------------------------------------------------
Article: 8824Simon Ramirez (s_ramirez@email.msn.com) wrote: : One other thing comes to mind. A while back I contacted Xilinx to tell : them how I was going to approach my design using Xilinx silicon and : software. The tech support guy said that my approach would result in : relatively poor performance, because I was using totally a VHDL design. He : said that the general feeling at Xilinx was that schematic based design was : the best way to go in order to achieve my performance goals. I told him : that I was strictly a VHDL code designer and had been for a while. We left : it at that, but I was left wondering if my VHDL design entry method was : going to achieve my performance goals. I am not sure there is a big difference. You *can* do in VHDL absolutely the same design that you do in schematic (i.e. write a netlist). The only difference is that VHDL will be more portable and easier to simulate. OTOH, you will need a schematic to understand what you wrote in VHDL. So-called "behavioral" VHDL description comes down to 2-3 sequential statements that the synthesis tool is able to understand (and each vendor interprets them in a different way). No big deal. Sometimes I do use behavioral description, but usually I prefer netlist and para- metrized libraries (XBLOX or LPM). Normally there is no difference in performance between this type of design and schematic. George.
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