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[ Editor's Note: I just got this note (bellow) that registration for SNUG'98
is now open. In reading it, it appears that Synopsys doesn't want non-web
connected engineers going to SNUG'98. Even if you wanted to FAX or register
on the phone by talking to a real, live human or even use good old fashioned
U.S. snail mail -- you're required to start with a web form! :^) - John ]
NOTE: SNUG'98 is held for 3 full days this year!
DATE: March 11th-13th, 1998.
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Legal Disclaimer: "As always, anything said here is only opinion."
Article: 8751Austin Franklin wrote: > > > hmmm ... perhaps you should change manufacturers? ;^) but seriously, i've > > done 1 pci target and, well, not the most trivial circuit. > > Er, if you did a PCI interface in an Actel part....it wasn't PCI > compliant. As far as I know, Actel does not meet all PCI > requirements....you need to use two pins for one signal, and that is > illegal in PCI land. > > Also, you HAD TO lock your PCI I/O pins, or you couldn't have hoped in a > million years to be PCI compliant (no crossed signals, one via per > max...1.5" max length...). > > Also, did you take into consideration the /STOP-/FRAME Intel chip set > bug? It requires 5 raw /FRAME destinations....though it is NOT part of > the PCI spec, in order to work in the real world, you need to implement > it... > > Austin > > P.S. Do you really use Actel parts? Kind of like driving a Mustang II > ;-) You see a few of them every now and then....not enough to take them > seriously, but just enough to let you know they are still out > there....somewhere..for some reason (though that reason escapes me ;-). I must disagree with you. I have designed PCI using Actel ACT3 . They have and are fully compliant to PCI. Low power and security are important to me and I can the pack 90+ % while locking the pins. Their new MX family is also pretty good. So they are out there and making their name. I am quite happy. If you have a chance, look at their new MX devices.Article: 8752
Just got back from Altera training so I think I can explain their gate counting method. In a 10k100 you have 12 EABs, each of them containing 2048bits. Altera considers each bit equivalent to 4 gates when used for logic. EABs = 12 * 2048 * 4 = 98304 gates Each LAB contains 8 LEs. Altera considers each LE equvalent to 12 gates. LABs = 624 * 8 * 12 = 59904 gates Assuming everything is used for logic this gives the maximum number of ~158,000 gates. The mininum number assumes that no RAM is used for logic ==> ~62,000 gates. As for the speed question ... I hope they will run that fast ... I'm just starting my first Altera design and it will need to operate at 50Mhz. I have done Xilinx designs which run at 50Mhz, but you must be VERY, VERY careful. Hopefully the Altera tools will make this an easier target to reach. mark Srikanth Gurrapu <gurrapu@ti.com> wrote in article <34C7E444.1970@ti.com>... > Hello. > > Couple of days back I posted an article reagrding what device to use: > Altera vs Xilinx. Our design requirement is a 2K-byte Sync RAM and > approximately 22K gate-logic. > > I have almost decided to use 10K100 part which has 12 EABS, eight of > which can be used for implementing the RAM. The remaining EABs and the > 624 LABs will give me approximately 62K available gates. > > *) The data sheet says 10K100 has 62K-158K gates available. I never > understood this.... If all EABs are used as memory, it gives me 24K > gates and from 624 LABs, I get ~62K and hence, 86K.. Minimum is ~62K > which is correct. Can somebody explain the maximum limit? > > *) However, can somebody tell me how to choode a device based on the > gate count required? In other words, how much fetch factor we need to > allow for FPGAs/ EPLDs. > Can somebody share their experince in Xlinx and Altera devices? > > One more thing I'm concerned is our design has some blocks operating > at 48 MHz. Is that Ok in Altera devices? What'd be the practical max CLK > for altera devices assuming that I've all i/ps and o/ps registered. > > Thanks and regards, > > -- > Srikanth Gurrapu, > Texas Instruments, Inc. > > Ph: (972)-480-2318 (o) (972)889-9678 (h) > Fax: (972)-480-2264 > Email: gurrapu@ti.com >Article: 8753
Just got my M1.4 (Alliance) software today and I was quite surprised to see that version 7.4 of WVOffice is required. I have been using M1.3 along with WVOffice 7.31 for some time and was looking forward to M1.4 so I could get rid of the XACT software (required for 3K and 5K designs with M1.3) and free up some disk space. It now looks like I will either have to a) shell out even more $$$ to get WVOffice 7.4 or b) stay with the M1.3 tools. Does anyone else have the same problem? Any ideas what might happen if I try to use WVOffice 7.31 with Xilinx M1.4? Thanks, markArticle: 8754
"COMMERCIAL ALERT" http://sps.motorola.com/fpaa Programmable Analog (yes analog) http://sps.motorola.com/fpga Programmable Digital ...we now return you to the regularly scheduled program.... Daniel Lang wrote: > > In article <34C12FFB.6F6B@cyberjunkie.com>, XenoPhantom@cyberjunkie.com writes... > >Yes, after taking a look at the prices, I think I will reconsider FPGA, > >PLD, etc. The thing is, I wanted to integrate some analog circuitry in > >the system, so programmable logic will not allow that. > > > >So, any more ideas? Still if someone has the key to ASICs, please let me > >know. I'm not talking about REALLY cheap, I mean anything reasonable, > >say within $400 or something. In fact, if there are any companies > >willing to make just one ASIC, whatever the price, tell me about them. > > > >Hesham M Wahby > >Computer Engineering > >Cairo University > > > > As someone else mentioned, an ASIC will run $40,000 and up due to > NRE charges. I do not know of any user programmable chips that > combine digital and analog on one chip but IMP makes an EPAC > programmable analog IC. Digi-Key (www.digikey.com) sells an > EPAC device development starter kit for $256. > > Lattice and Cypress make low cost digital CPLD development > software ($99 or so). You may also be able to get a low cost > digital CPLD/FPGA development kit with a CPLD/FPGA on a PC/AT > board with digital I/O connectors. You would then have to make > a daughterboard with the analog components. > > I trimmed some of the newsgroups and added comp.arch.fpga which > deals with FPGA software. > > Daniel Lang dbl@anemos.caltech.edu -- Doug Shade rxjf20@email.sps.mot.com Motorola MPA Field Programmable Gate Arrays Customer and Applications SupportArticle: 8755
Sorry, I missed the original posting, but . . . Daniel Lang wrote in message <19JAN199801494087@hydra1.tyrvos.caltech.edu>... >In article <34C12FFB.6F6B@cyberjunkie.com>, XenoPhantom@cyberjunkie.com writes... >>Yes, after taking a look at the prices, I think I will reconsider FPGA, >>PLD, etc. The thing is, I wanted to integrate some analog circuitry in >>the system, so programmable logic will not allow that. There are (were) two programmable analog "FPGA"s on the market, one sold by IMP (which seems to have left the market) and the other sold by Motorola (see http://www.optimagic.com/companies.html#Analog). You can mix and match purely digital FPGAs and some analog FPGAs to give you a mix of technologies. >> >>So, any more ideas? Still if someone has the key to ASICs, please let me >>know. I'm not talking about REALLY cheap, I mean anything reasonable, >>say within $400 or something. In fact, if there are any companies >>willing to make just one ASIC, whatever the price, tell me about them. >> There are some companies willing to do small volumes of devices. However, you will have a fairly hefty NRE charge up front. If you amortize it into your parts cost, you won't find anything in the $400 for one unit category. Programmable logic, despite its warts, makes a lot of sense, especially for low volume applications. If you don't want to spend much on software, check out http://www.optimagic.com/lowcost.html for a list of free or low-cost, downloadable design packages. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com -----------------------------------------------------------Article: 8756
John Chambers wrote in message <34C73882.4D6D@ihr.mrc.ac.uk>...
>I would like to port some simple PC ISA cards I have designed to the PCI
>bus. My first requirement will be to port a simple 16bit data I/O card
>- trivial on the ISA bus but not on the PCI I think. Can anyone
>recommend an FPGA and associated library that could enable me to get
>this done with the minimum of effort. Any book references would also be
>appriciated
>
> John
IMHO, the simplest implementation is probably a PLX PCI chipset plus some
FPGA or CPLD logic for the interface. If you want a fully-integrated
solution, here are some recommendations.
Recommended book: PCI SYSTEM ARCHITECTURE
Tom Shanley/Don Anderson
Available on Amazon.com at:
http://www.amazon.com/exec/obidos/ISBN=0201409933/6258-9779338-803719
Recommended FPGA: Xilinx XC4000XLT FPGA Family
( http://www.xilinx.com/spot/pci32_20.htm )
Recommended PCI core: Xilinx LogiCORE PCI Interface
( http://www.xilinx.com/spot/pci32_20.htm )
Other Solutions:
Altera: http://www.altera.com/html/programs/ta_pci.html
Lucent: http://www.lucent.com/micro/fpga/master.html
Actel: http://www.actel.com/products/pci/pcisolution.html
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail: sknapp@optimagic.com
Web: http://www.optimagic.com
-----------------------------------------------------------
Article: 8757
>>>>> "SG" == Srikanth Gurrapu <gurrapu@ti.com> writes:
In article <34C7E444.1970@ti.com> Srikanth Gurrapu <gurrapu@ti.com> writes:
SG> Hello. Couple of days back I posted an article reagrding what
SG> device to use: Altera vs Xilinx. Our design requirement is a
SG> 2K-byte Sync RAM and approximately 22K gate-logic.
SG> I have almost decided to use 10K100 part which has 12 EABS,
SG> eight of which can be used for implementing the RAM. The
SG> remaining EABs and the 624 LABs will give me approximately 62K
SG> available gates.
Why the rush to pick a specific vendor or part so early in your design
process?
Get coding and when you have a good chunk of it completed
(enough such that architecturally it will be representative of your
final design) fire the design off to your FAEs. Work with the FAEs
to see which part from which vendor gets you closest to meeting
your speed / area(aka cost) requirements. At this point you'll
have a much better feel for which part is best suited to your design.
Feed your decision about part and package type into Layout and then
continue on to complete the rest of your coding, simulations, and
final synthesis, place and route. ...and re-coding...re-simulation...
re-sythesis...re-place...and re-route...and re-coding...
Be careful to structure the memory models in your design such that you
can re-target to XLNX or ALTR easily. Don't worry about using tri-states
since the ALTR tools will turn them into muxes automagically. Initially,
don't bother using any vendor specific device features (eg. wide
edge decoders), but once you finally do pick a vender/part go ahead and
start using vendor specific optimizations if you must.
just my $0.02 ...
--
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David J. Evans | | email::djevans@spamnotnortel.ca (del spamnot)
H/W Design Engineer | | phone::esn393.6742
Magellan Passport | | fax > /dev/null
ATM Hardware | | nortel.say != me.say
Article: 8758M1.4 will work fine with VL 7.3.1. One of my clients spotted this requirement in the docs, and put his new M1.4 on the shelf. When I asked why, he showed me the docs. I called X, and had an email response by the next day that M1.4 will work with VL 7.3.1 Also, if you have the Xilinx OEM version of VL (i.e. bought VL from X), package DS-VLS-STD-PC1, and are currently under maintainance, Xilinx will be shipping VL 7.4 by the end of Feb. Enjoy, Philip In article <01bd284c$7a1d2d80$6728dc26@default> "feydo" <feydo@lcworkshop.com> writes: >Just got my M1.4 (Alliance) software today and I was quite surprised to see >that version 7.4 of WVOffice is required. I have been using M1.3 along >with WVOffice 7.31 for some time and was looking forward to M1.4 so I could >get rid of the XACT software (required for 3K and 5K designs with M1.3) and >free up some disk space. It now looks like I will either have to a) shell >out even more $$$ to get WVOffice 7.4 or b) stay with the M1.3 tools. > >Does anyone else have the same problem? Any ideas what might happen if I >try to use WVOffice 7.31 with Xilinx M1.4? > >Thanks, >mark >Article: 8759
I was wondering if there is a design out there for an 8 bit inteface to a PCMCIA card, the card I wish to talk to is any PCCard modem. I would like to interact with an 8031 type microprocessor through an CPLD or FPGA. Does any know of a design that I could look at? Richard.Article: 8760
feydo wrote: > > Just got back from Altera training so I think I can explain their gate > counting method. > In a 10k100 you have 12 EABs, each of them containing 2048bits. Altera > considers each bit equivalent to 4 gates when used for logic. > > EABs = 12 * 2048 * 4 = 98304 gates > > Each LAB contains 8 LEs. Altera considers each LE equvalent to 12 gates. > > LABs = 624 * 8 * 12 = 59904 gates > > Assuming everything is used for logic this gives the maximum number of > ~158,000 gates. > > The mininum number assumes that no RAM is used for logic ==> ~62,000 > gates. > > As for the speed question ... I hope they will run that fast ... I'm > just starting my first Altera design and it will need to operate at 50Mhz. > I have done Xilinx designs which run at 50Mhz, but you must be VERY, VERY > careful. Hopefully the Altera tools will make this an easier target to > reach. > Personally I think it is easier in Xilinx (although floorplanning is also more necessary to get performance). The practical speed in either really depends on what your design is doing. If you've got arithmetic stuff (ie you are using the carry chain) you get pretty quickly limited to one level of logic in Altera due to the carry propagation time. This isn't much, since the using the carry knocks your LUT size down to 3 inputs including the carry input to the LUT. An adder-subtracter is forced to be two levels of logic if the carry is used. On top of that, you are more of less forced out of the LAB for the second level because of the carry chain structure. THat means that the interconnect between levels has to go on the row connect. Even though they call it a Fast Track connection, it isn't all that fast (in a 10K30-3 it is 3.7 ns if you stay in the same row...which may be hard to do because the carry chain stays in the row too, 5.5 ns to stay in the same column and more than 9ns otherwise) THis is on top of about 3.9 ns for propagation through the LUT, setup and clock to out on the LE. Bottom line is for single level logic with no carries, you are practically limited to a minimum global clock cycle of about 13ns in a -3 part. The LUT is rather limited in capability. Put a carry chain in the logic and your minimum clock cycle will increase quickly. For a 22 bit add-subtract you can get about 45-50MHz depending on placement and how full the device is. You can do better if you restrict the high speed logic such that the connections across rows remain in the same column, and even better if all the high speed logic can be kept in the same row. Be aware that the routing times increase substantially as the device size increases (10K100 same row is 5ns, differnet row is 14ns) and that the routing resource in the larger device has a higher ratio of LEs to route tracks which can create routing problems With Xilinx 4K you get 4 inputs on the LUT with the carry, and a 5th input using the H generator isn't the end of the world. Carefully planned layout can get interconnect in a -2 xilinx on the order of a nanosecond ... about 3 times faster than the Altera Fasttrack connections. In the dash 2 part, the upper limit for frequency is set by a minimal clock to out, route and set-up of about 6.5ns, which I have done. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 8761
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 8762
<snip> > > Er, if you did a PCI interface in an Actel part....it wasn't PCI > > compliant. As far as I know, Actel does not meet all PCI > > requirements....you need to use two pins for one signal, and that is > > illegal in PCI land. <snip> > > I must disagree with you. I have designed PCI using Actel ACT3 . They > have and are fully compliant to PCI. > Low power and security are important to me and I can the pack 90+ % > while locking the pins. Their new MX family is also pretty good. So > they are out there and making their name. I am quite happy. If you have > a chance, look at their new MX devices. > At last tally, none of the Actel parts werer *fully* PCI compliant. They required two pins to be paralleled in order to meet the PCI VI curve. This may have changed in newer parts.... Did you take into consideration the /STOP-/FRAME bug I mentioned? It is quite difficult to make timing and fix that bug... AustinArticle: 8763
Austin: : <snip> : : > > Er, if you did a PCI interface in an Actel part....it wasn't PCI : > > compliant. As far as I know, Actel does not meet all PCI : > > requirements....you need to use two pins for one signal, and that is : > > illegal in PCI land. : : <snip> : someone, name lost in the replies: (gotta learn how to run this thing) : > I must disagree with you. I have designed PCI using Actel ACT3 . They : > have and are fully compliant to PCI. : > Low power and security are important to me and I can the pack 90+ % : > while locking the pins. Their new MX family is also pretty good. So : > they are out there and making their name. I am quite happy. If you have : > a chance, look at their new MX devices. austin: : At last tally, none of the Actel parts werer *fully* PCI compliant. They : required two pins to be paralleled in order to meet the PCI VI curve. : This may have changed in newer parts.... rk: ... yes, i believe it has, perhaps this info will help. in act 3, they started with the 'A' series at 0.8 um. then they moved to the 'B' series, denoting the 0.6 um devices and added another foundry or two for these designs. lastly, about a year or so ago, they added the 'BP' series, also at 0.6 um, with pci compliant i/o. i have their '96 data book handy and they have in it an advanced data sheet the usual i-v curves, slew rate #'s, and guaranteed clk -> out times, using the flip-flops in the i/o modules. home modem is too slow put i'm pretty sure they have up to date sheets on the www (been a while since i looked at the 'bp' in gory detail). now, if i remember correctly, the pci specification (to be 100% compliant) only allows one load per signal, please correct me if i'm wrong. from "pci, hardware and software, architecture and design" by solari and willse, page 436, they say the following with regard to clock lines: the CLK signal line can only have a trace length of 2.5 inches +/- 0.1 inches from connector pad to a component and may be attached to only 1 load the act 3 architecture has 4 clocks, 2 general low-skew array clocks, 1 high-speed dedicated array clock, the hclk, (more restricted on what can be hooked to it), and a dedicated clock for the i/o ring. the other clocks or general signals can't be routed as i/o clocks. to get the good tsu and th performance, the flip-flops in the i/o modules (there are two, 1 for input, 1 for output) must be used and so two pins have to be used for clocks. as an example, in the 208 pin plastic package, the ioclk is pin 156 and the hclk is pin 82, on opposite sides of the package. now, any pin can drive the two array global low-skew clocks so you can pick one next to the ioclock if you want, taking care of some of the trace length issues (and one must remember to check skew between the clocks, of course). as a timing example, you can drive from the general array clock pin, to an array flip-flop, and out through a non-registered output buffer. for a sizable design, +125C, +4.5V, a14100a-1, worst-case process, pin -> pin timing is approximately 28 nSec or so, not suitable for pci (remembered from a design done last spring). while the 'bp-3' would be better, the i/o module flip-flops must be used to get the data off chip quickly. haven't checked out the 42mx stuff yet for pci. so, i don't think they can be made *fully* compliant as austin stated, please correct me if i mis-read or mis-remembered the specification. in austin's original reply i thought he was referring to this clock pin issue - as far as i know, the i/o modules are fully pci compliant. hope this helps, -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8764
I have just finished putting up a search engine that allows FGPA users the ability to find an adapter that will allow them to find adapters that will allow them to program the devices. You simple need to supply the manufacturer and device name and it will list all the adapters for all the different package types. I need help testing this search engine. http://www.adapters.com Go to Search Go to Programming You need to register and you are on. Information that I need help with. 1. Is it easy enough to use. 2. Do you find any errors or problems. 3. Does it have the devices that you are looking for. 4. Any other suggestions or comments 5. Any questions about the search engine or how it works. Please, give me any feedback that you have. roystahl@ix.netcom.com roy@adapters.com I will post back in a week or two and let you know how it is going and look for more help testing the site.Article: 8765
I have been told by Xilinx that since M1.4 reads XNF, it will work with any Viewlogic that emits XNF, including my ancient 1992 stuff. >Just got my M1.4 (Alliance) software today and I was quite surprised to see >that version 7.4 of WVOffice is required. I have been using M1.3 along >with WVOffice 7.31 for some time and was looking forward to M1.4 so I could >get rid of the XACT software (required for 3K and 5K designs with M1.3) and >free up some disk space. It now looks like I will either have to a) shell >out even more $$$ to get WVOffice 7.4 or b) stay with the M1.3 tools. > >Does anyone else have the same problem? Any ideas what might happen if I >try to use WVOffice 7.31 with Xilinx M1.4? Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8766
I know "IP" is all the rage these days, but is it really worth paying $1000s for a UART design? And one of the objectives in the "IP" business is that the customer never gets hold of a copyable schematic. This is comparable to building a product where you buy-in some of the firmware without sources. Not a good idea, IMHO. The other thing is that building a really full-featured UART (e.g. a 16550) is a big waste of a big and expensive FPGA. And one certainly does not need to pay any money for schematics of simple UARTs - they are to be found in various FPGA vendors' appnotes; I recall Actel and Xilinx both have them. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8767
Rick Filipkewicz <rick@xxxxz.co.uk> wrote in article <34C888D2.446B9B3D@xxxxz.co.uk>... : I'm looking for a source of Military temp. range (Not necessarily : full Mil-Spec) 3.3V FPGA/CPLDs. So far I've come up with: : : ACTEL : QuickLogic (3.3V ?) <snip> my '94 q-logic data book has advanced data sheets for 3.3 volt QLL8x12b, QLL12x16b, and QL16x24b fpga's. can't locate my more recent data book right now. their pasic3 is 3.3 volts and you can run them in 5 volt systems too (by hooking vccio to 5 volts). -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8768
Peter <z80@ds.com> wrote in article <34d150a2.8058597@news.netcomuk.co.uk>... > > I know "IP" is all the rage these days, but is it really worth paying > $1000s for a UART design? I may have a slightly biased viewpoint on this subject since I am part the team that in fact charges more than a $1000 for a UART design. I think that it is important to examine what is being purchased. The IP business is predominately an ASIC business. Very few cores are sold into designs that will remain in an FPGA socket for the life of the product. An ASIC customer is willing to shell out the money for a core that has been proven in silicon; has the simulation test benches to support integration into their new design and has the support of the vendor for the integration. The buyer is trying to get his product to market sooner by purchasing the chunks he can and focusing his time on developing the secret sauce that makes his "widget" special. He also is trying to insure success on his first pass of silicon. His time and peace of mind is worth the thousands of dollars. > And one of the objectives in the "IP" business is that the customer > never gets hold of a copyable schematic. This is comparable to > building a product where you buy-in some of the firmware without > sources. Not a good idea, IMHO. I think that this is a business issue that the IP industry is trying to figure out. There are several models being tried by different vendors. It's not time yet to assume everyone is working by the same rules. True, There is a great deal of work being devoted to locking schemes and encryption of the designs. (most of it by CAE vendors) Personally this reminds me of Lotus 1-2-3 in the early days. Other vendors are supplying the source and are charging for the maintenance and support (much like firmware support today) Memec Design has taken a somewhat different approach. We supply the source for a one-time fee. The buyer is allowed to use the core in as many designs as they please... provided that the designs are in Xilinx FPGAs. The source in the case of the UART is ViewLogic schematics, with simulation command files, time specs, data sheet and example designs. If the customer needs it, we also have a 40 pin carrier so they can try our core in place of a 8250 UART. Is this worth a couple of thousand dollars? > The other thing is that building a really full-featured UART (e.g. a > 16550) is a big waste of a big and expensive FPGA. I agree that using an FPGA for a UART is questionable. We get a lot of inquires were the customer wants four UARTs in one FPGA and nothing else! We politely point them to EXAR/Startech or another such vendor. But on the other hand, an FPGA is a great place to have a UART that is only there for product debug and development. The software guys can buy the drivers for a standard product and the hardware guys use a bigger FPGA for development; Later they remove the UART and use a smaller device for production runs. Other customers use multiple configurations where the UART maybe in one version for test/debug modes and is removed in the runtime configuration. There ARE situations where having a full featured UART is useful. > And one certainly > does not need to pay any money for schematics of simple UARTs - they > are to be found in various FPGA vendors' appnotes; I recall Actel and > Xilinx both have them. > If the appnotes are all that are needed, that's great. But many times those design's haven't really been tested out. Often you don't get the simulation, time specs or anyone that remembers anything about the design if you have a question. I think we agree more that we disagree on this topic, I just wanted to point out some of the other views on the subject of IP. I don't have all the answers, and only can grasp a few of the questions. I think that IP in FPGAs has been a non-issue because of the size of the parts. Now that the marketing guys have discovered big numbers, it will be interesting to see if there will be a market for IP in FPGAs. John Memec Design Services - BostonArticle: 8769
Hi every one:
A new app. note from Xilinx states “Maximum DC overshoot or
undershoot above VCC or below GND must be limited to either
0.5 V or 10 mA, which-ever is easier to achieve."
I have an application where the state of a switch (open or ground)
has to be read by an FPGA/CPLD. The switch output would swing
from -2 to +9.0 v but is current limited to 100ua (micro-amps). I
have to interface with 30 such switches. Is it safe to interface all
these
switches directly to the FPGA/CPLD as long as their output is
current limited?
Regards,
Kayvon Irani
Los Angeles, Ca
Article: 8770
Rick Filipkewicz wrote:
> I'm looking for a source of Military temp. range (Not necessarily
> full Mil-Spec) 3.3V FPGA/CPLDs. So far I've come up with:
>
> ACTEL
> QuickLogic (3.3V ?)
> Lucent
> Xilinx
>
> Are there any others ? Which SRAM based vendors do mask programmed
> versions ?
>
Rick:
We have been using Military Cypress CPLDs (flash 370). A new company
called Clearlogic featured on the cover of the latest EE Times claims
a push-button mask conversion for Altera Flex8000 and apperently they
can test for Mil. temp also.
Regards,
Kayvon Irani
Los Angeles, Ca
Article: 8771
z80@ds.com (Peter) writes:
> I know "IP" is all the rage these days, but is it really worth paying
> $1000s for a UART design?
>
> And one of the objectives in the "IP" business is that the customer
> never gets hold of a copyable schematic. This is comparable to
> building a product where you buy-in some of the firmware without
> sources. Not a good idea, IMHO.
Or comparable to buying a 16550 and putting it on your board. No
schematics of the internals either.
> The other thing is that building a really full-featured UART (e.g. a
> 16550) is a big waste of a big and expensive FPGA. And one certainly
> does not need to pay any money for schematics of simple UARTs - they
> are to be found in various FPGA vendors' appnotes; I recall Actel and
> Xilinx both have them.
I would expect you get what you pay for...
The trouble with IP as I see it, is making sure there aren't any bugs
in the code. A bit like buying low-level software and hope it will
work.
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 8772>Memec Design has taken a somewhat different approach. We supply the source >for a one-time fee. The buyer is allowed to use the core in as many >designs as they please... provided that the designs are in Xilinx FPGAs. Interesting. How do you enforce this? By supplying the schematics in Viewdraw format, with the "magic number" locking them to the Xilinx version of Viewdraw? But then what if someone has the unrestricted version of Viewlogic? I did an ASIC recently, and it is interesting to discover just what things the ASIC vendors can offer, if you ask nicely. A lot of them have CPU cores which they don't advertise - presumably reverse engineered in some HDL. UARTs, timers, the usual PC chipset bits are all available, and often for free. There is a fair bit of this stuff going around. I am not against someone charging $1000s for a UART design, especially if one is supplied with the schematic. But I am curious how long the vendor can do this for. In the software business, companies continue to make money by churning out new "improved" versions; in the IP business one would seem to be limited to doing reverse engineered designs of commonly used VLSI chips. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8773
Hello, I have been using Viewlogic 4 (DOS) and XACT6 PPR for XC3000 designs. It has occurred to me that XACT6 might be ignoring these net attributes, as attached to certain wires in Viewdraw. I don't want to clutter a simple question, but the reason this came up is that years ago, Xilinx app engineers were recommending that (if one cannot use the global clock nets) it is OK to use a long line for it, by using the L attribute. One could also put in a very tight skew spec, like SC=1. This worked fine with the old APR (and with the slower devices of the day), but with XACT6 PPR it often fails. I recently heard that XACT6 now ignores these net attributes. I know that the Xilinx preferred method today is timespecs. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8774
In article <885421136.338231300@dejanews.com>, husby@fnal.gov writes: > 1) 16.76 ns No optimizations, timing driven routing > 3) 8.23 ns Mapping and hand placement That factor of two is why/where I spend a significant amount of my time. I just end up working on problems that need the extra speed. In article <MPG.f31bc498e0511e989689@news.anet-chi.com>, thomas@x-tekcorp.com (Thomas Rock) writes: > 2) The place and route times for Xilinx ran between 24 hours (68% full) > and 53 hours (70% full). It seemed odd that a relatively small change in > logic produced such a large change in place and route time. I gave up on automatic placement years ago. If that's typical, then I won't need to spend much effort trying it again for a while longer. -- These are my opinions, not necessarily my employers.
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