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In article <34CAEB01.51EB9115@cinenet.net>, Kayvon Irani <kirani@cinenet.net> wrote: > Hi every one: > > A new app. note from Xilinx states “Maximum DC overshoot or >undershoot above VCC or below GND must be limited to either >0.5 V or 10 mA, which-ever is easier to achieve." > > I have an application where the state of a switch (open or ground) > has to be read by an FPGA/CPLD. The switch output would swing > from -2 to +9.0 v but is current limited to 100ua (micro-amps). I > have to interface with 30 such switches. Is it safe to interface all >these > switches directly to the FPGA/CPLD as long as their output is > current limited? Remember it is 0.5V ir 10ma whichever comes first. I would not recommend that at all. I would personally say an SRAM part should survive that much voltage if it current limited for 100ua. However, if you have some voltage rining in your inputs to your fpga the device will likely blow in notime. > > Regards, > Kayvon Irani > Los Angeles, Ca > >Article: 8777
Max+Plus II has the capability to perform timing driven compilations for some versions now. From what I heard, Max+Plus II 8.2, which was just released, has an improved TDC. When I need to meet timing requirements, TDC is what I use first. Ying ying@csua.berkeley.edu -- ----------------------------------- http://www.csua.berkeley.edu/~yingArticle: 8778
In article <34C82196.8CCC0C0C@magma.ca>, Richard Sloan <sloan@magma.ca> writes >Spare time? > >I am working on a design for a video capturing device, I have most of >the hardware >designed and implemented when I found that there were some problems with >the design and a CPLD would have to be developed to handle some of the >high speed stuff. > >I hope to use the 9572 by Xilinx to do this. > >Basically the CPLD must look at some 8 bit data and extract embedded >codes that represent new frames and new lines for the video image being >digitized. Then it must shuffle some of the embedded codes along with >some digitized video images off into an attached SRAM buffer. The SRAM >would be address through a counter. The data comes in at around 28Mhz, >so in about 30ns you must read the data and then make some decisions to >write it or get some more data, the write of the SRAM may occur right >away and be follow by another write immediately or may take a few cycles >for the next write. > >I would like to hook up with a willing sole and see if we can't get this >project done together. I do have Foundation at my disposal, just not the >time to learn it right now. > >Let me know what you think by emailing me at sloan@magma.ca and we'll >see if we can't make some magic happen with this beast. > >Thanks, >Richard. > > I can do any CPLD, FPGA, ASIC design you like - I am a UK based design engineer with all the XIlinx, Actel, Altera, Lattice, AMD, tools, etc. Previous designs range from 22V10s to six Xilinx 4025 FPGAs in a single design. The power of email means I can work for companies around the world from the UK. If I can help, contact... mark@woodstec.demon.co.uk Regards, Mark WoodsArticle: 8779
Kayvon Irani wrote: > A new app. note from Xilinx states “Maximum DC overshoot or > undershoot above VCC or below GND must be limited to either > 0.5 V or 10 mA, which-ever is easier to achieve." > > I have an application where the state of a switch (open or ground > has to be read by an FPGA/CPLD. The switch output would swing from -2 > to +9.0 v but is current limited to 100ua (micro-amps). Since I wrote the note, I might as well explain it here:The conventional statement about not exceeding Vcc by more than 0.5 V is really nonsense. Worse than that, it is being violated by the reflections on every pc-board. The real problem is not voltage, but current, since almost every manufacturer has ESD-protection diodes between the pin and Vcc. These diode protect the input even when a capacitor with a few thousand volts is discharged through a 1.5 kilohm resistor that limits the current. (This is called the human-body model). Protection diodes can easily handle hundreds of milliamps, but the metal width in this areea does not tolerate such currents indefinitely. That's why we say: Don't exceed 10 mA of continuous current per pin. So the short answer is: No problem with a 100 microamp current-limited driver. But you will never see 9 V. The pin will clamp the voltage at less than 1 V above Vcc. And the system will live happily ever after. Peter Alfke, Xilinx ApplicationsArticle: 8780
There has been much comment on Xilinx vs: Altera. Can anyone comment on Lattice parts? Regards, Gary LevinArticle: 8781
You could be sure by fitting a dual schottky diode (BAS16 ?)
which is in a miniature SOT-23 package to clamp to VCC & GND ...
e.g.
VCC
!
K2
----------- #
Input ------[ 470R ]------ A2K1
----------- #
A1
!
GND
The 470R limits input current.
The schottky diodes conduct at a lower voltage than the
logic pin clamp does.
Paul.
Rita Madarassy wrote in message <6ahidn$ak5@darkstar.ucsc.edu>...
>In article <34CAEB01.51EB9115@cinenet.net>,
>Kayvon Irani <kirani@cinenet.net> wrote:
>> Hi every one:
>>
>> A new app. note from Xilinx states “Maximum DC overshoot or
>>undershoot above VCC or below GND must be limited to either
>>0.5 V or 10 mA, which-ever is easier to achieve."
>>
>> I have an application where the state of a switch (open or ground)
>> has to be read by an FPGA/CPLD. The switch output would swing
>> from -2 to +9.0 v but is current limited to 100ua (micro-amps). I
>> have to interface with 30 such switches. Is it safe to interface all
>>these
>> switches directly to the FPGA/CPLD as long as their output is
>> current limited?
>
>Remember it is 0.5V ir 10ma whichever comes first. I would not recommend
>that at all. I would personally say an SRAM part should survive that
>much voltage if it current limited for 100ua. However, if you
>have some voltage rining in your inputs to your fpga the device will
>likely blow in notime.
>
>
>
>
>
>>
>> Regards,
>> Kayvon Irani
>> Los Angeles, Ca
>>
>>
>
>
Article: 8782Rip Loomis wrote: - -Can anyone tell me who the players are in the manufacture of RadHard -FPGA's? I'm aware of efforts by ACTEL, SPEC, SEi, Honeywell, and -Mission Research Corp. Are there others? Who seems to be the industry -leader in terms of hardness to severe/nuclear environment specs? - -Thanks for the input. - -David LaVigna -dlavigna@radium.ncsc.mil Wasn't Harris corp working with Xilinx as a second source for the 3000 series FPGA's?Article: 8783
Jeff <me@home.sleeping> wrote in article <34CCF88A.1F60@home.sleeping>... : Rip Loomis wrote: : - : -Can anyone tell me who the players are in the manufacture of RadHard : -FPGA's? I'm aware of efforts by ACTEL, SPEC, SEi, Honeywell, and : -Mission Research Corp. Are there others? Who seems to be the industry : -leader in terms of hardness to severe/nuclear environment specs? : - : -Thanks for the input. : - : -David LaVigna : -dlavigna@radium.ncsc.mil : : Wasn't Harris corp working with Xilinx as a second source : for the 3000 series FPGA's? hi, if iirc this was the story; perhaps someone else (with a bit better memory) can fill in some details. a few years ago one or some of the xilinx devices appeared in the harris rad-hard data book as preliminary data sheets. the words that i heard were that the first devices did not work as there were some shorts in them and that the processing line that they were built on at harris (soi?) was shut down; and there were no efforts to move the design to another line. i can look up more details if any one is interested; i do have the data sheets somewhere in the basement. the xc3020 and xc3090 were the devices being ported (correct pete?). -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8784
In article <34C7E444.1970@ti.com>, gurrapu@ti.com writes... > >I have almost decided to use 10K100 part which has 12 EABS, eight of >which can be used for implementing the RAM. The remaining EABs and the >624 LABs will give me approximately 62K available gates. > >One more thing I'm concerned is our design has some blocks operating >at 48 MHz. Is that Ok in Altera devices? What'd be the practical max CLK >for altera devices assuming that I've all i/ps and o/ps registered. I have some experience with the smaller devices (10K10 & 10K20). I find that for these devices, if I limit the maximum # of cascaded 4-input lcells to 3 levels, I can usually acheive 45 to 55 MHz operation (most of my designs run at 40 MHz with a few small parts at 80 MHz). For 80 MHz, I have to limit the logic to 1 lcell (max fan-in of 4) per pipeline stage (unless I use an occasional CASCADE primitive) and a fan-in of 1 (and possibly an enable) on the I/O cell flip-flop. Counters of up to 8 bits using the LPM_COUNTER are also OK. This usually achieves 100 to 125 MHz on the timing analyzer. The main problem is that the 10K100 is significantly slower than the 10K10 and 10K20. A 10K100-3 will probably limit you to about 2 levels of lcells. You may want to look at the 3.3 volt devices; 10K100A-1, 10K100A-2, and 10K130V-2. Not only are they significantly faster, but they are also much lower power. The V series has about 1/2 the current consumption and the A series has about 1/3 the current consumption of the 5 volt devices. The lower voltage saves additional power. Daniel Lang dbl@hydra0.caltech.eduArticle: 8785
Hello guys, my name is Amir, I live in Brazil and I'm very interested in this old technology that's becoming cheap and powerfull. However, I don't know enough to start. I'd like if someone could give me some hints, like sites, softwares and some advices. I have played with a software called Synario v2.10 which I got in a CDrom. It seems that each vendor has it's own free version of Synario that supports its chips. I'm considering using Atmel's ATF1508 (128 macrocells + ISP), it seems to be a good choice for a beginner, and I already ordered 2 samples from my chip supplier in Sao Paulo. I'd like to know more about ISP. How can I program the CPLD? \ can I use any ISP download software? Is there any free/ shareware ISP downloader? Can I use Altera's byteblaster? Is Synario worth learning? Please, someone help me!Article: 8786
In article <34C7C89A.17B64362@radium.ncsc.mil>, rip@radium.ncsc.mil says... > >Can anyone tell me who the players are in the manufacture of RadHard >FPGA's? I'm aware of efforts by ACTEL, SPEC, SEi, Honeywell, and >Mission Research Corp. Are there others? Who seems to be the industry >leader in terms of hardness to severe/nuclear environment specs? > >Thanks for the input. > >David LaVigna >dlavigna@radium.ncsc.mil > Perhaps another angle is to look at a "commercial FPGA" such as the fusible links Quicklogic combined with a total dose improved packaging such as offered by RadPack (won't help for SEL). Wouldn't it be nice if you could buy an SOI/SOS ram based FPGA..... Hans.Article: 8787
Does any one know of a RELIABLE ABEL to Altera-HDL conversion utility? Where is the FAQ for this news group? Thank you, Douglas L Datwyler Alta Technology datwyler@altatech.comArticle: 8788
Hi,
At the moment I am involved with a design that will go first into an
FPGA and later it will be part of an Asic.
As FPGA, we selected an Altera Flex10K10 (or if required we could go
to a Flex10K20). Higher sizes were not possible due to the package
that we selected (144TQFP) and the voltage on the board (only 5V).
Our estimates initially were about 8Kgates (of which 400 flip-flops)
and 1.8 kbit of ram (single port). The device runs at 4MHz.
We are now experiencing big problems in fitting the device in a
Flex10K20 !!
Synthesis for an Asic tells me that the current design has :
- 663 FFs -> 3656 equivalent gates (nand2's)
- combinatorial logic -> 2869 equivalent gates (nand2's)
- some RAM, but this is mapped into the 3 EAB blocks.
I got somewhere the info that on the average, a LE (logic element)
is equivalent to 6..12 gates.
For me, I had assumed that this 6..12 gates is actually "combinatorial"
logic only. If this is the case, my design would (in worst case)
need only 472 LE's for the combinatorial part. Flip-flops and logic
could share the same element in most of the cases, so for a 10K20,
there should be (according to me) no problem for routing.
A 10K20 has 1152 LE's (each LE is a 4input LUT, some extra logic, a FF).
The current status of my design is that it needs about 1080 LE's
(report of MaxPlus2) but we can't get it routed (it complains on
fasttracks that are all used somewhere in the design).
So my question is :
- this 6..12 gates/LE : is this with or without the Flipflop gates ?
Are there other people who have got similar problems with either
routing or problems in estimating the size of the target device ??
Thanks.
--
Koenraad SCHELFHOUT
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VH14 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 47 \ / /
mailto:ksch@sh.bel.alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
Article: 8789Has anyone designs which fitted with M1.3 release and do not longer fit with M1.4 ? We have a 4010 design which no longer fits with M1.4 in a 4010E and which simply crashes PAR for a 4010XL device. We are stuck. Anyone recommendations on M1.4 settings to solve this problem ? Is there a way to downgrade to M1.3 else then to reinstall full M1.3 ?Article: 8790
Hi all, I've been offline for a bit, so after catching up I thought I'd dive on in with the XOR gate saga :-) I did two (wait for it) VHDL implementations, one which was a plain vanilla 36 bit loop on a variable, the other, using one instantiation and some NOMERGE properties to aid mapping to ORCA. My results in the same 2T06A-5 array are interspersed with Don's. RK's reults : > a1460bp-3 14.6 nSec > 42MX09-2 10.3 nSec Now Don's >Numbers for an ORCA 2T06-5 (worst case): > >1) 16.76 ns No optimizations, timing driven routing > 14 PFU Time to enter schematic: 1 minute Plain (portable) VHDL synthesised for speed, automatic P&R. 11.6 ns 13 PFU >2) 10.29 ns Mapping constrained on schematic > 10 PFU Time to enter schematic: 10 minutes Mapping constrained in VHDL - (delay optimise), automatic P&R. 9.96 ns 10 PFU The P&R tool put all input flipflops arranged on one edge of the chip directly abutting inputs to simulate actually coming in with correct setup time for PCI etc. The ouput result FF was internal. The same thing in a 2T15-6 squeezed in at just under 7.5 ns. Oooh, Smokin'. >3) 8.23 ns Mapping and hand placement > 10 PFU Time to enter schematic: 10 minutes (same as above) > Time to place blocks: 2 minutes Good result from hand placement. Stuart -- For Email remove "die.spammer." from the addressArticle: 8791
On Tue, 27 Jan 1998 10:00:30 +0100, Koenraad Schelfhout VH14 8993 <ksch@sh.bel.alcatel.be> wrote: >At the moment I am involved with a design that will go first into an >FPGA and later it will be part of an Asic. :-) <snip> >We are now experiencing big problems in fitting the device in a > Flex10K20 !! Stuart raises eyebrow ;-) >Synthesis for an Asic tells me that the current design has : > - 663 FFs -> 3656 equivalent gates (nand2's) > - combinatorial logic -> 2869 equivalent gates (nand2's) > - some RAM, but this is mapped into the 3 EAB blocks. > >I got somewhere the info that on the average, a LE (logic element) >is equivalent to 6..12 gates. I think you'll find that includes the register. But it's a finger in the air against other FPGA's, not really against ASIC. >For me, I had assumed that this 6..12 gates is actually "combinatorial" Never assume. It's what FPGA Marketeers rely on you to do. >logic only. If this is the case, my design would (in worst case) >need only 472 LE's for the combinatorial part. Flip-flops and logic You forget things like non-sharable inputs, inefficient cascading of multiple levels of logic, mutual exclusion of flipflops and logic, routing limitations etc... <snip> >A 10K20 has 1152 LE's (each LE is a 4input LUT, some extra logic, a FF). > >The current status of my design is that it needs about 1080 LE's >(report of MaxPlus2) but we can't get it routed (it complains on >fasttracks that are all used somewhere in the design). 94%? And you are surprised why it won't route? <snip> Simple crude approximation. =========================== Take ASIC gates, and multiply by 2. That should put you in the ballpark for FPGA gates. You might then need a "wiggle factor" based on the typical utilisation you can expect from an architecture and still have it route. Say 60% to 80%. Your 94% fill sounds very unlikely to be acheivable even given the low 4MHz speed. You have your 6525 ASIC gates, multiplied by 2 gives 13K FPGA gates. Divide by 0.6 or 0.8 and you get 16K to 22K EPF10K20 usable (FPGA) gates 15,000 to 63,000, but 63K is counting RAM, so combinatorially say 15K (FPGA) gates. Even with the rough rule of thumb, the estimate says you have two hopes: Bob Hope & No Hope. Stuart -- For Email remove "die.spammer." from the addressArticle: 8792
Can anyone offer any advice or comments about using "negative hold time" with a Xilinx 4000XL ? Looking at the various IOB and clock delays, it looks like you can sample input data at a point a few nanoseconds before the clock rising edge (hence negative hold time). However, the datasheet only quotes zero hold times and not particularly worst-case. So - is there such a thing, how much, and is it practical to use ? (My application is a hold time problem due to upgrading from a 4000E to the faster 4000XL) Regards, RichardArticle: 8793
Hi,
The Ph. D. forum at DAC provides a structured way of increasing
interaction between academia and industry. The forum's goals include:
(a) providing graduate students with feedback on their thesis work
from other researchers, and
(b) giving CAD and system companies a chance to preview academic
work-in-progress.
The forum consists of two sessions:
1. An open poster session, hosted by SIGDA SIGDA during their
member meeting on Tuesday, June 16, 7-9 p.m. All interested DAC
attendees are invited to attend. Illustrating their work via posters,
participating students will describe their work to interested
audience.
2. A closed discussion session to be held on Wednesday, June 17,
6:00-7:30 p.m., during which students received detailed feedback about
their work.
Students and researchers (from both industry and academia) are
encouraged to participate in the forum. Please visit the forum's web
page: http://www.cs.washington.edu/homes/soha/forum/ for more details
on how you can participate in the forum.
This project has been approved by DAC, and it is sponsored by SIGDA.
For any questions or comments, please send e-mail to
daforum@cs.washington.edu
Thanks.
Forum organizers,
Soha Hassoun & Olivier Coudert
Article: 8794
In article <MPG.f303c46ac9671d59896b0@nntp.ix.netcom.com>,
Austin Franklin <dark7room@ix.netcom.com> wrote:
>In article <En3sCB.Aq3@world.std.com>, jhallen@world.std.com says...
>> In article <34BD0834.2D@wgate.com>, Todd KLine <tkline@wgate.com> wrote:
>> >Hello,
>> >Is anyone doing a synchronous DRAM interface in an FPGA? If so, at what
>> >speeds? This is for ASIC prototyping only, so FPGA cost is not a big
>> >SDRAMs are rated at speeds up to 100 MHz. When my boss tells me he
>> >wants to do this in an FPGA, I just look at him funny.
>> I've done a 50MHz SDRAM controller in a 4013e-3, but it should be possible
>> to go all the way up to 100MHz without a problem with the right fpga (say a
>> 3142a-1 or -09).
(Actually you want to use an XC40xxE-2)
>> The SDRAM controller is pretty simple, and everything can be pipelined.
>> It's a burst device (I burst 4 words at a time), so the address counter only
>> needs to be 25MHz (and I use LFSR for the counter, so even that could be
>> much faster).
>> The other issue is clock skew between the FPGA clock and the SDRAM clock.
>> At 50MHz this was no problem, but at higher speeds it probably will be. You
>> may have to add delay lines to minimize the skew. I'm actually feeding the
>> clock through the FPGA, so you get a slight variation for each run of the
>> place & route. Also you can insert an inverter for a big effect.
>Tell me more....how did you generate the clocks?
Sorry to take so long... I've had the flu for the last week.
For the 50MHz design the clock timing is not critical, so I just took the
clock running the state machines in the FPGA, fed it though an output
buffer, and drove the SDRAM clock pins with it. It and the address and
control lines (also all directly from the FPGA) are driven though 33 ohm
series terminators (they drive a bank of four 2Mx8 SDRAMs).
At 100MHz, the timing becomes critical (I think you get about a 2ns window),
so it would be better to feed both the FPGA and SDRAMs from the same source
and adjust the skew between them with some external delay.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 8795>Take ASIC gates, and multiply by 2. That should put you in the >ballpark for FPGA gates. You might then need a "wiggle factor" based >on the typical utilisation you can expect from an architecture and >still have it route. Say 60% to 80%. Your 94% fill sounds very >unlikely to be acheivable even given the low 4MHz speed. I recently did an ASIC which was prototyped in a XC3090 FPGA where it filled 80% of it. That's about 5k-6k FPGA gates. When the XNF netlist was given to the ASIC firm, and translated, it came out "equivalent" to only 1900 gates. In the XC3090 it would not route (not quite) with APR and I had to purchase XACT6 (about £2500) to route it. The lesson is that when prototyping ASICs one should buy the biggest FPGA around. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8796
can anyone point out a very good advanced vhdl book Kind regards Bart PlackleArticle: 8797
Koenraad Schelfhout VH14 8993 wrote: > Hi, > > At the moment I am involved with a design that will go first into an > FPGA and later it will be part of an Asic. > > As FPGA, we selected an Altera Flex10K10 (or if required we could go > to a Flex10K20). Higher sizes were not possible due to the package > that we selected (144TQFP) and the voltage on the board (only 5V). > > Our estimates initially were about 8Kgates (of which 400 flip-flops) > and 1.8 kbit of ram (single port). The device runs at 4MHz. > > We are now experiencing big problems in fitting the device in a > Flex10K20 !! > > Synthesis for an Asic tells me that the current design has : > - 663 FFs -> 3656 equivalent gates (nand2's) > - combinatorial logic -> 2869 equivalent gates (nand2's) > - some RAM, but this is mapped into the 3 EAB blocks. Hmm, the number of Flip-Flops increased by 60%+ over the initial estimate. Not atypical 8^) Just as an exercise, I'd pass this circuit to some other synthesis vendors as a benchmark for them to evaluate. I've seen differences in logic usage of 1.5 to 2 X (with a couple of designs even going 3X) between the largest and smallest sized results. -- Charles F. Shelor charles@efficient.com Efficient Networks, Inc 'ATM for the Desktop' 4201 Spring Valley, Suite 1200 http://www.efficient.com/ Dallas, TX 75244 (972) 991-3884Article: 8798
<snip question of who are the rad-hard fpga manufacturers> Hans <ees1ht@ee.surrey.ac.uk> wrote in article <6ak5ph$3t9$1@info-server.surrey.ac.uk>... : Perhaps another angle is to look at a "commercial FPGA" such as the fusible : links Quicklogic combined with a total dose improved packaging such as offered : by RadPack (won't help for SEL). unfortunately the early quicklogic devices produced on cypress 0.65 um line easily latched requiring either an element of risk or a latchup detection/power-interruption circuit. there is a plan to test one of the newer pasic3 devices (ql3025, no sram) in mid-february. : Wouldn't it be nice if you could buy an SOI/SOS ram based FPGA..... there was an effort a while back at harris corp. for the xc3000 series but that didn't make it for a variety of reasons. currently, there is an effort at honeywell to port a version of the at6010 on their soi line. of course, you need the rad-hard reprogrammable prom or other non-volatile memory to go along with it or you're just moving the problem. as usual, one must define "rad-hard" very carefully in comparing devices. -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8799
Hello, I'm going to implement ten 32-bits counters running at 20 MHz together with some logic to sequentially read the counters 8 bits at a time from a microcontroller. I'm considering various PLDs for the task: Xilinx XC4006/XC4008, Altera FLEX10K, Altera MAX9000, Atmel AT6000. I'd like to use the MAX9000 (EPM9560) because of its non-volatile ISP feature, but I am unsure whether I will be able to fit the counters in it. I am also unsure whether the counters will fit into the XC4006 or XC4008 (this is an issue because Foundation only supports devices up to XC4008). Since I am new to PLD technology, I would be happy to get some advice on this. Thanks, Knut Arne Vedaa
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