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Hello, this is Amir again (the damn rookie ;-) I've been playing with a shareware version of Synario (2.10) which I go from a Lattice CD. However, I'm planning usong Atmel's ATF1508, which is availlable here in Brazil. I'd like to know: Can I convert an .ABL file to a schematic block/component? Why isn't there any flip-flop with both asynchronous preset and clear, only with one of them? I'm trying to make a 74ls197 compatible block (counter with asynchronous load) Without both the set and reset inputs to the flip flop, I'm having to use a latch and a FF to do the same job. BTW, does anybody know where can I get a new version of Synario and the Atmel libraries (i've downloaded from Atmel's site, but they didn't install and I didn't look further) Thanks for your help! amirma@hotmail.comArticle: 8976
Hello everyone.
I need some help with FPGA/chip-design synthesis programs.
I've heard of ocean, spice and chipmunk. The version of chipmunk I had was an unfinished
work, you can imagine my happyness after getting halfway through stat-entry and
realising I was using the beta!
So, I dont know if other synth programs cost money, or are freeware or what. Im
looking for something that will work with Xilinx FPGA chips.
If anyone can help me please drop me a line:
z5c@hotmail.com
ALSO- if anyone can tell me an estimate of how many gates it would take to emulate a
simple device (floppy, for instance), as I have limited materials here and can only
guess what it would be.
thanx alot,
-Eric Blincow
Article: 8977
Hello everyone.
I need some help with FPGA/chip-design synthesis programs.
I've heard of ocean, spice and chipmunk. The version of chipmunk I had
was an unfinished
work, you can imagine my happyness after getting halfway through
stat-entry and
realising I was using the beta!
So, I dont know if other synth programs cost money, or are freeware
or what. Im
looking for something that will work with Xilinx FPGA chips.
If anyone can help me please drop me a line:
z5c@hotmail.com
ALSO- if anyone can tell me an estimate of how many gates it would take
to emulate a
simple device (floppy, for instance), as I have limited materials here
and can only
guess what it would be.
thanx alot,
-Eric Blincow
Article: 8978You can check the page http://www.actel.com/html/_____sales_office.html for distributor in your local area. Alex On Tue, 10 Feb 1998 08:21:11 -0800, "Steven K. Knapp" <sknapp@optimagic.com> wrote: >I believe that Texas Instruments has discontinued these devices. However, >Actel (http://www.actel.com) was the original developer of these devices and >continues to sell them as their ACT 1 Series. I would recommend contacting >Actel for their recommendations on an alternative. > >----------------------------------------------------------- >Steven K. Knapp >OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" >E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com >----------------------------------------------------------- > >Ptmsa1 wrote in message <01bd3600$3fb3f4a0$50131fc4@rb>... >>We require information of anyone who might have stock of the TEXAS >>INSTRUMENTS TPC1020AFN-068C FPGA devices for purchase. >> >>We are looking of a quantity of 50. Could you please provide us with any >>information urgently!!!! >> >>Thank-you. >>Bossie > >Article: 8979
Hi, As so many peoples look for a free FPGA Developpment tools suite with only a simple download cable, i'd like you share us your knowledge, and i start first : --> Lattice ISP Synario & ISP DS+ Well, you can get a free CD containing a complete tools chain for both standalone and third party developpment software but for ONLY a few parts (1016 & 2032 --> 32 to 36 I/O max...), then you need a simple download cable (they sell $65 but they even give schematics :-) --> What about Xilinx Foundation sold for $99 ??? --> What about AMD/VANTIS ??? Hope this list will have some feedback ;-) François. -- ------------------------------------------------------------- THIEBOLT Francois \ You think your computer run too slow ? UPS Toulouse III \ - Check nobody's asked for tea ! thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams -------------------------------------------------------------Article: 8980
Philip Freidin wrote: > Check out a really neat program called System Commander, that allows > booting multiple operating systems on the one machine. A utility I > could not live without, and only $69.95 at Fry's. You actually can convince Windows NT to boot DOS, Windows 95, and Windows NT from its regular boot loader. I second the recommendation for System Commander, however, as it makes booting an almost limitless number of different operating systems very painless to setup and use (whereas you or your MIS guys would easily kill $70 getting NT's boot loader to load 3 OSes...). ---Joel KolstadArticle: 8981
I know you can generate a schematic from an edn or xnf file when using the Foundation package. The layout is pretty ugly though. The best schematic generator by far is the one from Mentor Grpahics. In article <34e101e2.0@news1.ibm.net>, Amir Manasterski <amirma@hotmail.com> wrote: >Hello, this is Amir again (the damn rookie ;-) > >I've been playing with a shareware version of Synario (2.10) which I go from >a Lattice CD. >However, I'm planning usong Atmel's ATF1508, which is availlable here in >Brazil. > >I'd like to know: >Can I convert an .ABL file to a schematic block/component? > >Why isn't there any flip-flop with both asynchronous preset and clear, only >with one of them? >I'm trying to make a 74ls197 compatible block (counter with asynchronous >load) >Without both the set and reset inputs to the flip flop, I'm having to use a >latch and a FF to do the same job. > > >BTW, does anybody know where can I get a new version of Synario and the >Atmel libraries (i've downloaded from Atmel's site, but they didn't install >and I didn't look further) > >Thanks for your help! > >amirma@hotmail.com > > > > > > >Article: 8982
Friends, Can anyone point to a competitive comparison of vendors, devices and prices in table format. I would like to know what I can get for my money when designing for anything in quantities of 10,000. Regards, Gary LevinArticle: 8983
We have recently released a new version of our Clustor software, which might be of interest to you and your colleagues. To date, Clustor has been used effectively by other researchers and practitioners in the area of CAD. Clustor greatly simplifies and speeds up parametric executions - running the same application numerous times with different input parameters. It generates jobs, speeds up the task by distributing the jobs over a network and collects the results. Jobs can be distributed over a local area network or over Internet. In the CAD area Clustor has been used to allow the exploration of different design scenarios. Clustor makes it very easy to explore design options through its friendly graphical user interface. Because the work is performed in parallel on otherwise idle workstations, it is possible to perform many more simulations, which greatly improves the quality of the design. Clustor is currently available for major Unix environments such as Digital Unix, Hewlett Packard HP-UX, IBM AIX, Silicon Graphics Irix, Sun Solaris, Linux as well as the Windows NT environment will be released later this year. More details plus a free demonstration license for Clustor can be obtained from: http://www.activetools.com Regards David Abramson Director of Research Active Tools INC.Article: 8984
On Sun, 08 Feb 1998 20:40:18 GMT, mushh@jps.net (David Decker) wrote: >Sure, they could be forced, kicking and screaming, to implement it >this way, but schematics seemed far simpler. Schematic capture also RESULT <= ext((a & "000"),12) + ext(a,12) ; Works just fine through Galileo Xtreme. Single 8 bit adder with the carry out being used. >provided an easy way to control the relative placement of the logic. >this meant that I could build up libraries of minimized, preplaced >DSP parts, for easy reuse. So once you have your relatively placed hard/soft macros you could then heirarchically instantiate said macro's from the hdl. >I wonder if any of these tools have improved enough, in the last two >years, that they would now instantiate a 9 bit adder, and permit me >to graphically, hierarchally, edit the placement of this adder with >respect to the registers on its input and/or output. You can't really lock down that which has yet to be synthesised, but creating a small macro of such a type given above would not be too much trouble (with Foundry anyways). The code below synthesises to six PFU's in ORCA. Two for the input registers, two for the adder (and amalgamated output registers). Another one for the other 4 registers required, and another just to generate a VLow to pad the adder appropriately (only one LUT used): library IEEE ; use IEEE.Std_Logic_1164.ALL ; use IEEE.Std_Logic_Arith.ALL ; use IEEE.Std_Logic_Unsigned.ALL ; entity democct IS port ( clk : IN std_logic ; A : IN std_logic_vector (7 downto 0) ; B_Q : OUT std_logic_vector(11 downto 0) ) ; end democct ; architecture orca of democct is signal aff : std_logic_vector(7 downto 0) ; begin registers : process (clk) begin if (clk'event and clk='1') then aff <= A ; B_Q <= ext((aff & "000"),12) + ext(aff,12) ; end if ; end process ; end orca; Runs 60 MHz in a -2 (slowest) and 100 MHz in a -4 (medium) with auto P&R. Stuart -- For Email remove "die.spammer." from the addressArticle: 8985
At 10000 pieces, I would definitely go with an ASIC. But if you just don't have the time to wait, Xilinx have announced their new Spartan series of fpgas which are quite cheap (according to the gate capacity claimed) but I don't know how "available" they are. You might want to check with ChipExpress although I received a quote from them and they seem to have a hard time competing with FPGAs (their claim-to-fame is rapid time-to-market). Maybe they gave me a "high" quote because they didn't want my business? Anyhow, FPGAs are very hard to compare. Sometimes it's like comparing oranges & apples. You have to see how each device vendor calculates gate capacity based on their FPGAs architecture. Also, your algorithm (or whatever you're implementing) may be better suited for one type of FPGA rather than another. If you are using a high-level design flow, then you should take into considerations the tools you are using. I find the best way to compare is to target my design for different devices and evaluate cost, timing, % utilisation of resources. The problem with this is that each device vendor has his own place&route tools which usually run between $2k-4k. For a small independant like me, this is big bucks. Rgds, Sam Falaki Gary Levin wrote: > Friends, > > Can anyone point to a competitive comparison of vendors, devices and > prices in table format. > > I would like to know what I can get for my money when designing for > anything in quantities of 10,000. > > Regards, > > Gary LevinArticle: 8986
Hi, We are working on compression algorithms for XC6200 bitstreams to reduce reconfiguration time, and have some promising results. We were hoping that you could provide us with some benchmark circuits to use to improve this work. Would it be possible for you send us VHDL/Velab circuits for the 6200 series that we can use in this work? We would be happy to send you compressed versions of your files back when we have finished our work. Also, if you happen to have sets of mappings for run-time reconfiguration (i.e. a series of mappings sent to the XC6200 in sequence for a computation) we would love to get access to these mappings. Thanks in advance, ZhiyuanArticle: 8987
The X84 XILINX FPGA board now comes with a demo version of a VHDL Simulator and Synthesis Tool (PeakVHDL) with examples and tutorials run using the X84 board. The X84 can be gotten for as little as $150.00 !!! See: http://www.associatedpro.com/aps -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 8988
On 9 Feb 1998 15:35:36 GMT, madarass@cats.ucsc.edu (Rita Madarassy) wrote: > >Well, you are probably referring to the ISP Lattice parts. >If you are using these lattice parts you are probably spending >way too much money on these parts. Yes Rita, but like the man said, the tools didn't cost anything. Razor blade marketing eh? Stuart -- For Email remove "die.spammer." from the addressArticle: 8989
On Wed, 11 Feb 1998 10:54:27 -0800, Gary Levin <gary_levin@phx.mcd.mot.com> wrote: >Can anyone point to a competitive comparison of vendors, devices and >prices in table format. Such a table is IMHO not particularly useful. However... You could visit the arrow schweber site and marshall to get some indication of small volume pricing on specific parts available today. These guys cover a number of vendors. What do you want to achieve from such an exercise? Are you looking to simply find who is the lowest "cost per gate", who is the most expensive, or just who has the cheapest part? Do you have a bearing on what your 10,000 parts will have to do? >I would like to know what I can get for my money when designing for >anything in quantities of 10,000. Take your design requirements to the vendors, see what they reckon and then start the auction on forward pricing for your production. Todays pricing will be totally out of date in 12 months time (for most vendors). I assume you production is not imminent ;-) Stuart -- For Email remove "die.spammer." from the addressArticle: 8990
hi there,
Dose any-one know if it is possible to read back the checksum
from an fpga, using xcheker or readback (since i have a micro to process
the data) if so could you point me in the right direction.
the device i am using is xilinx 4000e
Thanks
Davey
--
--
...phil
Article: 8991I am a student, studying at UMIST (Manchester England), I am involved in a project which utilises a XC6264 FPGA (as well as a number of other processing elements). I am currently looking for a synthesis route for the Xilinx XC6264 FPGA I have the xact6000 software + Velab (low level VHDL elaborator, converts low level (subset of ) VHDL descriptions to edif format netlists, but this utility seems to require placement information to be attached to the descriptions) - A library of velab friendly macros comes with this as well as the low level library for XC6200 cell primitives. I've looked at the Trianus/Hades system (system developed at Zurich, takes LOLA h/w description language at the highest level, has various tools (place route, circuit checker .... etc), and will produce the bitstream for the FPGA. This software seems like a workable soluttion, but only supports 6216 and not the larger 6264. There is a tight budget for the project, so unfortunately we cannot afford to buy expensive suites of software. Any suggestions would be most appreciated. Thanks Dave AArticle: 8992
We have been using the Altera classic line (EP1810LC-35T, EP910-30T,
EPM5128LC) in several of our designs for years withour problems but,
since the die-shrink, we have had these devices cause failures in several
of our products. We have been pursuing Altera for help to no avail.
They say they have no problem with the devices, but I have noticed that
the asking price at distributors for the older lot codes has tripled for
the 1810 device in a matter of a few months. This price hike would tell
me that there is significant demand for older lot codes which means we
are definitely not alone. Has anyone else using the classic line found
solutions or gotten help from Altera ??
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8993Hi! I`m looking material about Walace tree. Could you help me, please? Regardless, Victor Levandovsky vicNS@alpha.podol.khmelnitskiy.ua Remove NS if replyArticle: 8994
Hi I have an AMD MACH 5V in-circuit programming kit which was a freebie a couple of years ago. Has anybody used the cable (printer port to 10 way header) and software to program a Lattice ispLSI1016 ? Could I really be that lucky? Thanks -- Keith WoottenArticle: 8995
We have experienced problems with their classic line (EP1810LC-35T,
EP910-30T, and EPM5128LC). Since the switch to the new die, the devices
program and verify OK but they flake out in certain applications. We
have actually had them generate enough heat to burn labels off of them.
Altera is not really helping us and claim we are the problem. We have
procured safety stock of old devices to protect our product lines until
we can reach a resolution. Interestingly, the market price for older
devices (pre die-change) has tripled in recent weeks. We are stumped.
>
> -------------------==== Posted via Deja News ====-----------------------
> http://www.dejanews.com/ Search, Read, Post to Usenet
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8996Stuart Clubb wrote" "You could visit the arrow schweber site and marshall to get some indication of small volume pricing on specific parts available today. These guys cover a number of vendors." Thanks. That is good advice. And Stuart wrote asked "Are you looking to simply find who is the lowest "cost per gate", who is the most expensive, or just who has the cheapest part?" We are not looking for the lowest cost per gate. We would like to be able to compare and choose a vendor for a particular size of FPGA or PLD. Our board designs often have a run rate of several hundred to several thousand per month. Therefore, a 10,000 quantity is not an underestimate for any new design. The problem with PLD and FPGA design is that many devices seem to require vendor dependent tools. Personally, I prefer to use Verilog because we design our ASICs here with Verilog. I just did a bunch of Lattice 2064's and 1016's using Verilog and Synopsys. That worked out fine. But using Verilog for FPGA Verilog doesn't always give the best results. Although Verilog is easier to maintain here. For critical designs, for example, one group of designers use Viewlogic for Xilinx. Another group prefers Altera parts. Our factory likes Lattice because of ISP and manufacturing issues. Still yet, some older engineers like ABEL for smaller PLD's. Our boards are designed using Mentor Graphics DA-LMS. We have older designs still in Cadence. So as you see, the tools can get out of control. What I'd like to know, before I start a new design and get locked into a particular vendor is some competitive pricing for a particular class of device. Unless of course they are mostly cost competitive and it really doesn't matter to compare. Regards, Gary LevinArticle: 8997
Victor Levandovsky wrote:
>
> Hi!
>
> I`m looking material about Walace tree.
> Could you help me, please?
>
> Regardless,
>
> Victor Levandovsky
>
> vicNS@alpha.podol.khmelnitskiy.ua
>
> Remove NS if reply
I extracted this from a recent post of mine to COMP.ARCH.DSP. That was
in response to a question about multipliers. Hope this helps:
A Wallace tree is actually a bunch of full adders in a tree structured
to add several numbers together simultaneously. The structure of the
tree is such that the carries do not form long crosswise chains which
slow down the propagation speeds. A Wallace tree multiplier is one that
uses a wallace tree to combine the bit products. The structure combines
like weighted bits in full adders to reduce the number of bits. THe
next level combines like weighted bits output from the first level.
This is repeated n subsequent levels until there is only one bit of each
bit weight left.
the following diagram illustrates a wallace tree that adds 3 two bit
numbers together. THe FA blocks are full adders (described above). The
HA blocks are half adders (sum=A^B, carry=A*B). The numbers in the
signals are the corresponding bit weights. coming out of an adder, the
sum has the same weight as the inputs, while the carry has a weight one
greater. all inputs to each adder must have the same weight. a[1:0],
b[1:0] and c[1:0] are the inputs.
a0 -| s|--0------------------------out0
b0 -|FA|
c0 -| c|--1---| s|--1--------------out1
|HA|
a1 -| s|--1---| c|--2--| s|--2-----out2
b1 -| | |HA|
c1 -| c|--2------------| c|--3-----out3
I am not sure if there are references to the wallace tree on the WWW.
You might do a search to see what you come up with.
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 8998Gary Levin wrote: > > Friends, > > Can anyone point to a competitive comparison of vendors, devices and > prices in table format. > > I would like to know what I can get for my money when designing for > anything in quantities of 10,000. > > Regards, > > Gary Levin Gary, Look at Xilinx. They are most agressive in that type of quantity. What density are you looking at?Article: 8999
I received the following email response to a posting I submitted on 6-feb to the comp.arch.fpga newsgroup. The reply was sent by Bryon Moyer at Altera. The original posting described some nasty (but avoidable) problems with in-system programming of Altera Max7000s devices. I appreciate Mr. Moyers' having taken the time to reply. The email reply from Altera is included in its entirety, without editing: ================ Begin email reply from Altera ================= Dear Mr. Elkind: Your experience with Altera ISP was brought to my attention via the newsgroup where you posted your message. I wanted to respond, both directly to you as well as to the newsgroup. I was concerned not only with the experience you had, but even moreso with the information you received, much of which was incorrect. Please review the response below; I wanted you to see it personally before posting to the newsgroup. If you have further questions, please feel free to contact our hotline at (800) 800-EPLD or send an email to sos@altera.com. Regards, Bryon Moyer Sr. Manager of Customer Applications Altera Corp. 101 Innovation Dr. MS 1203 San Jose CA. 95134 (408) 544-6662 Voice (408) 544-6424 Fax email: bryon_moyer@altera.com ************************************************************************ Mr. Elkind: I wanted to respond to your comments about the experience you had with In-System Programming on MAX7000S parts, and to the information you were given about solving the problem. The issue you experienced is not so much one of having a running global clock signal, as much as it is one of having too much negative overshoot (often confusingly referred to as "undershoot") on one of the global clock signals. We have observed a few cases where such excessive negative overshoot at the wrong frequency caused a failure to erase. In all such cases, successfully eliminating excessive negative overshoot (typically by adding a suitable series terminating resistor) eliminated the behavior. If you were informed by Altera that you needed to stop the clock, that is incorrect information, and I apologize for the extra work it might have put you through. Of course, stopping the clock would work, but is not required. I will work to ensure that the correct information is publicized within Altera. As far as public notification is concerned, we are putting together an application note detailing recommended design practices for successful in-system programming. Regarding future products, any changes will focus on tolerance of excessive negative overshoot. The global clocks are already disabled during programming; that is not a change. There are no plans to add CRC checking to the programming algorithm. Note that where this situation occurs, removing the part from the board and programming on a stand-alone programmer will allow the part to recover. This is clearly not convenient from an ISP standpoint, but it is a way to recover the parts as long as there hasn't been extreme contention on the board. I hope this helps clarify the situation. ===================== end of email reply ========================= **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z