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THIEBOLT Francois wrote: > Hi, > > Can someone tell me what are the FPGA Xilinx parts that could be > programmed using a simple download cable (like lattice parts) ??? > ALL Xilinx FPGAs ever made over the last 12 years ( and going to be made for the next decade ) can download their configuration from a simple download cable. That is the normal procedure during design and debugging. Peter Alfke, Xilinx ApplicationsArticle: 9051
In article <34DD1F0E.74AAA61B@ethergate.com>, &miker <Don't, Hit, Reply, Use, the, Link> wrote: > >The problem with FPGAs is that I can't find any affordable tools to >program them. Does anyone support their >programmable devices with free base development software? I don't need >anything more capable than PALASM. > I recently bought a book that included a CDROM with the student edition of MAX+PLUS II 7.2 software from Altera. The book wasn't exactly free (~90$) but I know that Altera gives the software away to Universities. I'm a strong believer in the Altera design environment. This version can only program the FLEX 10K20 and one other device but it's fully functional in every other respect: full VHDL, AHDL, schematic entry, simulation, timing, etc. If you want the book and publisher, let me know -- I don't have it with me. Tim. University of CincinnatiArticle: 9052
STU02Article: 9053
Sometime back I saw some stuff about using ATMEL re-programmable serial proms for Xilinx XC4xxx parts instead of the Xilinx one time only parts. Which devices are they & how can they be made Xilinx equivalent ? -- _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 9054
Hello,
What is the difference between System Level Gates and Logic cells?
These two terms are used widely by Xilinx in describing their products.
Example:
In their description of the XC40125XV products they say:
## 10,982 to 20,102 logic cells (4-input look-up-table and
flip-flop)
## Up to 500,000 system level gates
## Up to 448 user I/O pins
## ...
Thanks.
--
,,,
(o o)
####=================================oOO==(_)==OOO================####
## _ | ##
## (_) | M. ABERBOUR ##
## _ _ ___ | Laboratoire LIP6 / Equipe CAO-VLSI ##
## | | | | | ) | Universite Pierre et Marie Curie (Paris 6) ##
## | | | | | 6 ) | Couloir 55-65 2eme etage ##
## | | |_| | _) | 4, place Jussieu, 75252 Paris Cedex 05 ##
## | |___ | | | Tel: (33) 1 44 27 71 24 Fax: (33) 1 44 27 72 80 ##
## |_____| |_| | mailto:mourad.aberbour@lip6.fr ##
## | http://asim.lip6.fr/~mourad/ ##
####==============================================================####
Article: 9055Jeff, Check the Answers Database on the Xilinx website. From http://www.xilinx.com choose "Service & Support" and then "Answers Search". If you can't find what you're looking for, try contacting Xilinx Technical Support. Regards, Hobson Frater XilinxArticle: 9056
This is not about the timing issue which is currently being thoroughly discussed in another thread. My question is if anybody knows how registers are cleared during power-up. Is it done with global reset signal so that only those registers that do not use product term reset are cleared or it is done with the same global reset but before reading user information or perhaps they are cleared with some hidden signal? In other words I just want to know if all the registers are really cleared during power-up regardless of anything else. I will appreciate any suggestions. Thank you in advance. Mikhail MatusovArticle: 9057
Want good C compiler for 8051 micros. Prefer Keil or Franklin. Needs to be complete and <nearly> current rev. Will trade ALLMAX or FLEX700 device programmer. Your choice. Both like new. Both program thousands of devices, including micros, gal, pals, etc. Check out EETOOLS and TRIBAL MICROSYSTEMS for supported devices. FLEX700 includes adapters for ALTERA EPM7032, 7128, and 7160 FPGA's. Email if interested.Article: 9058
Timothy Oconnell wrote: > In article <34DD1F0E.74AAA61B@ethergate.com>, > &miker <Don't, Hit, Reply, Use, the, Link> wrote: > > > >The problem with FPGAs is that I can't find any affordable tools to > >program them. Does anyone support their > >programmable devices with free base development software? I don't need > >anything more capable than PALASM. > > > > I recently bought a book that included a CDROM with the student edition > of MAX+PLUS II 7.2 software from Altera. The book wasn't exactly free > (~90$) but I know that Altera gives the software away to Universities. > I'm a strong believer in the Altera design environment. This version can > only program the FLEX 10K20 and one other device but it's fully > functional in every other respect: full VHDL, AHDL, schematic entry, > simulation, timing, etc. > > If you want the book and publisher, let me know -- I don't have it with me. > > Tim. > University of Cincinnati This is a good book and a good tool. Look at the following URL for more information: http://www.altera.com/html/new/textbook.html Scott CampbellArticle: 9059
stu: : > > e.g. "Hello Mr. Vendor, I'd like to use 10,000 of your devices. I have : > > a netlist generated by my synthesis tools, and I really don't fancy : > > forking out money to see whether your silicon is up to the job, and : > > cost effective"..... : > zoltan: : > "Well Mr. Customer, $500 doesn's seem too much for a very good P&R tool, : > does it ? It routes all of our smaller chips. After all, you've forked : > out twenty grand for your synthesis, this is just peanuts. Excuse me ? : > You use unix ?! : sam: : This excuse for charging high prices is starting to get old. A $20k : synthesis tool cantarget a lot of different technologies and it doesn't have : to run on a Unix box when PCs : are starting to outperform them (not to mention the ease of maintenance and : instalation : of the software). Now if you are in this situation and you intend to use : FPGAs, you can't : directly compare different FPGAs because you need every vendor's P&R tools : running : at about $2k each. This has a tendency to lock you in to one or two : particular vendors : which can be very annoying, and you can't even be sure that you've made the : right choice : until after you spent your hard-earned cash. I think the vendors : underestimate the potential : of the small players. As ASIC methodologies are beginning to be applied by : traditional : PLD designers and as the software migrates towards PCs, I believe that a : vendor offering : free tools would capture a good part of this growing market. I hope that : the arrogance : of some of the vendors backfires on them. There aren't only big companies : with money to : waste out there. rk: it will be interesting to see how this all works out. actel has free tools for 8,000 gates and less (using their old accounting methods ;). i downloaded some quicklogic tools no charge. and i've seen no shortage of adds here for very low cost tools sets and demo boards <insert plug for r.s. here> for xilinx stuff. seems to be the trend. personally, i don't mind paying a bit for the tools, realizing that that the people developing the tools and maintaining them like to get paid. but having them free or added into device costs, i agree, allows you to do some realistic evaluations both of the tool performance and ease of use and achievable (not specmanship) device performance. most importantly, however, i'm glad i don't have to use the dongle any more. ;) -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9060
rk: it's easy enough to break out the terms and simply tell the compiler to add them up; i.e., x + 8x. i just finished an fir filter done that way and the <apparently snipped> dd: Did you check, rk, whether this produced a 9bit or a 12 bit adder? My experience was that those tools that did synthesize an adder, use a 12 bit adder, when only a 9 bit adder is required. Could be your FIR could have been smaller. rk: i didn't just tell the compiler to do 'x + 8x'. the above comment was simply stating that i do not write vhdl code with the multiplication included in it, as the original author to the post tried and that it is quite simple to do the factoring. if i remember the original post, it was commented that getting the compiler to do it efficiently was difficult. my point was that it wasn't. stu c. made a similar point. the code that i wrote factored the terms out and instructed the compiler on EXACTLY what to add up so it would do what i told it to do, not what it 'thought' what i wanted to do. since it doesn't know how to do y <= 9*x very well, i assumed it was stupid; and i kept that assumption in my final code. <pause for experiment> just for kicks i just tried the compiler. it is stupid. ------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) -------------------------------------------------------------- p.s. i used sign extension on the operands for my 2's complement arithmetic.Article: 9061
david p: : For 70% of programmable devices, there are 4 or more die changes during : the device's market life. For some devices (especially CPLDs) there can : be as many as a dozen changes. definitely agree. been using 1020's and 1280's for years and here's what we see, as an example. A1020 A1020A A1020B (1.0 um) A1020B (0.9 um) RH1020 A1280A A1280 A1280XL (0.8) A1280XL (0.6) RH1280 42MX16? through in different foundries and who knows if there are die and process revisions without a part marking change and you get more cases. and how many variants of the 22v10 are there? me, the last thing i want to worry about is if the programmer is doing the job right. -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9062
victor: : > I`m looking material about Walace tree. : > Could you help me, please? rick c.: : Two good books (I am only certain of the author - not the title) is : computer logic design? by Kai Hwang. I used that book as a reference : for writting a program for Wtree adder hardware minimization several : years ago. This book devotes an entire chapter to the subject : and is well worth seeking out. (I loaned mine out three years ago for : this very topic and haven't gotten it back yet). rk: are you referring to COMPUTER ARITHMETIC - PRINCIPLES, ARCHITECTURE AND DESIGN by Kai Hwang? good book and still use it. here's the info to whoever's (or is it whomever?;) is interested. john wiley & sons (c) 1979 isbn 0-471-03496-7 ============================================================= rich cc: : Another good multiplier reference is the very old Fairchild F100 ECL : user handbook, where an application note demonstrates a high-performance : Booth multiplier with wallace trees (at the gate level). It gives : 100% of the required info needed to quickly build and understand a : multiplier. This is an old book, let me know if you have problems : finding it. I inherited mine from a mainframe ASIC designer at my : first job out of school. rk: some of the old ecl databooks have good app notes written up on this too. i still save them, they have a lot of good engineering notes in them. good luck! -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9063
I'm currently evaluating several simulation and synthesis toolsets for FPGA development, and was wondering if anyone else had any comments. One thing that I find lacking is a benchmark of various vendors' synthesis engines. How does the Metamor engine on a particular machine with a particular design with a particular target device compare with Synplicity? Or FPGA Express? Or Exemplar? Which synthesizes fastest? Most efficient? Best use of macrocells? Fastest logic? For smaller designs (around 10K, no RAM) I have found that Metamor and FPGA Express compare favorably, but at what point does the ability of a higher end tool like FPGA Express to do things like optimize across module boundaries become a major consideration? As for simulation, I have found Aldec's Active-VHDL and Model Technology's V-System to be very good, a bit better than the PeakVHDL simulator. However, I haven't yet tried post-route simulation with them. Would anyone care to add to this thread? Please mention pricing if you have that information also. The emphasis should be on 3rd party tools as opposeed to FPGA vendor specific toolsets. Thanks, folks. Steve Mitchell sam@palmnet.net smitchell@emergevision.comArticle: 9064
Rick Filipkewicz wrote: > > Sometime back I saw some stuff about using ATMEL re-programmable > serial proms for Xilinx XC4xxx parts instead of the Xilinx one > time only parts. Which devices are they & how can they be made Xilinx > equivalent ? > > -- > > _________________________________________________________________________ > > Dr. Richard Filipkiewicz phone: +44 171 700 3301 > Algorithmics Ltd. fax: +44 171 700 3400 > 3 Drayton Park email: rick@algor.co.uk > London N5 1NU > England there parts are AT17C64,AT17C128 and AT17C256 EEPROMS Check out www.atmel.com for details Leo.Article: 9065
Dmitriy A. Gorkaev wrote: > > PLEASE IF YOU KNOW WHERE I CAN GET ACROBAT READER FOR WINDOWS3.1 IN .ZIP > AND NOT MORE THEN ONE DISKET PUT ME > > ADRESS Try www.download.com. they have what you need. Leo.Article: 9066
M. Aberbour wrote:
>
> Hello,
>
> What is the difference between System Level Gates and Logic cells?
> These two terms are used widely by Xilinx in describing their products.
>
> Example:
> In their description of the XC40125XV products they say:
>
> ## 10,982 to 20,102 logic cells (4-input look-up-table and
> flip-flop)
> ## Up to 500,000 system level gates
> ## Up to 448 user I/O pins
> ## ...
A Xilinx chip is built with elementary blocks which can implement some
logic equation.
For the X3000 series for instance, Xilinx defines the logic cell as a
4-input look-up-table (LUT). A certain Xilinx chip has a known number of
such cells. I don't remember by heart the numbers, but say a XC3020 has
128 cells, each being a 4-input LUT. That's the physical capacity of the
chip.
Now, the end user usually doesn't design directly using 4-input LUTs.
The user design could be made of an arbitrary number of gates (2-input,
3-input and more AND, OR and so on). The gate count is a universal
measure of the design complexity.
The big question for the user is to know whether his design, which
occupies a certain gate count ("system level gates") will fit in a
Xilinx chip which has a given number of cells.
For instance, if Xilinx announces 10000 logic cells, it could fit a
design of about 50000 gates. Maybe more, maybe less, gate count has been
a subject for controversy for ages.
Alain.
--
-----------------------------------------------------------------------
Alain RAYNAUD META SYSTEMS
R&D Logic Design Team Batiment Hermes
4, rue Rene Razel
Tel: (33) 01 69 35 10 00 91400 Saclay - FRANCE
E-Mail: Alain_Raynaud@mentorg.com Fax: (33) 01 69 35 10 10
-----------------------------------------------------------------------
Article: 9067
mushh@jps.net (David Decker) wrote:
:First:, sorry for my redundant post 2/13. Sometimes FreeAgent has
:trouble posting an article. It then squirels it away and for ever
:more, when ever I close FreeAgent, it tells me I have stuff to post
:and asks if I want to post now. I always try to click no, but
:eventually I use it when I'm too tired, and accidentally click yes.
:Does any one know how to kill pending posts in FreeAgent?
:
Select Window | Open Outbox
Then go down the list of messages, and delete those tagged as un-sent
(frowney face).
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: servers daveb@iinet.net.au
fingerprint 20 8F 95 22 96 D6 1C 0B 3D 4D C3 D4 50 A1 C4 34
What's all this? see http://www.iinet.net.au/~daveb/crypto.html
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Article: 9068Steve Mitchell wrote: > > I'm currently evaluating several simulation and synthesis toolsets > for FPGA development, and was wondering if anyone else had any comments. > One thing that I find lacking is a benchmark of various vendors' > synthesis engines. How does the Metamor engine on a particular machine > with a particular design with a particular target device compare with > Synplicity? Or FPGA Express? Or Exemplar? Which synthesizes fastest? > Most efficient? Best use of macrocells? Fastest logic? For smaller > designs (around 10K, no RAM) I have found that Metamor and FPGA Express > compare favorably, but at what point does the ability of a higher end tool > like FPGA Express to do things like optimize across module boundaries > become a major consideration? If you goto http://www.eet.com & then search on print articles and perform a search on synplicity, there is an article comparing synplicity to exemplar. It was done by some designers trying to compile a part and is their experience with their design. It doesn't give any feature comparisons or a general comparison of how well the software performs it's only a specific device. I can say from my experience on one design with synoposis FPGA compiler & synplicity, that synplicity gave a smaller/faster design. -- Regards Glenn Eng glenn.eng@nortel.com (remove "delete." in header to reply")Article: 9069
hello, I wonder wether there is someone out there to help me.......!!!! I am doing a project on reconfigurable compiler for general purpose computing.... I need to find out more about the architecture of a cross-bar switch....... please help if you can!!! Thank you MouradArticle: 9070
Is there anybody out there who has targeted a Virtual Chips PCI core to a Xilinx, Altera or other FPGA? We would like to prototype our product before designing an ASIC.Article: 9071
Peter Alfke <peter.alfke@xilinx.com> wrote: >THIEBOLT Francois wrote: >> Hi, >> >> Can someone tell me what are the FPGA Xilinx parts that could be >> programmed using a simple download cable (like lattice parts) ??? >> >ALL Xilinx FPGAs ever made over the last 12 years ( and going to be made >for the next decade ) can download their configuration from a simple >download cable. That is the normal procedure during design and >debugging. Not true. You can't download to the 7200/7300 familty. They require a special programmer. Tim Olmstead webmaster of the CP/M Unofficial web page email : timolmst@cyberramp.net http://cdl.uta.edu/cpmArticle: 9072
Peter Alfke <peter.alfke@xilinx.com> wrote: >THIEBOLT Francois wrote: >> Hi, >> >> Can someone tell me what are the FPGA Xilinx parts that could be >> programmed using a simple download cable (like lattice parts) ??? >> >ALL Xilinx FPGAs ever made over the last 12 years ( and going to be made >for the next decade ) can download their configuration from a simple >download cable. That is the normal procedure during design and >debugging. Sorry biout' that. You did say FPGA. Tim Olmstead webmaster of the CP/M Unofficial web page email : timolmst@cyberramp.net http://cdl.uta.edu/cpmArticle: 9073
Mikhail Matusov <mmatusov@ics-ltd.com> wrote: >This is not about the timing issue which is currently being thoroughly >discussed in another thread. > >My question is if anybody knows how registers are cleared during >power-up. Is it done with global reset signal so that only those >registers that do not use product term reset are cleared or it is done >with the same global reset but before reading user information or >perhaps they are cleared with some hidden signal? > >In other words I just want to know if all the registers are really >cleared during power-up regardless of anything else. > > >I will appreciate any suggestions. Thank you in advance. > > >Mikhail Matusov I believe that the flops are designed to power up in the reset state (or they implement an extra clear input only for power up). You can be assured that all your registers will be clear right after powering up the device. -- richard_damon@iname.com (Redirector to my current best Mailbox) rdamon@beltronicsInspection.com (Work Adddress) Richad_Damon@msn.com (Just for Fun)Article: 9074
These would be the Atmel 17xxx parts which are already Xilinx pin equivalent. For data sheets, app notes, samples etc. check out http://www.atmel.com/atmel/products/prod22.htm regards, tom Rick Filipkewicz wrote: > > Sometime back I saw some stuff about using ATMEL re-programmable > serial proms for Xilinx XC4xxx parts instead of the Xilinx one > time only parts. Which devices are they & how can they be made Xilinx > equivalent ? >
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