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We are using Cadence Design Tools -- 97a which include Xilinx/Cadence
interface program and here are the platform and software ready,
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hardware: a couple of SunSPARCs- Ultra 30 with one parallel port and two
serial ports
Software: Full featured Cadence 97a (including Concept- a schematic
editor supported by Xilin/Cadence interface), and xilinx m1.3.
language: Verilog HDL.
Simulator: Verilog-XL, Synergy.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Can anyone point to a FPGA/FPAA board and chips which can accomondate
a wide range of advanced multimedia applications from speech, image
processing to communication systems. i'll be more than grateful. The
current budget is $500.
Best regards
vicky
Article: 9076Rick Carmichael wrote: > Victor Levandovsky wrote: > > > > Hi! > > > > I`m looking material about Walace tree. > > Could you help me, please? > > > > Regardless, > > > > Victor Levandovsky > > > > vicNS@alpha.podol.khmelnitskiy.ua > > > > Remove NS if reply > > Two good books (I am only certain of the author - not the title) is > computer logic design? by Kai Hwang. I used that book as a reference > for writting a program for Wtree adder hardware minimization several > years ago. This book devotes an entire chapter to the subject > and is well worth seeking out. (I loaned mine out three years ago for > this very topic and haven't gotten it back yet). > > Another good multiplier reference is the very old Fairchild F100 ECL > user handbook, where an application note demonstrates a high-performance > Booth multiplier with wallace trees (at the gate level). It gives > 100% of the required info needed to quickly build and understand a > multiplier. This is an old book, let me know if you have problems > finding it. I inherited mine from a mainframe ASIC designer at my > first job out of school. > > Warm Regards, > rick Also try: "Low Power Digital VLSI Design, Circuits and Systems" by Abdellatif Bellaouar and Mohamed I. Elmasry, Kluwer Academic Publishers. 1995 ISBN 0-7923-9587-5 There's a whole subsection (7.2.4) on Wallace tree multipliers under the Parallel Multipliers section. Edwin GrigorianArticle: 9077
In article <34EA49C3.234548C8@sbee.sunysb.edu>, Scott Campbell <nospam@sbee.sunysb.edu> wrote: >Timothy Oconnell wrote: > >> In article <34DD1F0E.74AAA61B@ethergate.com>, >> &miker <Don't, Hit, Reply, Use, the, Link> wrote: >> > >> >The problem with FPGAs is that I can't find any affordable tools to >> >program them. Does anyone support their >> >programmable devices with free base development software? I don't need >> >anything more capable than PALASM. >> > >> >> I recently bought a book that included a CDROM with the student edition >> of MAX+PLUS II 7.2 software from Altera. The book wasn't exactly free >> (~90$) but I know that Altera gives the software away to Universities. >> I'm a strong believer in the Altera design environment. This version can > >This is a good book and a good tool. Look at the following URL >for more information: > >http://www.altera.com/html/new/textbook.html > >Scott Campbell > > I wish I would've had that link when I was trying to track down the book -- it took me a couple months. I knew of its existence and nothing else. I've hobbied around with the software and Nova Engineering's (www.novaengr.com) Constellation Board which has a Flex 10K20 on it. The power of the software and the flexibility of this board make a beautiful comination. Tim O'Connell toconnel@ddt.occ.uc.eduArticle: 9078
>(www.novaengr.com) Constellation Board which has a Flex 10K20 on it.
oops -- I think I meant www.nova-engr.com
>beautiful comination.
and for that matter I think I meant combination
Needing an editor,
Tim.
Article: 9079
Glenn Eng <glenn.eng@nortel.NOSPAMcom> writes:
> Steve Mitchell wrote:
> >
> > I'm currently evaluating several simulation and synthesis toolsets
> > for FPGA development, and was wondering if anyone else had any comments.
> > One thing that I find lacking is a benchmark of various vendors'
> > synthesis engines. How does the Metamor engine on a particular machine
> > with a particular design with a particular target device compare with
> > Synplicity? Or FPGA Express? Or Exemplar? Which synthesizes fastest?
> > Most efficient? Best use of macrocells? Fastest logic? For smaller
> > designs (around 10K, no RAM) I have found that Metamor and FPGA Express
> > compare favorably, but at what point does the ability of a higher end tool
> > like FPGA Express to do things like optimize across module boundaries
> > become a major consideration?
>
> If you goto http://www.eet.com & then search on print articles and
> perform
> a search on synplicity, there is an article comparing synplicity to
> exemplar.
> It was done by some designers trying to compile a part and is their
> experience
> with their design. It doesn't give any feature comparisons or a general
> comparison of how well the software performs it's only a specific
> device. I can
> say from my experience on one design with synoposis FPGA compiler &
> synplicity,
> that synplicity gave a smaller/faster design.
First off, my own biases. I use Exemplar. I have used Synplify (for
over a year). Synplify is faster, but not significantly so. Worst
case, Exemplar might take twice as long. (I've also used the Metamor
and unix based Synopsys FPGA Compiler. It's not worth writing much
more about either of the two.)
It was fairly obvious to anyone who regularly uses Exemplar that the
version the authors used in the EETimes article was fairly old. The
Exemplar tools have sped up _substantially_. I mean, things that might
once have taken 1/2 an hour are now compiled in less than a minute.
The integration with the backend P&R tools keeps getting better.
Exemplar writes edif and xnf netlists for the backend P&R tools but
can do more. Place and route constraints can be automatically written
for Xilinx, Altera, and ORCA from the synthesis constraints. After
place and route, the final netlists and SDF files can be read back in
for schematic viewing and static timing analysis.
The current version of Exemplar Logic tools is 4.2.1. If I could make
a summary of the past two releases it would be thus:
4.0 to 4.1 -> significant speed up in compile times
4.1 to 4.2 -> significant quality of results improvement through
more enhanced timing driven synthesis.
I have found that Synplify and Exemplar both beat Metamor and FPGA
Express. If in doubt, try changing the timing constraints in FPGA
Express and see how the logic changes (or does not). I have to hand it
to FPGA Express, their timing spreadsheet certain _looks_ impressive,
but I haven't seen it affect anything but the timespecs for P&R.
The reason you don't see benchmarks is quite simple. First, these
tools are _always_ changing; constantly improving. Second, there are
sooo many variables to evaluate these tools on. Like VHDL vs Verilog
subsets, constraints, ease of use, scripting, ad nauseum... While one
tool may be better at one foundry, the other tool might be better at
another foundry. By the time anyone took it upon themselves to
evaluate all the parameters, the tables would be turned with new
versions of the tools. This is where we get the expression "YMMV" (you
mileage may vary).
It comes down to several factors. Evaluate the tools with your own
designs and target to your technology. Check out the technical
support. And be wary of any EETimes info-mercials. Defy the marketing
weenies who espouse "Perception is reality".
Article: 9080Hi Does anybody know where I can find information about it? Thanks in advance, beniArticle: 9081
In article <34EA49C3.234548C8@sbee.sunysb.edu>
nospam@sbee.sunysb.edu "Scott Campbell" writes:
> Timothy Oconnell wrote:
>
> <<snip>>
> >
> > I recently bought a book that included a CDROM with the student edition
> > of MAX+PLUS II 7.2 software from Altera. The book wasn't exactly free
> > (~90$) but I know that Altera gives the software away to Universities.
> > I'm a strong believer in the Altera design environment. This version can
> > only program the FLEX 10K20 and one other device but it's fully
> > functional in every other respect: full VHDL, AHDL, schematic entry,
> > simulation, timing, etc.
> >
> > If you want the book and publisher, let me know -- I don't have it with me.
> >
> > Tim.
> > University of Cincinnati
>
> This is a good book and a good tool. Look at the following URL
> for more information:
>
> http://www.altera.com/html/new/textbook.html
>
> Scott Campbell
>
It's not, it's awful. The student version of MaxplusII is the _ONLY_ reason
to buy it. Most of the discussion of FPGA & CPLD families is a straight reprint
of Altera's databook, but with poorer typsetting and ocasional references to
Xylinx (mainly lipservice). The quality of diagrams is
generally poor, and ocassionally the diagrams are incorrect.
What is _MUCH_ worse is that it has been stuck in a time warp for about two
years. All ability to set fitter options such as pins, cliques etc was taken
out of TDF files long ago. Neither does the book mention Altera's later device
families, e.g. Max9k, Flex10k.
The most grevious sin committed is that there is no mention of Altera's LPM
building blocks whatsoever. As these are what make using Altera such a joy
compared to dogs like CUPL v4.7, I cannot understand why this is omitted. Sure,
there is reference to the standard TTL function libraries, but in nearly all
cases using the appropriate LPM is so much easier, and flexible.
The final point is that I wonder whether the authors ever tested their
temperature controller design? It looks to me that they made some very dodgy
assumptions about what would happen at power-up, and what temperature the probe
might be seeing.
My only connection is as a satisfied Altera customer, and a pissed-off buyer of
that book. It just really lets down Altera's position and image.
--
Steve Dewey
Steve@s-dewey.demon.co.uk
Too boring to have an interesting or witty .sig file.
Article: 9082
There has been so much complaining about the "high cost of software"
that I want to bring this good deal to your attention.
XC4000 and XC9500 M1.3-based software
plus a good tutorial book for less than $ 70.
If you are interested, you can find a description at
http://www.prenhall.com/search.html
enter
xilinx
in the search box, then click on
Xilinx Student Edition
If you want to buy it, you might go to
http://www.amazon.com
enter the keyword
xilinx
into the search box near the bottom of the page, press search and read:
The Xilinx Student Edition ~ Ships in 2-3 days
Prentice Hall / Paperback / Published
1997
Our Price: $66.67
Good deal .
Just the tutorial book might be worth the money, so the software is
"free".
Presently, the upper device-size limit is XC4008 ( XC4000E as well as
XC4000XL ).
Peter Alfke, Xilinx Applications
Article: 9083jim granville wrote: So, what do the XILINX 95xx CPLDs do ? > Do they POR load Macrocell info, like the others ? yes > > > If you remove power, to say 1-2V, then reapply, does the part > still work ? yes > We at Xilinx do not believe in keeping the user in the dark. So you can read about this on page 18/19 of the XC9500 data sheet ( page 3-18 /19 of our 1998 data book ), and I quote: "The XC9500 devices are well-behaved under all operating conditions. During power-up, each XC9500 device employs internal circuitry which keeps the device in the quiescent state until the Vccint supply voltage is at a safe level, ~3.8 V, During this time, all device pins and JTAG pins are disabled, and all device outputs are disabled, with the IOB pull-up resistors of ~10 kilohm enabled. When the supply voltage reaches a safe level. all user registers become initialized ( typically within 100 microsec for XC9538 through XC95144, 200 µs for XC95216, and 300µs for XC95288) and the device is then immediately available for operation..." Those 100 to 300 microsecond are used for the sequential transfer that I described in a previous posting. And there is a figure that explains the behavior with rising and falling supply voltage. I hope this answers the questions, and we did not need any help from the front of the alphabet.. Peter Alfke, Xilinx ApplicationsArticle: 9084
peter a.: : There has been so much complaining about the "high cost of software" : that I want to bring this good deal to your attention. : : XC4000 and XC9500 M1.3-based software : plus a good tutorial book for less than $ 70. : : If you are interested, you can find a description at : : http://www.prenhall.com/search.html : : enter : xilinx : in the search box, then click on : Xilinx Student Edition rk: here's part of the description: The book provides step-by-step instructions for designing and downloading multiple designs into Xilinx FPGA devices and complex programmable logic displays (CPLDs) as well as ... guess i gotta keep more up-to-date ;) -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9085
Dear All, I am a new to this field. I am interested in designing a fast floating point unit (single precision is okay) on Xilinx 4000s part. Can anyone have experience building his/her own floating point unit on FPGAs? Is there any cook book that I can find whatever I need to implement such design on Xilinx FPGA? Thanks a lot. KelvinArticle: 9086
--------------9F516CDCF44FD3FD28D1208B Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit M. Aberbour wrote: > Hello, > > What is the difference between System Level Gates and Logic cells? > > In their description of the XC40125XV products they say: > > ## 10,982 to 20,102 logic cells (4-input look-up-table and > flip-flop) > ## Up to 500,000 system level gate Watch out, the upper numbers of 20,102 and 500.000 refer not to the XC40125XV, but to the upper limit of the yet-to-be-introduced bigger members of this family. So let me explain the 10,982 Logic Cells, 147 k bits of RAM and 265000 max logic gates. This is a mixture of engineering specifications and marketing. Engineering specifications: The XC40125XV has a 68 x 68 array of CLBs = 4624 CLBs Each of these CLBs has 32 RAM bits = 147 968 RAM bits total. No ifs and no buts. Now we get into marketing: Since this is a competitive world, our users want to compare different manufacturers, but the structures are not the same. Altera puts eight LUTs in a block, Lucent puts 4 and we put 2 LUTs into a CLB, but everybody's LUTs are more or less identical. So Xilinx decided to standardize the nomenclature and emphasize not CLBs but rather Logic Cells, as a lingua franca for FPGAs. Good idea! Then marketing saw the third LUT in our CLB and gave it a value of 3/8 of a Logic Cell, so the whole CLB is worth 2.375 LCs. Obviously, we can argue about this addition, buit it is true that one can use the third LUT for really nice and efficient solutions. :-) Multiply the 4624 CLBs by 2.375 and you get 10 982 Logic Cells. What is that in ASIC gates? There is no scientific answer, because it depends on the design. What is the LUT being used for, is the flip-flop being used at all, and what if you use the LUT as RAM ? Assume that every LUT is worth 6 gates and every flip-flop is worth 6 gates, then every Logic Cell is worth 12 gates ( sometimes more, sometimes less ). 12 gates times 10 982 LCs makes a bare-bone gate-count of 131 784, and that is reflected in the name of the device. We are conservative and round it down a bit. :-) But there is the RAM in the LUT, and if only 25% of them are really used as RAM, these LUTs are not worth 6 gates, but rather 64 gates ( 16 bits with 4 bits per RAM cell, again, very conservative, ignoring the select structure and the read/write circuitry). That means, we must add another 58 gates times 25% of 9248 LUTs, which means another 134 096 gates, for a total of 265 880 logic gates. And we say explicitly that this assumes 20 to 30 % of the CLBs being used as RAM. That's how the XC40125XV got its name and its gate-count range of 125000 to 265000 gates. It is an attempt to bring some sanity to the gate-count confusion. Users will never agree about these assumption, and if you don't want to compare different manufacturers, then you can forget the whole thing and just stick with CLBs and RAM bits, for they are physical and thus non-controversial. Peter Alfke, Xilinx Aplications --------------9F516CDCF44FD3FD28D1208B Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <BODY BGCOLOR="#FFFFFF"> M. Aberbour wrote: <BLOCKQUOTE TYPE=CITE>Hello, <P>What is the difference between System Level Gates and Logic cells? <P>In their description of the XC40125XV products they say: <P> ## 10,982 to 20,102 logic cells (4-input look-up-table and <BR>flip-flop) <BR> ## Up to 500,000 system level gate</BLOCKQUOTE> Watch out, the upper numbers of 20,102 and 500.000 refer not to the XC40125XV, but to the upper limit of the yet-to-be-introduced bigger members of this family. <P>So let me explain the 10,982 Logic Cells, 147 k bits of RAM and 265000 max logic gates. <BR> <BR>This is a mixture of engineering specifications and marketing. <BR> <H3> Engineering specifications:</H3> The XC40125XV has a 68 x 68 array of CLBs = 4624 CLBs <BR>Each of these CLBs has 32 RAM bits = 147 968 RAM bits total. <BR>No ifs and no buts. <BR> <H3> Now we get into marketing:</H3> Since this is a competitive world, our users want to compare different manufacturers, but the structures are not the same. Altera puts eight LUTs in a block, Lucent puts 4 and we put 2 LUTs into a CLB, but everybody's LUTs are more or less identical. <P>So Xilinx decided to standardize the nomenclature and emphasize not CLBs but rather Logic Cells, as a <I>lingua franca</I> for FPGAs. Good idea! <P>Then marketing saw the third LUT in our CLB and gave it a value of 3/8 of a Logic Cell, so the whole CLB is worth 2.375 LCs. <BR>Obviously, we can argue about this addition, buit it is true that one can use the third LUT for really nice and efficient solutions. :-) <P>Multiply the 4624 CLBs by 2.375 and you get 10 982 Logic Cells. <BR> <H3> What is that in ASIC gates?</H3> There is no scientific answer, because it depends on the design. What is the LUT being used for, is the flip-flop being used at all, and what if you use the LUT as RAM ? <P>Assume that every LUT is worth 6 gates and every flip-flop is worth 6 gates, then every Logic Cell is worth 12 gates ( sometimes more, sometimes less ). 12 gates times 10 982 LCs makes a bare-bone gate-count of 131 784, and that is reflected in the name of the device. We are conservative and round it down a bit. :-) <P>But there is the RAM in the LUT, and if only 25% of them are really used as RAM, these LUTs are not worth 6 gates, but rather 64 gates ( 16 bits with 4 bits per RAM cell, again, very conservative, ignoring the select structure and the read/write circuitry). <BR>That means, we must add another 58 gates times 25% of 9248 LUTs, which means another 134 096 gates, for a total of 265 880 logic gates. And we say explicitly that this assumes 20 to 30 % of the CLBs being used as RAM. <P>That's how the XC40125XV got its name and its gate-count range of 125000 to 265000 gates. It is an attempt to bring some sanity to the gate-count confusion. <P>Users will never agree about these assumption, and if you don't want to compare different manufacturers, then you can forget the whole thing and just stick with CLBs and RAM bits, for they are physical and thus non-controversial. <P>Peter Alfke, Xilinx Aplications </BODY> </HTML> --------------9F516CDCF44FD3FD28D1208B--Article: 9087
My apologies for neglecting to inform all respondees to delete the "nospam" reference from my return email address in my previous post. I want a good C compiler for 8051 micros. Prefer Keil or Franklin. Needs to be complete and <nearly> current revision. Will trade you either ALLMAX or FLEX700 device programmer, your choice. Both like new, both program thousands of devices including micros, pals, etc. Check out EETOOLS and TRIBAL MICROSYSTEMS web pages for supported devices. FLEX700 includes adapters for ALTERA EPM7032, 7128 & 7160 FPGA's. Don't forget to delete the "nospam" reference in the return e,ail address. Cheers.Article: 9088
Okay... Peter is just mad because his company is now the number TWO programmable logic supplier in the world. I think Peter is an excellent resource for detailed Xilinx technical information; perhaps he should stick with his strengths... Also, Peter, there may indeed be no guts on Orchard Parkway, considering Altera moved to 101 Innovation Drive some months ago. You remember innovation, don't you? Hint: think back before the XC5200 and XC9500 families that looked curiously like Flex8000 and Max7000S... Sorry to everyone for the non-technical post; I didn't take the first shot however. I hope it was at least entertaining! Wayne Turner Altera Field Applications (posting from home and speaking for myself) Peter Alfke wrote: > [snipped...] > It is sad that there is nobody at Altera willing to stick his head out. > Of course they are monitoring this newsgroup, but there's no guts on > Orchard Parkway... > > It's fun to needle somebody who is too afraid to come out of hiding, and > relies on being rescued, occasionally, from New Zealand... > > Peter Alfke, Xilinx ApplicationsArticle: 9089
I'd like to use Xilinx XACT 6 with old Orcad IV. I've found sources of SDT and VST unified libraries for XACT 5.0 (on CD) and compiled them without problems. But I wonder whether they are equivalent to original ones. Haven't checked it yet. Another problem is that Xilinx technical support says one should upgrade to OrCad 386+ as soon as possible, because the source files has not been thoroughly tested. It is impossible for me, at least for now. Has anyone experience with such configuration? Regards Chris -- Christopher Rozniak Gdansk, Poland, Europe, Earth E-mail: k.rozniak@XXX.ien.gda.pl remove anty-spam XXX. to emailArticle: 9090
INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN 1998
Embassy Suites, Monterey, CA
April 6-8, 1998
http://www.ee.iastate.edu/~ispd98
ADVANCE PROGRAM
The International Symposium on Physical Design provides a high-quality forum
for the exchange of ideas and results in critical areas related to the physical
design of VLSI systems. This meeting evolved from the the ACM/SIGDA Physical
Design Workshops held during the years 1987-1996. The first Symposium in 1997
was highly successful and drew such a large number of attendees that
registration had to be closed a month early. The scope of this symposium
includes all aspects of physical design, from interactions with behavior- and
logic-level synthesis, to back-end performance analysis and verification.
This year's Symposium focuses on the challenges of
high-performance deep-submicron design, as well as the necessary
interactions between physical design and higher-level synthesis tasks.
An outstanding slate of technical papers has been selected for oral
and poster presentation. These developments are complemented by invited
presentations that set forth the contexts and visions for key areas
-- process technology, system architecture, circuit design and design
methodology -- with an emphasis on their implications for relevant
R&D in physical design. The Symposium concludes with a panel of
leading experts who each present their unique perspectives as to the
critical R&D needs of the field.
MONDAY, April 6
0915-0930 Welcome
M. Sarrafzadeh, General Chair (Northwestern)
D. F. Wong, Program Chair (UT-Austin)
0930-1030 Keynote Address
"Design of a 1GHZ Processor"
TBD
1030-1100 BREAK
1100-1230 Session 1: Floorplanning and Placement
Chairs: C.K. Cheng (UCSD) and Jochen Jess (Eindhoven)
"On Wirelength Estimations for Row-Based Placement"
A.B. Kahng, S. Mantik, I.L. Markov, A. Zelikovsky (UCLA)
"Performance-Driven Soft-Macro Clustering and Placement by
Preserving HDL Design Hierarchy"
H.-P. Su, A.C.-.H. Wu, Y.-L. Lin (Tsing Hua)
"Nostradamus: A Floorplanner of Uncertain Design"
K. Bazargan, S. Kim, M. Sarrafzadeh (Northwestern)
1230-1430 Lunch (Pinot Noir Room)
Special Address: "Impact of Web Technologies on EDA System
Architectures"
R. Newton (UCB)
1430-1600 Tutorial: "Timing Metrics for Physical Design of Deep
Submicron Technologies "
Presenter: L. Pillegi (CMU)
Panelists: J. Cong (UCLA)
S. Otto (Intel)
A. Yang (Washington)
1600-1630 BREAK
1630-1730 Special Address: "Moore's Law and Physical Design of ICs"
W. Maly (CMU)
1730-1830 Session 2: Interconnect Optimization
Chairs: M. Alexander (Washington State) and
Y.-L. Lin (Tsing Hua)
"Greedy Wire-Sizing is Linear Time"
C.C.N. Chu, D.F. Wong (UT-Austin)
"An Efficient Technique for Device and Interconnect
Optimization in Deep Submicron Designs"
J. Cong, L. He (UCLA)
1900-2100 Dinner (Pinot Noir Room)
Special Address:
"Consorting with the Consortia: Cooperating For Fun & Profit"
W. H. Joyner (SRC)
TUESDAY, April 7
0830-0930 Session 3: Layout Methodologies for RF Circuits
Chairs: M. Pedram (USC) and W. Dai (UCSC)
"Device-Level Early Floorplanning Algorithms for RF Circuits"
M. Aktuna, R.A. Rutenbar, L. R. Carley (CMU)
"A Layout Approach to Monolithic Microwave IC"
A. Nagao, T. Kambe (SHARP); I. Shirakawa (Osaka)
0930-1030 Session 4: Framework and Benchmarks
Chairs: D. Hill (Synopsys) and L. Jones (Motorola)
"CHDStd--Application Support for Reusable Hierarchical
Interconnect Timing Views"
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher,
A. Chokhavtia (Sematech); D. Cottrell, D. Mallis
(Silicon Integration Initiative); S. DasGupta,
J. Morrell (IBM)
"The ISPD Circuit Benchmark Suite"
C.J. Alpert (IBM)
1030-1100 BREAK
1100-1230 Panel: "Given that SEMATECH is levelling the semiconductor
technology playing field, will corporate CAD (in
particular, PD) tools continue to serve as enablers
differentiators of technology in the future?"
Organizer: S. DasGupta (IBM)
Panelists:
B. Beers, IBM
M. Khaira, Intel
R. Abrishami, Fujitsu Microelectronics
J. Hutt, Synopsys
L. Sheffer, Cadence
D. Guiou, Mentor Graphics
E. Hsieh, Avant!
1230-1330 Lunch (Atrium Court)
1330-1430 Session 5: "PD for Manufacturability"
Chairs: M. Weisel (Intel), R. Rutenbar (CMU)
"Critical Area Computation--A New Approach"
E. Papadopoulou (IBM), D.T. Lee (Northwestern)
"Filling and Slotting: Analysis and Algorithms"
G. Robins, A. Singh (Virginia); H. Wang (UCLA);
A. Zelikovsky (Virginia)
1430-1530 Special Address: "Global Wires: Harmful"
R. Otten (Delft)
1530-1600 BREAK
1600-1645 Session 6: Poster Presentations
Chairs: E. Yoffa (IBM) and G. Robins (Virginia)
"Partioning Using Second-Order Information and Stochastic-Gain
Functions"
S. Dutt (UI-Chicago), H. Theny (Intel)
"A Parallel Algorithm for Zero Skew Clock Tree Routing"
Z. Xing, P. Banerjee (Northwestern)
"On Convex Formulation of the Floorplan Area Minimization
Problem"
T. Chen, M. Fan (Georgia Tech)
"A Patten Matching Algorithm for Verification and Analysis
of Very Large IC Layouts"
M. Niewcazas, W. Maly, A. Strojwas (CMU)
"LIBRA--A Library-Independent Framework for Post-Layout
Performance Optimization"
R. Huang (UCSB), Y. Wang (Avant!), K.-T. Cheng (UCSB)
"Estimation of Maximum Current Envelope for Power Bus
Analysis and Design"
S. Bobba, I.N. Hajj (Illinois)
"New Efficient Algorithms for Computing Effective Capacitance"
S. Muddu (SGI)
"Calculation of Ramp Response of Lossy Transmission Lines Using
Two-Port Network Functions"
P. Heydari, M. Pedram (USC)
"Switch-Matrix Architecture and Routing for FPDs"
G.-M. Wu, Y.-W. Chang (Chiao-Tung)
1645-1745 Poster Session
1900-2200 Banquet
WEDNESDAY, April 8
0830-1000 Session 7: Efficient Representation in Placement
Chairs: R. Otten (Delft) and C. Sechen (Washington)
"Sequence-Pair Based Placement Method for Hard/Soft/Pre-placed
Modules"
H. Murata, E.S. Kuh (UCB)
"Rectilinear Block Placement using Permutation-Pair"
J. Xu, C.K. Cheng (UCSD)
"Topology Constrained Rectilinear Block Packing for Layout
Reuse"
M. Kang, W. Dai (UCSC)
1000-1030 BREAK
1030-1200 PANEL: "Process development and its impact on Physical Design"
ORGANIZER: N. Sherwani (Intel)
Panel members: J. Cong (UCLA)
D. Lapotin (IBM)
others TBD
1230-1400 Lunch (Pinot Noir Room)
1400-1530 Tutorial: "Why Clustering Is the Key to Partitioning"
Presenter: A. Kahng (UCLA)
Panelists: C. Alpert (IBM)
G. Janac (Cadence)
J. Lillis (UI - Chicago)
1530-1700 Session 8: Routing Algorithms
Chairs: J. Cong (UCLA) and J. Fishburn (Lucent)
"Chip-Level Area Routing"
L.-C. Liu, H.-P. Tseng, C. Sechen (Washington)
"Routing Tree Topology Construction to Meet Interconnect
Timing Constraints"
H. Hou (Iowa State), S. Sapatnekar (Minnesota)
"Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips"
T. Stoehr, M. Alt (IBM); A. Hetzel (Bonn), J. Koehl (IBM)
1700 Symposium Closes
%%==========================================================================%%
%% Symposium Organization %%
%%==========================================================================%%
General Chair
M. Sarrafzadeh (Northwestern)
Past Chair
A. B. Kahng (UCLA)
Steering Committee
J. P. Cohoon (Virginia)
S. DasGupta (IBM)
M. Marek-Sadowska (UC Santa Barbara)
B. Preas (Xerox PARC)
E. Yoffa (IBM)
Technical Program Chair
D. F. Wong (UT-Austin)
Technical Program Committee
M. J. Alexander (Washington State) C. K. Cheng (UC San Diego)
J. Cong (UCLA) W. W.-M Dai (UC Santa Cruz)
J. Fishburn (Lucent) D. Hill (Synopsys)
J. A. G. Jess (Eindhoven) L. Jones (Motorola)
S. M. Kang (Illinois) Y.-L. Lin (Tsing Hua)
M. Pedram (USC) R. Rutenbar (CMU)
C. Sechen (Washington) M. Wiesel (Intel)
T. Yoshimura (NEC)
Publication Chair
D. Hill (Synopsys)
Panel Chair
N. Sherwani (Intel)
Local Arrangements Chair
R.-S. Tsay (Axis Systems)
Publicity Chair
S. Sapatnekar (Minnesota)
Treasurer
S. Souvannavong
Sponsors
ACM Special Interest Group on Design Automation
in cooperation with
IEEE Circuits and Systems Society and IEEE Computer Society
Additional Support From:
Avant! Corporation
Ambit Design Systems
Intel Corporation
%%==========================================================================%%
%% Hotel Accommodations and Travel %%
%%==========================================================================%%
ISPD-98 is being held at the Embassy Suites Monterey Bay in Monterey,
California, located on the beautiful Monterey Peninsula, two blocks from
the beach, at the intersection of Canyon Del Rey and Del Monte Boulevard.
The address is
Embassy Suites Monterey Bay Hotel & Conference Center
1441 Canyon Del Rey
Seaside, California 93955
Tel: (408) 393 1115
Fax: (408) 393 1113
For hotel reservations, call (408) 393 1115 or (800)362 2779.
A block of rooms is being held for the nights of Sunday through Wednesday
(April 5 through April 8). Room rates are $125 per night for a single room
and $145 per night for a double room. Any individual cancellations within 72
hours from the date of arrival will be billed for (1) night's stay, plus tax.
+---------------------------------------------------------+
| Please make room reservations directly with the hotel |
| at either 1-408-393-1115 or 1-800-362-2779, mentioning |
| ``ISPD'' to get the special rate. |
+---------------------------------------------------------+
The number of rooms available at this rate is limited, and are only being
held through MARCH 9. Early room reservation is highly recommended.
%%==========================================================================%%
%% ISPD-98 Advance Registration Form %%
%%==========================================================================%%
Name: _______________________________________________________
Company/University: _________________________________________
Responsibility/Title: _______________________________________
Address: ____________________________________________________
City: _______________________________ State: ________________
Country: ______________________ Postal Code: ________________
Phone: ________________________ Fax: ________________________
Email: ______________________________________________________
Food Choices:
[ ] Vegetarian meals
[ ] Non-vegetarian meals
[ ] Either one is fine
Advance Late
(Through March 10) (After March 10)
ACM/IEEE Members [ ] $350 [ ] $425
Non-Members [ ] $425 [ ] $500
Full-Time Students [ ] $175 [ ] $225
Student ID is required if registering as a student.
ACM or IEEE Member No. _____________________________
Registration fee includes meals and Banquet.
Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/International Symposium on
Physical Design''. Payment may also be made with credit card (circle):
Mastercard Visa American Express
Credit Card # _______________________________________________
Expiration Date: ______________ Total Payment: ______________
Name as it appears on credit card: __________________________
Signature: ___________________________ Date: ________________
Please mail or FAX (credit card only) your completed registration form to:
ISPD-98 Symposium Registration
Sally Souvannavong, Treasurer
P.O. Box 395
Pullman, WA 99163-0395
FAX: 1-509-332-6118
Email registration will not be accepted. Cancellations must be in writing
and must be received by March 24, 1998. Questions concerning symposium
registration should be directed to Sally Souvannavong at 1-509-334-3162,
Email: ispd98@eecs.wsu.edu.
Article: 9091>There has been so much complaining about the "high cost of software" >that I want to bring this good deal to your attention. > >XC4000 and XC9500 M1.3-based software >plus a good tutorial book for less than $ 70. Why not M1.4? I think shipping a bug-fixed version of any program it would have reduced your tech support workload, and if Xilinx really wanted to take out the X3000 support from this cut-price version (why?) they could have done that also. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 9092
PENG LIU wrote: > > Hi: > I used altera EPF81500-240AQC2 designing a board. There is a counter in > the fpga, but why I mesure the counter's output, I found that if I > mesuare another signal, then the counter's output is right, when I take > down the probe on another signal, the counter's lowest bit lost some > pulse. > who meet the same problem. I need help!! > > yours. > > ws. Are your counters "LPM" counters? I had a problem with using LPM counters which I never did resolve (just spun my own instead). They'd appear to stop counting for unknown reasons. Fully synchronous inputs. Altera 10K parts. - Gary.Article: 9093
DEADLINE: FEBRUARY 25 1998 IEEE International Workshop on MEMORY Technology, Design, and Testing August 24--25, 1998 CALL FOR PAPERS San Jose, California Fairmont Hotel Sponsored by: IEEE Computer Society, Technical Committee on Test Technology and Technical Committee on VLSI. In cooperation with: IEEE Solid-State Circuit Society. The workshop will include all aspects of memory design, process technologies, and testability related topics. Memory circuit designs, cell structures, fabrication processes, design architectures and related testing and verification methods for SRAM, DRAM, Flash and non-volatile memories, EPROM, EEPROM, embedded memories, logic-enhanced and FIFO memories, 3-D memories, and content addressable memories. Representative topics are: Memory fault modeling and test generation Built-in test and testable designs for memories Concurrent checking and memory fault diagnosis Quality and reliability issues Space applications and radiation hardening issues Memory failure and yield analysis High-speed, innovative designs Fault isolation, reconfiguration and repair Multiported, multibuffered memories Logic-enhanced and programmable memories Application-specific and embedded memories Multimegabit SRAMs and DRAMs CMOS, BiCMOS and bipolar designs for high yield and reliability If you are interested in giving a tutorial please contact the Tutorial Chair as early as possible. For consideration for the regular technical program, please submit five (5) copies of an extended abstract of about one thousand words of original work on any aspect of memory technology, design, and testing to either Program Chair. Submissions should include full names and affiliations of authors and contact information, and should indicate the intended presenter. Submissions are due February 25, 1998. Acceptance notification will be on March 31, 1998. Final papers will be due May 15, 1998 and must be in postscript format. Presentation time slots will average 30 minutes. GENERAL CHAIR Fabrizio Lombardi Computer Science MS 3112 Texas A&M University College Station TX 77843, USA 409/845-5464; fax 847-8578 lombardi@cs.tamu.edu LOCAL ARRANGEMENTS Craig Soldat, Hewlett-Packard 351 E Evelyn Ave San Jose CA 95035, USA 415/694--3499; craig_soldat@hp.com TUTORIALS CHAIR Bruce Cockburn Elec. and Comp. Engg. MS 238 CEB University of Alberta Edmonton AB T6G 2G7, Canada 403/492-3827; fax 492-1811 cockburn@ee.ualberta.ca PROGRAM COMMITTEE Thomas Wik, PROGRAM co-CHAIR LSI Logic, MS E--194 1551 McCarthy Blvd, Milpitas CA 95035, USA 408/954-4471; fax 433-4561; trw@lsil.com David Lepejian, PROGRAM co-CHAIR Heuristic Physics Laboratories 1649 S Main Street, Milpitas CA 95035, USA 408/263-1466; fax 263-1584; dyl@hpl.com Glenn Chapman, Simon Fraser Univ. Bernard Courtois, INPG/TIMA Bob Evans, MosAid Paul Franzon, NCSU Ad van de Goor, Delft Univ. of Tech. Susumu Horiguchi, JAIST Omar Kebichi, Mentor Graphics Jim Lewandowski, Bell Labs Sankaran Menon, TI Sharon Murray, Medtronic Micro-Rel Ceredig Roberts, Micron Konrad Schoenemann, Siemens AG Ying Shiau, Cypress Semiconductor Stu Tewksbury, WV Univ. Seiken Yano, NEC Yervant Zorian, LogicVisionArticle: 9094
Rick Filipkewicz wrote: > Sometime back I saw some stuff about using ATMEL re-programmable > serial proms for Xilinx XC4xxx parts instead of the Xilinx one > time only parts. Which devices are they & how can they be made Xilinx > equivalent ? Rick, there really is no problem. Just look at their data sheet. They use our nomenclature. If I remember right, they use our Vpp pin differently, and they tend to be slower than our parts, but that is no problem at 1 MHz configuration rate ( but may be a worst-case problem at 8 MHz) A long time ago, Atmel was also confused about the programming of the reset polarity, but that must have been resolved long time ago. Enjoy their reprogrammability. ( I tried to e-mail you directly, but you have this crazy anti-spam address ) Regards Peter Alfke, Xilinx ApplicationsArticle: 9095
Peter Alfke wrote: > --snip-- > Then marketing saw the third LUT in our CLB and gave it a value of 3/8 > of a Logic Cell, so the whole CLB is worth 2.375 LCs. > Obviously, we can argue about this addition, buit it is true that one > can use the third LUT for really nice and efficient solutions. :-) > --snip-- > Users will never agree about these assumption, and if you don't want > to compare different manufacturers, then you can forget the whole > thing and just stick with CLBs and RAM bits, for they are physical and > thus non-controversial. > > Peter Alfke, Xilinx Aplications So, Peter, expalin to me again how 1 CLB=2.375 Logic Cells makes the CLB a physical feature. I get the feeling that this is yet another marketing-created metric designed to prove beyond a reasonable doubt that A>B for any values of A and B. Why not go back a few graphcs in your well-reasoned explanation, and just invite people to count either flipflops or 3-input LUTs (whichever is the critical resource in their design) and then degrade that by a factor for real-world utilization? The factor would be dependent on both % of maximum capacity and architecture, but at least the result would be a useful number. ron wilson, ee timesArticle: 9096
Princeton Information < www.princetoninformation.com > is seeking Ten (10) Senior Digital Design Engineers............ Digital FPGA Hardware Engineer -High Speed Digital Modem Technology Job Description: You will participate in the design and development of a flexible communications system breadboard utilizing FPGA's (ASIC) for Motorola's Celestri (tm) Modem Technology development program. These are specialized high-speed modems (Mbps) installed in satellites. Celestri is a multi-year, $13 billion project that will provide high-bandwidth packet switching - connections (e.g., internet) in outer SPACE!!! Celestial Data Communications for the 21st Century!!! BS/MS in Electrical Engineering +4 to 6 years of experience required. Familiarity with FPGA based design limitations and mitigation methods. Willingness to accept responsibility & technical challenge Ability to work independently and on a team Focus on customer satisfaction EMAIL your resume TODAY!!! ==> azjobs@usa.net Location: Phoenix/ Chandler, AZ Duration: Temp to Permanent Pay Rate: $55,000 => $85,0000 Also, Temp to Perm - "Try it you'll like it!" See our Website: < www.princetoninformation.com > Digital FPGA Hardware Designer - High Speed Digital Design - Modem Technology We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 4-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, Modem Technology development....... Experience with PLD's, FPGA's (ASIC), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. Our client is located in Chandler, Arizona. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail your resume TODAY===> azjobs@usa.netArticle: 9097
Can anybody tell me what's the difference between BUFT and BUFE in Aldec Foundation Series software? I use it to do design with Xilinx device.Article: 9098
This argument will go on forever. The CLB *is* a physical feature, of course. The differences between published gate equivalents and what people actually achieve are down to the P&R software not being too clever. I recently did an ASIC, which was prototyped in a XC3090, and the FPGA was about 80% full (on the CLB count). But counting the gates in the XNF netlist yielded only about 2000 gates (counting a D-type with async preset & clear as 11 gates, as per its standard gate-based schematic), and that was close to what the eventual ASIC had. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 9099
I understand that there are problems with Altera's new release of its Max+Plus II software, version 8.2, that has severely impacted compile times. Does anyone have any knowledge or experience with this software version. thanks Tim -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreading
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