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> > No, it is an anti-trust issue if they do not make the correct documentation > > available to third party manufacturers at the same time they have it. > > > > Unless there have been special limiations or restrictions placed on Intel that > is incorrect. If they make both the CPU, and the system board, they must give equal oportunity to other system board designers (with certain limitations) the same information, as they hold a clearly dominant position in the market place. If they originally came out with the CPU and system board as one unit, than this would not be a problem, but because they ONLY made the CPU originally, and other manufacturers developed the system boards, and now, they are intentionally restricting the ability of other manufacturers to compete with them.....that is anti-trust. >There are plenty of companies with the > resources to go up against Intel if they wanted to. Samsung, Hitachi, etc. DEC > could have done it if they hadn't had a bonehead running the Alpha marketing. You are right, but that was then, and this is now. AustinArticle: 9876
Hello all!
I'll be very appreciate for list of known to you vendors shipped
place&route tools for XC6200 FPGA family.Thanks.
Andrey Ushenin.
-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/ Now offering spam-free web-based newsreading
Article: 9877I haven't seen the "free" set of software but you can obtain the Xilinx Base development system for $99 dollars. It contains the Xilinx Foundation tools, supports all the XC9500 series, and even supports moderate-density FPGAs. See http://www.optimagic.com/lowcost.html#VeryLow. Or, for $87, you can purchase the 300-page Xilinx Student Edition text book containing the Xilinx software CD-ROM. See http://www.optimagic.com/books.html#Xilinx for more information. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Kolaga Gold wrote in message <6gk2j5$m1u@bgtnsc03.worldnet.att.net>... >OK. I see that Digikey these parts in single unit quantity >for around US$5. What about the software to program them? >I know that there is a 4 CD "free" set of software that >Xilinx is offering -- but I'm a student and I don't think >they will send a sales rep over to my dorm room to had me >this stuff. > >Where can I get software for the XC9500 series? I have >XABEL-CPLD 6.10 but that is good only for the XC4000 >parts. I want the ISP feature of the XC9500. > >Thanks.Article: 9878
In article <352DA40E.60B2@isu.edu>, kantviti@isu.edu wrote: > > I think this service is a truly obnoxious intrusion of privacy!!! > > Good Info Services wrote: > > > > Introducing the hottest new way to find out anything about anyone... > > INTERNET INVESTIGATOR!! > I don't know why this ended up in this newsgroup, but here goes. Many government agencies have been collecting such information for years, 30-40 years at least. The IRS, DEA BATF and many others. They have it and make it available to others. Why shouldn't we the general public have access to it also? That way we can at least add a statement when we think something is incorrect, or possibly even get it corrected. You might think the information should be kept from your neighbor, but they have been able to get it anyway simply by paying private investigation agencies. Rather than try to hide information about yourself, the solution is to create so much information that no one, no agency, no organization can handle the volume. Hide in plain sight. Scott Taylor -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9879
Kolaga Gold wrote: > OK. I see that Digikey these parts in single unit quantity > for around US$5. What about the software to program them? > I know that there is a 4 CD "free" set of software that > Xilinx is offering -- but I'm a student and I don't think > they will send a sales rep over to my dorm room to had me > this stuff. > > Where can I get software for the XC9500 series? I have > XABEL-CPLD 6.10 but that is good only for the XC4000 > parts. I want the ISP feature of the XC9500. > Here is the answer to your prayer: Prentice Hall publishes and sells the "Xilinx Foundation Student Edition" which supports all XC9500 devices and all XC4000-type devices up to 8k gates today, 10k gates in the next upgrade. Registration and activation only takes a few mouse-clicks. The box ( I have it in my hand here ) contains a book "The Practical Xilinx Designer Lab Book" by Dave Van den Bout, a Quick Start Guide, and of course a CD-ROM. And the best thing is the price: you can order the whole box from amazon.com for less than seventy dollars. ( search for Xilinx ) I really hope that this is the end of frustration about "expensive Xilinx software". Peter Alfke, Xilinx ApplicationsArticle: 9880
I use Altera's MAXPLUS for all my CPLD/FPGA requirments. The version I have has VHDL complier, fitter, timing simulator, programmer etc. I am a bit of a newbie to this kind of work, but so far Maxplus has been perfectly adequate for all my needs. What would be the benefit of using a 3rd party VHDL compiler ? Would it allow a greater subset of VHDL to be compiled ? (e.g. 1987 & 1993 VHDL varients ?) Would a third party compiler be more effecient, i.e. shorter compile time, higher used logic density, faster device speed ? If this is the case, where would I find any metrics on which compiler is best on the above criteria ? Why can't I take my Altera VHDL and run it on another _cheap_ vendor-specific VHDL tool, eg cypress warp ? Sorry if these are obvious and reveal a lack of insight on my part. -- Steve Dewey Steve@s-deweynospam.demon.co.uk Too boring to have an interesting or witty .sig file.Article: 9881
Kolaga Gold wrote: > OK. I see that Digikey these parts in single unit quantity > for around US$5. What about the software to program them? > I know that there is a 4 CD "free" set of software that > Xilinx is offering -- but I'm a student and I don't think > they will send a sales rep over to my dorm room to had me > this stuff. > > Where can I get software for the XC9500 series? I have > XABEL-CPLD 6.10 but that is good only for the XC4000 > parts. I want the ISP feature of the XC9500. > > Thanks. Here is the answer to your prayer: Prentice Hall publishes and sells the "Xilinx Foundation Student Edition" which supports all XC9500 devices and all XC4000-type devices up to 8k gates today, 10k gates in the next upgrade. Registration and activation only takes a few mouse-clicks. The box ( I have it in my hand here ) contains a book "The Practical Xilinx Designer Lab Book" by Dave Van den Bout, a Quick Start Guide, and of course a CD-ROM. And the best thing is the price: you can order the whole box from amazon.com for less than seventy dollars. ( search for Xilinx ) I really hope that this is the end of frustration about "expensive Xilinx software". Peter Alfke, Xilinx ApplicationsArticle: 9882
I have blown up 3K devices. (I think they were Lucent however). It would happen if you accidentaly loaded the part with garbage. The 4K devices seem to survive and even have an optional CRC checker to detect loading something other than a bit file. I have heard stories of big systems filled with 3090s popping like fire-crackers. I would check to see if something could be corrupting the config data =AE= clocks. Best Wishes Brad Leon Heller wrote: > = > In article <6g21od$j6i$1@newacme.west.net>, Kevin Steele > <ksteele@silcom.com> writes > >I've worked with Xilinx over the last 5 years and in more than a few > >instances have seen cases of Xilinx 3K devices (Prom loaded, Master se= rial) > >smoke seriously on boot. > > > >I suspect a possible cause could be a misloaded serial bitstream, enab= ling > >all the tbuffs? > > > >Anybody else see this kind of behavior? The end result on a qfp packag= e is a > >cracked case or crater in the molten plastic... > = > This sounds like "latchup". It used to be quite common with the older > CMOS devices - the device behaves like an SCR, takes *lots* of current > and self-destructs unless the power is switched off in time. > = > Leon > -- > Leon Heller: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk > Amateur Radio Callsign G1HSM Tel: +44 (0) 118 947 1424 > See http://www.lfheller.demon.co.uk/dds.htm for details of my AD9850 > DDS system. See " "/diy_dsp.htm for a simple DIY DSP ADSP-2104 system. -- = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D User Name: blt Intranet Site: http://web/~blt/top.html A map to my cube: http://web/~blt/how_to_find_me.txt Email: brad.taylor@xilinx.com = Phone: 1-408-879-6976 Fax: 1-408-879-4676 Address: 2100 Logic Drive, San Jose, Ca. 95124 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DArticle: 9883
Dear, As far as I know, XACTstep 6000 series ver 1.17 is the latest version for a route&place tool for XC6200 series. VELAB is a VHDL tool for making an input for the XACTstep 6000 from VHDL code. Seonil uab@info.novsu.ac.ru wrote: > Hello all! > I'll be very appreciate for list of known to you vendors shipped > place&route tools for XC6200 FPGA family.Thanks. > Andrey Ushenin. > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9884
I have five asynchronous pulse streams arriving at my logic device. Right now they range from 40 Hz to 120 MHz, but that range is pretty flexible. I would like to calculate the frequency of each stream. 120 MHz is pushing the limits of the brute-force method (implement counters clocked by the pulse stream, periodically compare them to a real-time clock). Does anybody know of a more elegant solution? Thank you for any ideas. - Scott (change my address to reply: sbronson -a-t- opentv.com)Article: 9885
> You continue to overlook the **FACT** that Intel does design and manufacturer > the motherboards themselves. Just because their name isn't on it doesn't mean > they didn't make it. We manufacturer products without our name on them. What's your point? I am not overlooking that fact. I know it do be a fact, but how is that relevant to it being an anti-trust issue, and or this discussion? Read what I said below, and please explain how what you say above is applicable. > > If they make both the CPU, and the system board, they must give equal > > oportunity to other system board designers (with certain limitations) the > > same information, as they hold a clearly dominant position in the market > > place. If they originally came out with the CPU and system board as one > > unit, than this would not be a problem, but because they ONLY made the CPU > > originally, and other manufacturers developed the system boards, and now, > > they are intentionally restricting the ability of other manufacturers to > > compete with them.....that is anti-trust.Article: 9886
Austin, You continue to overlook the **FACT** that Intel does design and manufacturer the motherboards themselves. Just because their name isn't on it doesn't mean they didn't make it. We manufacturer products without our name on them. In article <01bd6490$ea208570$8fc220cc@drt3>, "Austin Franklin" <darkroo8m@ix.netcom.com> wrote: > > > If they make both the CPU, and the system board, they must give equal > oportunity to other system board designers (with certain limitations) the > same information, as they hold a clearly dominant position in the market > place. If they originally came out with the CPU and system board as one > unit, than this would not be a problem, but because they ONLY made the CPU > originally, and other manufacturers developed the system boards, and now, > they are intentionally restricting the ability of other manufacturers to > compete with them.....that is anti-trust. > Scott Taylor - DSP Fibre Channel Systems -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9887
Guillaume SZCZYGIEL wrote: > > Hello, > > I just wanted to know in which category we can put the FLEX 10 KE from > ALTERA. ALTERA told me it was a CPLD but other people told me it was a > FPGA. > Can you answer me and tell me the reasons why ? > > Thanks, > Guillaume SZCZYGIEL It is more like a CPLD than an FPGA in several respects: 1) the routing is reminiscent of a CPLD. It gives a predictable route between any two elements. However, the price is the route is slow compared to what can be achieved in a thoughtfully executed FPGA design. 2) The LABs, although internally structured similar to other FPGAs, are really alot more like CPLDs when you look at them in relation to other LABs. 3) The memories are separate entities on in the CPLD-like routing structure. Unlike CPLDs, the inputs to the LEs are narrow (in fact narrower than many of the FPGAs), and the IOs are slow. The architecture, kind of splits the difference between FPGAs and CPLDs (probably as was intended). The problem is it seems to have brought along the undesirable baggage (long delays due to the global routing, poor construction of arithmetic functions, very limited input to the LEs, and slow IOs) from both sides without really seeing the benefit of either. Nevertheless, it is a popular device; probably because with its structure, it is tolerant to sloppy, hastily done and ill-conceived designs. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 9888
Peter wrote: > That's correct, Dallas have been pushing their unique-serialised parts > for years. I have used their DS1820 temp sensors, and I would **NOT** > use them for something like this because I have found they are not > exactly 100% reliable. Agreed. I was using them a few years ago in a low cost application that needed to have unique serial numbers for machines on a very large network. I saw one or two that failed. These are not really all that secure, as you can make easily make a circuit to mimic the operation using a CPLD> > It also does not solve the basic problem: say the serialised piece of > hardware (the "token") stops working. If you are able to contact the > vendor for a new license which works with a new token, then the vendor > has no way of knowing whether the original token was *really* damaged. > For all they know, you still have it, and now you will have *two* > copies of the s/w running. I wasn't suggesting it was a good solution. I was merely correcting the previous poster who stated that they were dip parts that could concievably be moved from machine to machine. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 9889
Greetings Alternate Verilog FAQ Version 6 is released. It is available on http://www.comit.com/~rajesh/verilog/faq/alt_FAQ.html 1. Links to Verilog Emacs mode is modified. 2. Information on Verilog text file to HTML conversion is added. Your suggestions are welcome. Rajesh Bawankule -- Rajesh Bawankule | Checkout http://www.comit.com/~rajesh/verilog/ Project Leader | for Verilog FAQ Comit Systems Inc. | 3375, Scott Blvd, #330 | Santa Clara, CA 94054 | ----------------------------------------------------------------------------- ~ -------------------------------------------------------------------- Posted using Reference.COM http://WWW.Reference.COM FREE Usenet and Mailing list archive, directory and clipping service --------------------------------------------------------------------Article: 9890
Why does your VHDL work on Altara and not anything else? (I don't have the Altara tools (Being an X guy they would be hard for me to obtain)) However two possible reasons come to mind right away. 1. You are writing in VHDL, but you are using vendor specific libraries or component instantiations. As soon as you do either of these two things poof goes transportable code. 2. You are not really writing in VHDL but are really using Altara's AHDL. Which is sort of like VHDL but different enough to make it so that other tools don't get it. Why would Altara make a tool that was very much like an industry standard, but different? I am sure that there are two answers to this question. Third parties better? Well I know that X decided that they make chips and that is what they are good at. Tool makers make tools that is what they are good at. Exemplar, Synopsys, Symplicity & all the rest make money only one way and that way is to have the best or close to it tools on the market. So natually they are more driven to perfection, because if they don't meet perfection they don't live. A powerful stimulent, to live or not to live based on the quality of your work. Nick Steve Dewey wrote: > I use Altera's MAXPLUS for all my CPLD/FPGA requirments. The version I have > has VHDL complier, fitter, timing simulator, programmer etc. I am a bit of a > newbie to this kind of work, but so far Maxplus has been perfectly adequate > for all my needs. > > What would be the benefit of using a 3rd party VHDL compiler ? > Would it allow a greater subset of VHDL to be compiled ? > (e.g. 1987 & 1993 VHDL varients ?) > > Would a third party compiler be more effecient, i.e. shorter compile time, > higher used logic density, faster device speed ? > > If this is the case, where would I find any metrics on which compiler is best > on the above criteria ? > > Why can't I take my Altera VHDL and run it on another _cheap_ vendor-specific > VHDL tool, eg cypress warp ? > > Sorry if these are obvious and reveal a lack of insight on my part. > > -- > Steve Dewey > Steve@s-deweynospam.demon.co.uk > Too boring to have an interesting or witty .sig file.Article: 9891
Austin, Because they can start the motherboard and chipset design at the same time as the CPU or soon after. That gives them a lead that others cannot match. And, if they were forced to provide that early information, a few changes would render outside designs invalid or non-functional. They would appologize but point out that the data sheet did say preliminary, as do 10 year old 8086 datasheet last time I looked. When anti-trust could be enforced is if Intel provided the information to some outsiders but not others. In article <01bd64f0$0a596000$8fc220cc@drt3>, "Austin Franklin" <darkroo8m@ix.netcom.com> wrote: > > What's your point? I am not overlooking that fact. I know it do be a > fact, but how is that relevant to it being an anti-trust issue, and or this > discussion? Read what I said below, and please explain how what you say > above is applicable. > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9892
In article <352EC176.A45D9EF2@opentv.com>, Scott Bronson <nospam@opentv.com> wrote: > > I have five asynchronous pulse streams arriving at my logic device. > Right now they range from 40 Hz to 120 MHz, but that range is pretty > flexible. I would like to calculate the frequency of each stream. > > 120 MHz is pushing the limits of the brute-force method (implement > counters clocked by the pulse stream, periodically compare them to a > real-time clock). Does anybody know of a more elegant solution? Thank > you for any ideas. > > - Scott (change my address to reply: sbronson -a-t- opentv.com) > Depending on how often you need to measure the frequency, you can divide the 120MHz by 2 or 4 and then count it for 2 or 4 times longer. Another method is to use ripple counters for the first few stages. That requires that you stop the counting and wait a bit before storing the result to allow the clocks to ripple through. Actually both of those suggestions are the same if you look at it the right way. Most high speed frequency counters pre-scale first to avoid the problem you bring up. Scott Taylor - DSP Fibre Channel Systems -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9893
A pity that Microsoft are not obliged to do the same. Their monopoly, and use of inside knowledge for their own products, is just as bad as Intel's. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9894
>I have blown up 3K devices. (I think they were Lucent however). It would >happen if you accidentaly loaded the part with garbage. The 4K devices >seem to survive and even have an optional CRC checker to detect loading >something other than a bit file. I have heard stories of big systems >filled with 3090s popping like fire-crackers. XC4000 devices should never start up with a bad bitstream since they use proper CRC checking. XC3000A devices should also never start up as a result of total garbage, because they have some limited frame checking - this is very effective in rejecting garbage, I found. The old XC3000 devices can definitely start up with garbage in them, and can get very hot, dissipating several watts (XC3064). I have never actually destroyed any, but that's because I had my finger on them right after a failed upload :) Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9895
It all depends on how you how quickly you want to calculate it, and how you want to represent the calculated value. Obviously, to calculate a "frequency" for a 40 pulse/second signal, you need to wait at least 1/40 of a second. At 120MHz, you can probably just count pulses for a certain time. Somewhere between the two extremes, you may want to switch over from one method to another. But all this is obvious, so I must be missing something. >I have five asynchronous pulse streams arriving at my logic device. >Right now they range from 40 Hz to 120 MHz, but that range is pretty >flexible. I would like to calculate the frequency of each stream. > >120 MHz is pushing the limits of the brute-force method (implement >counters clocked by the pulse stream, periodically compare them to a >real-time clock). Does anybody know of a more elegant solution? Thank >you for any ideas. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9896
I use both Altera VHDL and Warp VHDL and as yet have had no problems as long as you stick to the VHDL standard. Altera VHDL does have some errors in making arrays, but these are overcomable. When you have a very large VHDL source that say takes up a full 10K100, you will some time get odd errors from Altera VHDL, but it will compile OK on say Leonardo. The VHDL contructs are too complex for Altera. But neverless, I stick to ALtera VHDL for 90% of my VHDL work. Steve Dewey wrote: > I use Altera's MAXPLUS for all my CPLD/FPGA requirments. The version I have > has VHDL complier, fitter, timing simulator, programmer etc. I am a bit of a > newbie to this kind of work, but so far Maxplus has been perfectly adequate > for all my needs. > > What would be the benefit of using a 3rd party VHDL compiler ? > Would it allow a greater subset of VHDL to be compiled ? > (e.g. 1987 & 1993 VHDL varients ?) > > Would a third party compiler be more effecient, i.e. shorter compile time, > higher used logic density, faster device speed ? > > If this is the case, where would I find any metrics on which compiler is best > on the above criteria ? > > Why can't I take my Altera VHDL and run it on another _cheap_ vendor-specific > VHDL tool, eg cypress warp ? > > Sorry if these are obvious and reveal a lack of insight on my part. > > -- > Steve Dewey > Steve@s-deweynospam.demon.co.uk > Too boring to have an interesting or witty .sig file.Article: 9897
Nick Hartl wrote: > > Sure if it is in 93 and not in 87, then forget it. > Yes, this is the word I got from Xilinx. Are they planning to replace XVHDL with a compiler that's based on a 10+ year old VHDL spec ? Fortunately I only really loaded the Express tools so I could start playing around with Verilog. > > I have run into the same problem. I've been telling Synopsys that the > > inability to run FPGA Express from the command line is a problem since > > they brought out the first release of it. I understand that Synopsys > > are going to fix this problem but I don't know the timescales. > > So I'm not the only one who thinks GUIs are a WOT. On the Xilinx CD there is a program called FE.EXE that is sort of batch-like but it can only be used to rebuild a project/chip that's been created by the GUI! I haven't yet got it to export an XNF netlist but I'm still trying. > > XVHDL is still included with the M1 tools, I've decided to continue > > using it. If FPGA Express is still broken when they stop supporting > > XVHDL then I'll move FPGA vendors. > > > > By the way, there is a new restriction in XVHDL that forces you to > > put all bidirectional buffers at the top level if you are outputting > > to EDIF, otherwise it puts in internal tristates. You can get around > > this by outputting to XNF. > > Lucky my design style does this anyway ... > > -- > > Aedan Coffey, Eurologic Systems Ltd, Kilkenny, Ireland > > Email: acoffey at eurologic dot com -- _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 9898
=======================================================================
CALL FOR PAPERS
The 19th IEEE Real-Time Systems Symposium
Madrid, Spain
December 2-4, 1998
Sponsored by The IEEE Computer Society Technical Committee on
Real-Time Systems
=======================================================================
SCOPE OF THE CONFERENCE
RTSS '98 brings together a diverse body of researchers and developers,
to advance the science and practice of real-time and embedded systems.
All papers on real-time, embedded or reactive systems are welcome,
including (but not limited to) the following topics:
* Real-time and embedded operating systems.
* Systems design and analysis: theories, methods and tools.
* Scheduling techniques: CPUs, devices, networks, end-to-end.
* Programming languages for real-time and embedded systems.
* Specification, verification and automated analysis.
* Middleware and APIs for real-time and embedded systems.
* Performance evaluation: theory, analysis and tool support.
* Domain-specific architectures for embedded systems.
* Instrumentation, profiling, testing and debug support.
* Support for COTS-based integrated systems.
* Fault-tolerance, reliability and safety.
* Program analysis and tools.
* Object-oriented languages: designs, programs, interfaces.
* Real-time and reactive databases and file systems.
* Computer networks and communications.
* Signal processing, control and robotics.
* Digital video, audio, animation and multimedia.
Papers on these or other relevant topics are solicited for RTSS '98.
Of particular interest are case-study reports on experimental results,
from any core application area in real-time, embedded and/or reactive
systems.
=======================================================================
SUBMISSION GUIDELINES
Papers should describe original research (i.e., not published elsewhere),
and should not exceed 20 double-spaced pages. All accepted submissions
will appear in the proceedings published by IEEE, with the committee
recommending a selection of the best papers for publication in a journal.
If possible, submissions should be made electronically, either in
postscript or PDF format. Additional details on submission guidelines
will be posted at the RTSS'98 Home Page:
http://www.cs.umd.edu/~rich/rtss98/
Electronic submissions are preferred; however postal submissions will
be accepted for review, provided they arrive by the Submission Deadline
of May 1, 1998. All authors taking this option should mail eight (8)
copies of their submitted papers to the Program Chair:
Richard Gerber Email: rich@cs.umd.edu
Department of Computer Science URL: www.cs.umd.edu/~rich
University of Maryland Phone: +1-301-405-2710
College Park, MD 20742 USA Fax: +1-301-405-6707
=======================================================================
IMPORTANT DATES
* May 1, 1998 -- Deadline for paper submissions
* July 25, 1998 -- Notification of acceptance
* September 1, 1998 -- Final paper due
* December 2-4, 1998 -- RTSS '98, Madrid, Spain
=======================================================================
EXHIBITION, WORKSHOP AND WORK-IN-PROGRESS SESSIONS
Exhibition and Show: RTSS '98 will include an industrial exhibition in
a centrally located space, for vendors to demonstrate state-of-the-art
systems, development tools and applications; where RTSS attendees can
engage in technical discussions with product engineers and developers;
and where company representatives meet (and potentially recruit) young
researchers specializing in real-time and embedded systems. To reserve
space for the exhibition, please contact the RTSS '98 Industrial
Chair, Dr. Alan Burns (burns@minster.cs.york.ac.uk).
Workshop: RTSS '98 will co-host a workshop on December 1, 1998,
directly before the conference. The focus of the workshop will be a
"hot topic" of special interest to researchers and developers of
real-time systems. Recent RTSS workshops were on topics such as
Middleware/APIs (1997) and Multimedia Systems (1996). More information
on the 1998 workshop topic will be announced shortly, and publicized
on the conference home page.
Work-in-Progress Session: As in previous years, RTSS '98 will include
a Work-In-Progress (WIP) session, featuring short presentations on new
and evolving work. Accepted WIP papers will be included in a special
proceedings, and distributed to RTSS'98 conference participants. The
proceedings will then be published electronically on the IEEE-CS
TC-RTS Home Page. WIP papers will be due approximately one month
before the Symposium.
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ORGANIZING COMMITTEE
General Chair: Kwei-Jay Lin, University of California, Irvine
Program Chair: Richard Gerber, University of Maryland
Finance Chair: Walt Heimerdinger, Honeywell Technology Center
Registration Chair: Linda Buss
Local Arrangements Chair: Angel Alvarez, Universidad Politecnica de Madrid
Local Treasurer: Juan A. de la Puente, Universidad Politecnica de Madrid
Publicity Co-Chairs:
Alejandro Alonso, Universidad Politicnica de Madrid (Europe)
Chao-Ju Jennifer Hou, Ohio State University (Americas)
Joseph Ng, Hong Kong Baptist University (Asia/Pacific)
Industrial Chair: Alan Burns, University of York
Ex-Officio: (RTS-TC Chair) Doug Locke, Lockheed Martin Corporation
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PROGRAM COMMITTEE
James Anderson (University of North Carolina)
Azer Bestavros (Boston University)
Sanjoy Baruah (University of Vermont)
Giorgio Butazzio (Scuola Superiore e Sant'Anna)
Gerhard Fohler (Malardalen University)
Michael Gonzalez Harbour (Universidad Cantabria)
Jeffrey Hollingsworth (University of Maryland)
Seongsoo Hong (Seoul National University)
Farnam Jahanian (University of Michigan)
Kevin Jeffay (University of North Carolina)
Hermann Kopetz (Vienna University of Technology)
Kim G. Larsen (Aalborg University)
Insup Lee (University of Pennsylvania)
Jane W.S. Liu (University of Illinois)
Keith Marzullo (University of California at San Diego)
Sang Lyul Min (Seoul National University)
Al Mok (University of Texas at Austin)
Ragunathan Rajkumar (Carnegie Mellon University)
Jennifer Rexford (AT&T Research)
Manas Saksena (Concordia University)
Bran Selic (ObjectTime, Ltd.)
Andy Wellings (University of York)
David Wilner (Wind River Systems)
Sergio Yovine (CNRS/VERIMAG)
Hui Zhang (Carnegie Mellon University)
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Article: 9899Hello, I am a student at Clemson University (South Carolina) and am working on a project for a class. I have purchased the student edition of Xilinx's foundation software, but it is currently only at v1.3, and thus does _not_ include VHDL support. According to to Xilinx's homepage, I can legally upgrade my student edition to v1.4, if I can find someone who has the _Foundation Express version 1.4_ software. If anyone has this available, and would be willing to let me bring my computer by to upgrade my system, please contact me. I know this seems like a strange request, but I'm really crunched for time on this project, and having the ability to do the VHDL design at home would help me out a great deal. Thank for any assistance. Rob Ehlers rehlers@clemson.edu 864-653-4097
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