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I'm trying to use a FPGA to control an IDE hard drive. Can't
even write to the registers on the drive yet. I have the ANSI spec
but I can't shake the feeling it's leaving something out. Anyone know
where I can get more detailed info on ATA-2 or can anyone help?
Thanks much,
kz
cjsmith@uiuc.edu
Article: 9976
Hello reader,
i would announce two development boards of Alcatel Telecom.
The two boards are useful for ASIC prototyping and simulation.
We already used the boards to verify DSP algorithms written in
VHDL, to test the behaviour of PLL circuits, to built test
equippment (complex signal generators written in VHDL) for our
fab and for other applications.
Short description of the boards:
HW_SIM
* 200.000 gates logical resources (4*Altera EPF10K50)
(300.000 gates if equpipped with 1EPF10K70)
* 2 Slots for SIMM memory modules (30 pin types)
* 2 on board oscillators (48,640 MHz, 16,384MHz)
* PBA size 233mm*210mm
* breadboard area
* reset circuit
* ...
DEV_KIT
* 20.000 gates logical resource (2*Altera EPF81188)
* on board oscillator (16,384 MHz)
* PBA size 233mm*160mm (possible splitting 2 times 100mm*160mm)
* breadboard area
* reset circuit
* ...
For more information about the development boards contact
one of the persons listed below.
Financial Questions: R.Prestin@alcatel.de
Technical Questions: brod@lts.sel.alcatel.de
Best regards Lothar Brodbeck
p.s.
An user wrote: ... We successfully used the HW_SIM development
board to verify our complex signal processing
algorithm. ... The programming and the handling
of the evaluation board stands out. ...
You can find a description and pictures of the boards using the
following address:
http://www.alcatel.de/telecom/asd/test_hw/topdevboard.htm
--
Best regards Lothar Brodbeck
MFG Lothar Brodbeck
\////
(o/o)
+----------------+-------------UUUU----U----UUUU--+-------------------+
|Lothar Brodbeck | Email: brod@lts.sel.alcatel.de | Alcatel Telecom |
|Dept.: AS/EC1 | Phone: +49-711-821-47334 | Lorenzstrasse 10 |
|Room: 58/2/4 | Fax: +49-711-821-45068 | D-70435 Stuttgart |
+----------------+--------------------------------+-------------------+
Article: 9977staylor@dspsystems.com wrote: > Eric, > > ICs are responsible for the electronic era. Have you ever heard of football > widows? Have you ever tried to talk to someone who keeps getting phone calls. > Do children play catch or nintendo? Do people read books or watch TV? TV news > has caused many people to believe anything they are told rather than to think > about it or question the accuracy or validity. > In this vein, consider reading "Amusing Ourselves to Death" by Neil Postman. This is not sci-fi, like many of the other suggestions, but social criticism in a more scholarly fashion. Realize that this doesn't mean that it will necessarily be regarded as a better source, just that the story line won't be quite as interesting. :) Also, this book (I really do recommend it) predominantly addresses the last couple of questions that staylor posed. Also, consider the influence that the "electronic revolution" has had on the community of corporate entities in the world. How many of the Fortune 50 are IC or consumer electronics manufacturers? What was the situation like 50 and 100 years ago? How do these changes affect individuals and economies? What effects are electronic commerce having? Many of the influences on modern culture have been driven by reverberations of Moore's Law. Dig in and think about how all things electronic affect your life. Then, push outward until you get to the ragged edges of civil-war-torn third world countries where weaponry that could never have been produced without help from the "silicon race" are laying waste to human life (not that this wouldn't be happening otherwise, but the scale would probably be different). Consider that a huge amount of advanced research in electronics is funded by military budgets. Okay, this has been far more than enough extemporizing for a struggling student who should be doing proofs rather than reading newsgroups. :) Good luck with your paper, Eric. Tahoma.Article: 9978
I'm using some new 4010XL FPGAs in a lab class, and I'm having some trouble with my pin assignments. I'm using the XS40 prototyping board from Xess, and I don't seem to be able to use particular pins, the programming pins such as TCK and TDI for example. I was under the impression that these pins become general purpose I/O pins after the chip is programmed. Is that correct? Thanks. James jameskim@leland.stanford.eduArticle: 9979
I am trying to use the C++ code provided with the HOT Works
board to interface with the board via software. Unfortunately I am
having major difficultiies in doing this. There are a few reasons :
(a) I dont know what is in the device driver, and hence have no idea if
this is working correctly.(The code uses the device driver)
(b) The code provided doesn't read in CAL files correctly, nor does the
executables provided by VCC.
I have contacted VCC a few times for help but there is a curious lack of
response from them.....
If anyone has used the C++ code to interface to the HOT Works board, I
would love to get a couple of pointers on how to get started.
Dave Braendler.
Centre for Intelligent Systems.
Swinburne University.
Article: 9980I'm trying to design a 17-bit carry-save adder using Xilinx Foundation. A carry-save adder is nothing but an array of 1-bit full-adders. First I tried designing this using the schematic editor in a straightforward way -- I created a one-bit adder, and repeated it 17 times. This uses 17 CLB's. Then I tried using LogiBlox to create arrays of simple gates of size 17, and designed an array of 17 full-adders using those gate arrays. Again, I needed 17 CLB's. This seems incredibly wasteful, considering that LogiBlox can generate a 17-bit "fast" carry-propagate adder using only 10 CLB's! Unfortunately, LogiBlox can't generate an array of unconnected full-adders. Any clues on how to do that cheaply? How do I program my own LogiBlox program (if I need to)? Or maybe I should ask Xilinx to add a full-adder array generator to LogiBlox?? I'd appreciate answers via email. Thanks in advance!!Article: 9981
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Article: 9982Prof. Vitit Kantabutra wrote: > > I'm trying to design a 17-bit carry-save adder using Xilinx Foundation. > A carry-save adder is nothing but an array of 1-bit full-adders. First > I tried designing this using the schematic editor in a straightforward > way -- I created a one-bit adder, and repeated it 17 times. This uses > 17 CLB's. Then I tried using LogiBlox to create arrays of simple gates > of size 17, and designed an array of 17 full-adders using those gate > arrays. Again, I needed 17 CLB's. > > This seems incredibly wasteful, considering that LogiBlox can generate a > 17-bit "fast" carry-propagate adder using only 10 CLB's! > > Unfortunately, LogiBlox can't generate an array of unconnected > full-adders. > > Any clues on how to do that cheaply? How do I program my own LogiBlox > program (if I need to)? Or maybe I should ask Xilinx to add a full-adder > array generator to LogiBlox?? I'd appreciate answers via email. Thanks > in advance!! Hi there, As far as I remember, a full-adder-cell has three inputs (a, b, carry-in) and two outputs (sum, carry-out). To generate two outputs, you will always need both function generators of one CLB (XC4K). This will lead to n CLB's for n full-adders. The only reason why the n-bit ripple-carry-adders generated by LogiBlox use less than n CLB's is by using dedicated carry-logic included in every CLB. It is difficult or nearly impossible to use this carry-logic for your own purpose. The dedicated carry-logic is explained in http://www.xilinx.com/xapp/xapp013.pdf . Hope that helps Frank ____________________________________________________________________ Frank Gilbert | University of Kaiserslautern mailto:gilbert@informatik.uni-kl.de | Center for Microelectronics (ZMK) phone: ++49/0 631 205 3608 | Erwin-Schroedinger-Strasse fax: ++49/0 631 205 3616 | D-67663 Kaiserslautern, GermanyArticle: 9983
On Sun, 19 Apr 1998, Peter Trei wrote: > Do you have a massively parallel FPGA box, or a lot > of development boards sitting idle? > RSA Labs (http://www.rsa.com/rsalabs/des2/) has for > the last couple of years been running "DES challenges", > in which they publish a message encrypted using the This is exactly the topic of my final year project. My system is still not yet completed, but what I can say is, the system can fit in around 10K gates.... I haven't contact my university so I won't disclose any details here.... :) ------------------------------------------------------------------------------- | Best Regards, +--------+ | Email: eg_hsh@stu.ust.hk | | David Ho | ¦ó²Ðºµ | | cshosh@cs.ust.hk | | Ho Siu Hung +--------+ | | | University of Science and Technology | ICQ#: 798357 | | Computer Engineering Year 3 (CPEG) =======================================| -------------------------------------------------------------------------------Article: 9984
I am looking for a XNF to EDIF conversion utility. FPGA express only generates XNF netlist when synthesizing for XILINX. I would like to read in the generated code into Viewlogic, using edif netlist reader and then generate schematics with Viewgen.Article: 9985
Hi,
Is there a good way to compress the data for a 10K20. I have a board
wich does not have JTAG wired up so I can not use JAM. Any ideas ?
Thanks Billy B.
Article: 9986James Kim wrote: > > I'm using some new 4010XL FPGAs in a lab class, and I'm having some > trouble with my pin assignments. I'm using the XS40 prototyping board > from Xess, and I don't seem to be able to use particular pins, the > programming pins such as TCK and TDI for example. I was under the > impression that these pins become general purpose I/O pins after the > chip is programmed. Is that correct? Have you got the databook? There is a full table of what particular pins become in the XC4000 section. (The databook is also available on-line at Xilinx's Web site).Article: 9987
Hey all, I am getting strange problem with my Minc fitter for Synario. I have a single clock pin assigned for a MACH466. I am using about 180 macrocells out of 256. When the Minc fitter runs, it assigns another non-clock pin for my clock! I don't use the clock as an input in any equations, just for clock. Why the heck would the fitter decide I needed this clock as an input signal? When I run the static timing analyzer it shows several of my output signals as being asyncronous, which indicates that the clock for that output is coming from the I/O pin, not the clock pin! I have tried Synario support, and they just pointed the finger at Minc. I am inclined to believe them since the pre-fit equations (and the post fit for that matter) show this clock input as being used as a clock only, not as a signal. I left a message for Minc, but I don't know when they will get back to me. Any ideas would be greatly appreciated. Mike ******************************************************* * Michael J. Kelly tel: (508) 278-9400 * * Cogent Computer Systems, Inc. fax: (508) 278-9500 * * 10 River Rd., Suite 205 web: www.cogcomp.com * * Uxbridge, MA 01569 email: mike@cogcomp.com * * * * CMA - Universal Target Platform for 32/64-Bit RISC * *******************************************************Article: 9988
Willy wrote: > > I am looking for a XNF to EDIF conversion utility. FPGA express only > generates XNF netlist when synthesizing for XILINX. I would like to read in > the generated code into Viewlogic, using edif netlist reader and then > generate schematics with Viewgen. I understand that XNF is a more robust and descriptive way to transfer design data into M1 (the Xilinx compiler). A possible work around is to take the XNF through the Xilinx tools and define an output EDIF file for Viewlogic post place and route Tim. -- Strong words softly spoken. My opinions != Nortel's opinion.Article: 9989
In order to use some of the special purpose pins (configuration mode pins and JTAG pins) you must use special library elements to allow them to be used after configuration. I don't know whether you are using schematics or HDL. If you are using schematics, you must use the special pad symbols named TCK, TDI, and TMS (these pads can be inputs only after configuration) and TDO (output only). In VHDL or Verilog, these must be declared as components and instantiated. Do not instantiate the BSCAN element, as this will make the JTAG pins actual JTAG pins after configuration. James Kim wrote: > > I'm using some new 4010XL FPGAs in a lab class, and I'm having some > trouble with my pin assignments. I'm using the XS40 prototyping board > from Xess, and I don't seem to be able to use particular pins, the > programming pins such as TCK and TDI for example. I was under the > impression that these pins become general purpose I/O pins after the > chip is programmed. Is that correct? > > Thanks. > James > jameskim@leland.stanford.edu --Article: 9990
Frank Gilbert wrote: > As far as I remember, a full-adder-cell has three inputs (a, b, > carry-in) and two outputs (sum, carry-out). To generate two outputs, you > will always need both function generators of one CLB (XC4K). This will > lead to n CLB's for n full-adders. > > The only reason why the n-bit ripple-carry-adders generated by LogiBlox > use less than n CLB's is by using dedicated carry-logic included in > every CLB. It is difficult or nearly impossible to use this carry-logic > for your own purpose. The dedicated carry-logic is explained in > http://www.xilinx.com/xapp/xapp013.pdf . Thanks. That makes sense. But now I wish CLB's were designed in a more carry-free-operations-friendly manner. Aren't there FPGA's out there that are better suited to carry-free arithmetic?Article: 9991
Prof. Vitit Kantabutra wrote: > > I'm trying to design a 17-bit carry-save adder using Xilinx Foundation. > A carry-save adder is nothing but an array of 1-bit full-adders. First > I tried designing this using the schematic editor in a straightforward > way -- I created a one-bit adder, and repeated it 17 times. This uses > 17 CLB's. Then I tried using LogiBlox to create arrays of simple gates > of size 17, and designed an array of 17 full-adders using those gate > arrays. Again, I needed 17 CLB's. > > This seems incredibly wasteful, considering that LogiBlox can generate a > 17-bit "fast" carry-propagate adder using only 10 CLB's! > > Unfortunately, LogiBlox can't generate an array of unconnected > full-adders. > > Any clues on how to do that cheaply? How do I program my own LogiBlox > program (if I need to)? Or maybe I should ask Xilinx to add a full-adder > array generator to LogiBlox?? I'd appreciate answers via email. Thanks > in advance!! Xilinx gets two adder bits per CLB because of the dedicated ripple carry chain built into the CLB architecture. Each bit requires a sum and a carry output. THe ripple chain takes care of the carry outputs, allowing you to get two bits per CLB. Note that the chain within the CLB has the carry out of the low bit (F) hardwired to the carry in of the high bit (G). You can program the carry logic associated with either bit to bypass so that you can get one bit carry functions on either half. You cannot however decouple the two carry logics for independent use. THe carry in and carry out connections at the CLB boundary connect only to carry connections on the CLBs above and below that one (in 4000E, the direction of the carry can go up or down; in 4000XL and XV it only goes up). This means that to get to the carry out, you still need to use a CLB to get the signal off of the carry chain. While you can do some designing around the carry chain if you are so inclined, The wired connections don't permit 2 a 2 bit adder without an interconnected carry. Designing with the carry chain requires you to be very familiar with the architecture and to be comfortable with detailed floorplanning (carry chain components need to be relationally placed so that the chain connects to adjacent CLBs). I don't recommend it for someone such as you who is just starting out on his first xilinx design. Generally speaking, it is better to use (in terms of both area and speed) ripple carry adders incorporating the carry chain than to construct a carry save adder. This is because of the speed of the carry chain relative to the LUT logic and general interconnect. When you get into very wide arithmetic logic, hybrid architectures consisting of ripple carry segments connected in carry-save, arithmetic progression, propagate-generate or other carry schemes can yield significant benefits. For these techniques to be advantageous though, you usually need data widths wider than 24 or more bits. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 9992
peterc wrote: > James Kim wrote: > > > > I'm using some new 4010XL FPGAs in a lab class, and I'm having some > > trouble with my pin assignments. I'm using the XS40 prototyping > board > > from Xess, and I don't seem to be able to use particular pins, the > > programming pins such as TCK and TDI for example. I was under the > > impression that these pins become general purpose I/O pins after the > > > chip is programmed. Is that correct? > > Have you got the databook? > > There is a full table of what particular pins become in the XC4000 > section. (The databook is also available on-line at Xilinx's Web > site). The information is on pages 4-244 and 4-245 of the 1998 Data Book, but you can also find it on page 4-47 of the 1996 data book if you modify the Mode pin information ( they are different on Spartan ). Peter Alfke, Xilinx ApplicationsArticle: 9993
Prof. Vitit Kantabutra wrote: > I'm trying to design a 17-bit carry-save adder using Xilinx > Foundation. > A carry-save adder is nothing but an array of 1-bit full-adders. > First > I tried designing this using the schematic editor in a straightforward > > way -- I created a one-bit adder, and repeated it 17 times. This uses > > 17 CLB's. Then I tried using LogiBlox to create arrays of simple > gates > of size 17, and designed an array of 17 full-adders using those gate > arrays. Again, I needed 17 CLB's. > > This seems incredibly wasteful, considering that LogiBlox can generate > a > 17-bit "fast" carry-propagate adder using only 10 CLB's! > > Unfortunately, LogiBlox can't generate an array of unconnected > full-adders. > > Any clues on how to do that cheaply? How do I program my own LogiBlox > > program (if I need to)? Or maybe I should ask Xilinx to add a > full-adder > array generator to LogiBlox?? I'd appreciate answers via email. > Thanks > in advance!! A full adder is two functions with each three input variables.The FPGA thus needs two look-up tables ( each with three inputs ) one creating the sum, the other one the carry. That takes a whole CLB. Yes, it is inefficient, but that is your choice. You want to generate all those intermediate sums and carries, and you pay the price. Since this method is neither efficient nor fast, why bother ? If you just want to play with it or use it for teaching purposes, accept the poor performance. It should not matter. Did I misunderstand your application ? Peter Alfke, Xilinx ApplicationsArticle: 9994
Willy wrote: > I am looking for a XNF to EDIF conversion utility. FPGA express only > generates XNF netlist when synthesizing for XILINX. I would like to read in > the generated code into Viewlogic, using edif netlist reader and then > generate schematics with Viewgen. You could try tracking down an old copy of XNF2WIR used in the pre-M1 days. Just out of curiosity, why do you want to generate schematics? Unless Viewlogic has improved Viewgen output, the schematics are not user friendly! Also, if you are in a big Xilinx part, you will get many many pages. ToddArticle: 9995
--------------A2572C65E25F7167FE7C2CFB Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Yes, Peter (of Xilinx), you misunderstood my application. I am not trying to use this scheme to teach with, nor am I just "playing" with it. Carry-save adders are well-known, very useful devices. Basically, the idea is that you can add 3 numbers together and express the result as two numbers instead of one. (One of the result numbers is the sum output bits put together, while the other is the carry output bits put together. The latter is shifted by 1 position, of course.) The delay is only equal to the sum output delay of a one-bit adder. How is this useful? Well, for example, you can wire an array multiplier with it, using carry-save adders in each stage. In each stage, a new partial product, expressed as one binary number, is added to existing result, which is expressed as two numbers, making three binary numbers coming in altogether. The new partial product, expressed as two numbers, comes out in 1 full adder delay. Only in the last stage would you have to add two numbers together in a regular way, propagating the carry. The result is a compact and fast multiplier. My application is a radix-4 CORDIC rotator, which could make great use of carry-save adders because of the algorithm's iterative nature. Believe me, there are a lot of us out there who would like to see area-efficient carry save adders. You wrote, "You want to generate all those intermediate sums and carries, and you pay the price." Well, the way your (Xilinx's) CLB's are, that would be true. But surely your CLB's could be extended just a little in some of your many fpga's, and things would be better for both Xilinx and those customers who would like to do "carry-free arithmetic." Note also that "carry-free arithmetic" has been in use for a long time in the world of custom-made IC's. I think it is time for it to be widely known in the fpga world. (Fpga's are now big enough for this.) --------------A2572C65E25F7167FE7C2CFB Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Yes, Peter (of Xilinx), you misunderstood my application. I am not trying to use this scheme to teach with, nor am I just "playing" with it. Carry-save adders are well-known, very useful devices. Basically, the idea is that you can add 3 numbers together and express the result as two numbers instead of one. (One of the result numbers is the sum output bits put together, while the other is the carry output bits put together. The latter is shifted by 1 position, of course.) <I>The delay is only equal to the sum output delay of a one-bit adder.</I> <P>How is this useful? Well, for example, you can wire an array multiplier with it, using carry-save adders in each stage. In each stage, a new partial product, expressed as one binary number, is added to existing result, which is expressed as two numbers, making three binary numbers coming in altogether. The new partial product, expressed as two numbers, comes out in 1 full adder delay. Only in the <I>last stage</I> would you have to add two numbers together in a regular way, propagating the carry. The result is a compact and fast multiplier. <P>My application is a radix-4 CORDIC rotator, which could make great use of carry-save adders because of the algorithm's iterative nature. <P><I>Believe me, there are a lot of us out there who would like to see area-efficient carry save adders.</I> You wrote, "You want to generate all those intermediate sums and carries, and you pay the price." Well, the way your (Xilinx's) CLB's are, that would be true. But surely your CLB's could be extended just a little in some of your many fpga's, and things would be better for both Xilinx and those customers who would like to do "carry-free arithmetic." <P>Note also that "carry-free arithmetic" has been in use for a long time in the world of custom-made IC's. I think it is time for it to be widely known in the fpga world. (Fpga's are now big enough for this.) <BR> <BR> </HTML> --------------A2572C65E25F7167FE7C2CFB--Article: 9996
"Prof. Vitit Kantabutra" <kantviti@isu.edu> writes: >I'm trying to design a 17-bit carry-save adder using Xilinx Foundation. >A carry-save adder is nothing but an array of 1-bit full-adders. First >I tried designing this using the schematic editor in a straightforward >way -- I created a one-bit adder, and repeated it 17 times. This uses >17 CLB's. Then I tried using LogiBlox to create arrays of simple gates >of size 17, and designed an array of 17 full-adders using those gate >arrays. Again, I needed 17 CLB's. As others have said, the dedicated carry logic doesn't help you at all, so it is one per CLB. The Altera FPGA uses a lookup table for both sum and carry, and may be able to do what you want. Last I knew, they were similar density and price to Xilinx, even considering they had more LUT instead of dedicated carry. But my design depended on the dedicated carry logic. -- glenArticle: 9997
Thanks a lot for your extensive reply. The reason I'm struggling with carry-save adders is because I'm trying to do the X & Y iterations for my radix-4 CORDIC algorithm. A Xilinx application engineer responded by suggesting reducing 4 operands to 3, instead of 3 to 2. (He's done carry-save adders himself.) But it seems to me that this would take 3 CLB's for every 2 bit positions. Is it possible to do better?Article: 9998
Prof. Vitit Kantabutra wrote: > > I'm trying to design a 17-bit carry-save adder using Xilinx Foundation. > A carry-save adder is nothing but an array of 1-bit full-adders. First > I tried designing this using the schematic editor in a straightforward > way -- I created a one-bit adder, and repeated it 17 times. This uses > 17 CLB's. Then I tried using LogiBlox to create arrays of simple gates > of size 17, and designed an array of 17 full-adders using those gate > arrays. Again, I needed 17 CLB's. > > This seems incredibly wasteful, considering that LogiBlox can generate a > 17-bit "fast" carry-propagate adder using only 10 CLB's! > > Unfortunately, LogiBlox can't generate an array of unconnected > full-adders. > > Any clues on how to do that cheaply? How do I program my own LogiBlox > program (if I need to)? Or maybe I should ask Xilinx to add a full-adder > array generator to LogiBlox?? I'd appreciate answers via email. Thanks > in advance!! -- Another alternative would be to use an Atmel part. I believe they can implement a full adder in a single cell (with a rather minimalist architechture). The big advantage is that you get so many more cells than you do in a comparable sized Xilinx part. I forget the numbers, but I believe there are about 6 or 8 times as many cells for a part of a given size rating. The limitation in the Atmel FPGA is the limited interconnect. It is based on adjacent cell connections with few and rather limited interconnect otherwise. But they have a new line coming out that sounds like it gets around this somewhat. But then I use Xilinx for everything I do. ;-) Rick Collins rickman@XYwriteme.com remove the X and Y to email me.Article: 9999
If either the sums or the carries can be registered in flip-flops, then I think it should be possible to use the F, G, and H function generators and pack the design in ceil(17*2/3) = 12 CLBs. Remember each CLB has 3 function generators (2 4-luts and 1 3-lut) driving up to 2 registered and 2 non-registered outputs. Hint: this will probably require use of 2 FMAPs, 1 HMAP, and at least one FD per CLB, all with [R]LOC attributes. Jan Gray
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