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Hi, I am in VHDL. I have the following statements: type integer_array is array(natural range <>) of integer; type cs_type is array (0 to N) of integer_array (1 to Nmax); signal cs : cs_type; If those statements live within an architecture, everything goes well. But if I make the signal cs as a port of the entity, the problem arise: I must specify integer_array and cs_type somewhere in the project globally. Is anything I can do to use the type declarations locally in the file of the entity? Thank you. WengArticle: 148326
Weng Tianxiang <wtxwtx@gmail.com> writes: > Hi, > I am in VHDL. > > I have the following statements: > > type integer_array is array(natural range <>) of integer; > type cs_type is array (0 to N) of integer_array (1 to Nmax); > signal cs : cs_type; > > If those statements live within an architecture, everything goes well. > > But if I make the signal cs as a port of the entity, the problem > arise: > > I must specify integer_array and cs_type somewhere in the project > globally. > > Is anything I can do to use the type declarations locally in the file > of the entity? You have to put them in a package. The package can exist within the same file as the entity though. Then things which instantiate that entity can make use of the package to see the same definitions. Be aware - just because it's in the same file doesn't mean you don't have to do: use work.my_package.all; before the entity declaration! Also be aware that if you put the package in the same file and compile the file "normally", you'll have to recompile anything which depends on the that package (as it's been touched). If you're using Modelsim, you can use vcom -just bac myfile.vhd to compile just the package bodies, architetcures and configs, which doesn't touch the package and entity declarations, which then don't ripple on to other files. If your compiler can't do something similar, you may be better to put the package (and probably the entity) in a separate file to the architecture, as it's the architecture which get's the most iteration during the development of the code, and it's great to only have to recompile the one file most of the time. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 148327
On Jul 6, 7:31=A0pm, "alangeering" <alan@n_o_s_p_a_m.algee.co.uk> wrote: > Does anyone make the following: > > HDMI Receiver -> FPGA -> HDMI Transmitter > > I would considder DVI/Displayport also. > > I just want this for video processing. I don't need audio, controls, PCIe= , > etc. > I've seen some very large boards with HDMI daughter boards but they're wa= y > too large and unnecessary for just testing video algorithms. > > Thanks, Alan Geering > http://www.blackmagic-design.com/products/intensity/ cheapest devkit you can get :) $199 hdmi in/out, S3E1200 FPGA FPGA download is controlled by cypress FX2 (there is no onboard flash) but you would need to reverse endineer lots of connections :( AnttiArticle: 148328
I have a Platform Cable USB: http://www.xilinx.com/products/devkits/HW-USB-G.htm I want to start playing with spartan-6 devices, but spartan-6 is not in the Device Family Support list of this programmer. Seems that only Platform Cable USB II supports spartan-6: http://www.xilinx.com/products/devkits/HW-USB-II-G.htm Is it really that way? If so, does anyone have a good explanation for it? Thanks DanielArticle: 148329
I'm troubleshooting a design that uses a XC3S50 as a way to take a 125Mhz clock and, using 2 DCMs, output 4 copies of it shifted 45deg from one another. The 1st DCM CLK0/90 ports give you the 0 and 90deg output clocks and the second DCM has a fixed phase offset so it's CLK0/90 ports give you the 45 and 135deg clks. However, the client didn't provide any external feedback of the clocks to the DCMs on the PCB and internal routing/gate delays are screwing up the phase relationship at the output pins of the FPGA. I'm having a hell of a time trying to constrain path delays to compensate. Has anyone done anything like this before? I have a post PAR simulation so I know what deltas I'm looking for. My thought was that there must be some way to request a particular routing delay via a constraint. So far I've not had much luck. It's the only thing the device is doing so I have routing resources to burn.... the difference in routing delay I need to compensate for is ~1ns. If I could match the internal DCM to PAD paths for the 0/90 outputs of each DCM I could use the phase offset of one of the DCMs to set the phase relationship between the two output clock groups and save a re-spin of the board. Thoughts? Thanks, CaseyArticle: 148330
"John McCaskill" <jhmccaskill@gmail.com> wrote in message news:e23621b7-bb14-4c58-b907-5264172c7a5a@k39g2000yqb.googlegroups.com... > On Jul 7, 8:04 am, "Roger" <rogerwil...@hotmail.com> wrote: >> Anyone know about FO transceivers? >> >> The Finisar (and other SFP/SFP+ FOTs come in particular frequencies) - >> e.g. >> 8.5Gbps for the FTLF8528P2BNV. Can these parts still be used for lower >> frequencies, say 6.5Gbps for Xilinx GTP RocketIO links please? >> >> Has anyone any proven solutions of using a FOT for 6.5Gbps RIO links? >> >> Thanks. > > > Hello Roger, > > While I have not tried that specific module, we have several products > that use SFP and SFP+, and my experience is that the optical modules > are quite happy to run at lower speeds. I don't know how low they will > go, but many of them are rated at multiple rates, ie 2 and 4 Gbs or 4 > and 8Gbs. > > You can use ChipScope Pro and the IBERT tool to try out a specific SFP > + module quickly. If you have the ML605 development board, there are > reference designs and documentation that describe how to do this. It > also has one SFP connector on it. The ML605 has the slowest speed > grade part on it that is only rated at 5 Gbs, but we used an ML605, > IBERT, and one of these : http://www.fastertechnology.com/fmc.html to > get four lanes running at over 7 Gbs. > > > Regards, > > John McCaskill > www.FasterTechnology.com John, Thanks for your reply. You've provided some good information which I'll look into. Roger.Article: 148331
You should be ok with this cable provided you have a new enough version of Impact (ISE). John Adair Enterpoint Ltd. - Home of Raggedstone2. The Spartan-6 PCI Express Development Board. On 7 July, 21:04, dmendesf <dmend...@gmail.com> wrote: > I have a Platform Cable USB: > > http://www.xilinx.com/products/devkits/HW-USB-G.htm > > I want to start playing with spartan-6 devices, but spartan-6 is not > in the Device Family Support list of this programmer. Seems that only > Platform Cable USB II supports spartan-6: > > http://www.xilinx.com/products/devkits/HW-USB-II-G.htm > > Is it really that way? If so, does anyone have a good explanation for > it? > > Thanks > > DanielArticle: 148332
On Jul 7, 4:10=A0pm, Casey Smith <cjs1...@gmail.com> wrote: > I'm troubleshooting a design that uses a XC3S50 as a way to take a > 125Mhz clock and, using 2 > DCMs, output 4 copies of it shifted 45deg from one another. =A0The 1st > DCM CLK0/90 ports give you the 0 and 90deg output clocks and the > second > DCM has a fixed phase offset so it's CLK0/90 ports give you the 45 and > 135deg clks. =A0However, the client didn't provide any external feedback > of > the clocks to the DCMs on the PCB and internal routing/gate delays are > screwing up > the phase relationship at the output pins of the FPGA. I'm having a > hell of a time > trying to constrain path delays to compensate. =A0Has anyone done > anything > like this before? =A0I have a post PAR simulation so I know what deltas > I'm looking for. =A0My thought was that there must be some way to > request a particular routing delay via a constraint. So far I've not > had much luck. It's the only thing the device is doing so I have > routing resources to burn.... the difference in routing delay I need > to compensate for is ~1ns. =A0If I > could match the internal DCM to PAD paths for the 0/90 outputs of each > DCM I could use the phase offset of one of the DCMs to set the phase > relationship between the two output clock groups and save a re-spin of > the board. Thoughts? > > Thanks, > Casey Hello Casey, It sounds like you are trying to take the clock signals and drive them directly out IO pins. That requires that the clocks leave the dedicated clock routing an use the general purpose routing. That will introduce skew to their phase relationship that is difficult to control. There is a better way to do this. Use the DDR registers in the IOBs to mirror the clock that is driving them by tying one of the inputs high, and the other low. By doing this, the clocks will stay on the dedicated clock routing, and you can more precisely control their phase relationship with the DCMs. While that is the approach that I would take, it is interesting to note that you can also hand route a net in the FPGA editor, and then have it saved as a directed routing constraint that you can put into the UCF file so that it will be repeatable. I have done that once, but only as a last resort. Regards, John McCaskill www.FasterTechnology.comArticle: 148333
On Mon, 5 Jul 2010 21:02:15 -0700 (PDT), Bryan <bryan.fletcher@avnet.com> wrote: >John, > >Thanks for your patience. I have been in contact with your FAE, and >he now has the document. If he hasn't gotten it to you within a day >or two, please let me know. > >Bryan Bryan, Got it, thanks. It's looking like V12.1 of the Xilinx software is much friendlier to Spartan6's than 11 was. Things compile bigger, but seem to be closer to right. We just redesigned a block of 32 8-pole 48-bit-wide IIR digital lowpass filters, from 6500 LUTs down to about 280, so they will compile under 12.1. Maybe 12.1 (or 12.2) and your procedure will fix our DRAM problems. JohnArticle: 148334
"Frank Buss" <fb@frank-buss.de> wrote in message news:894cs5thfx7j.15odz7d3o9fwz.dlg@40tude.net... > Switch to Altera. I've never heard of delivery problems for the Cyclone 2, > which a customer is still using for a product which I helped to program. > Even for the latest Cyclone 4 there are already some chips available in > the > Altera online shop. For the Cyclone 3 device there are hundreds of each > type in stock. Digikey, Farnell and other distributors have it in stock, > too. We get 26 weeks now om Stratix III (actually this was a few weeks ago)... I hope its temporary.. Supplier is whinig and doing the best they can they claim.Article: 148335
is it possible to program only one FPGA in the chain from EEPROM i.e. first FPGA without disconnecting other one from the loop.? Also, how do we generate the mcs file for the daisy chained FPGAs? Thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148336
Thanks for the suggestions everyone. I will be looking into them all over the next month. Since I posted I've developed my rough design a little and for future proofing would like to have 2 inputs and 2 outputs (the world is going 3d). Thanks again, Alan GArticle: 148337
On Jul 8, 8:03=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > is it possible to program only one FPGA in the chain from EEPROM i.e. fir= st > FPGA without disconnecting other one from the loop.? Yes. The difficulty is getting just one FPGA in a chain into program mode. > Also, how do we generate the mcs file for the daisy chained FPGAs? Xilinx Impact. There's an XAPP for that. > Thanks =A0 =A0 Ciao.Article: 148338
Avnet has the following. Still undergoing some testing. Scheduled to
start shipping later this month.
http://www.em.avnet.com/spartan6video
Ov9715 input => FPGA
DVI-D input => FPGA
FPGA => DVI-D output
FPGA => DisplayPort output (untested)
FPGA => ALI
We have reference designs for the following combinations:
Ov9715 input => FPGA => DVI-D output
DVI-D input => FPGA => DVI-D output
FPGA (test pattern) => ALI
FPGA (test pattern) => DisplayPort output
(untested)
Bryan
Article: 148339Can u give me a link to the xapp ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148340
On Jul 8, 11:57=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Can u give me a link to the xapp ? =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com <http://www.google.com/search?q=3DUG332> Same book symon pointed you to. The restriction is that it is only the 1st chip can be done by itself. (If you can get around the other problem I mentioned.) How to create an mcs file is here: <http://www.google.com/search?q=3Dimpact+user+guide> Cheers!Article: 148341
Another no reserve Craignell1 module on Ebay if anyone wants one of these cheaply. Item number #250663650739. John Adair Enterpoint Ltd.Article: 148342
On Jul 9, 1:16=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Jul 8, 11:57=A0am, "salimbaba" > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > Can u give me a link to the xapp ? =A0 =A0 =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > <http://www.google.com/search?q=3DUG332> =A0Same book symon pointed you > to. > > The restriction is that it is only the 1st chip can be done by > itself. =A0(If you can get around the other problem I mentioned.) > > How to create an mcs file is here: > <http://www.google.com/search?q=3Dimpact+user+guide> > > Cheers! Is that true? If the PROG signals to each FPGA are separate, then any of the chips can be put into programming mode. When being configured, once an FPGA has received its entire bitstream and is ready to enter user mode, it passes all configuration data received out to the next chip which does the same. I don't know if the FPGAs continue to pass the configuration data after they have transitioned into user mode, but if they do, you should be able to put one chip into configuration mode and pass the bitstream through the other FPGAs. Does anyone know if these FPGAs continue to pass configuration data after they enter user mode? RickArticle: 148343
On Jul 9, 11:56=A0am, rickman <gnu...@gmail.com> wrote: > On Jul 9, 1:16=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > > > > > On Jul 8, 11:57=A0am, "salimbaba" > > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > > Can u give me a link to the xapp ? =A0 =A0 =A0 =A0 > > > > --------------------------------------- =A0 =A0 =A0 =A0 > > > Posted throughhttp://www.FPGARelated.com > > > <http://www.google.com/search?q=3DUG332> =A0Same book symon pointed you > > to. > > > The restriction is that it is only the 1st chip can be done by > > itself. =A0(If you can get around the other problem I mentioned.) > > > How to create an mcs file is here: > > <http://www.google.com/search?q=3Dimpact+user+guide> > > > Cheers! > > Is that true? =A0If the PROG signals to each FPGA are separate, then any > of the chips can be put into programming mode. =A0When being configured, > once an FPGA has received its entire bitstream and is ready to enter > user mode, it passes all configuration data received out to the next > chip which does the same. =A0I don't know if the FPGAs continue to pass > the configuration data after they have transitioned into user mode, > but if they do, you should be able to put one chip into configuration > mode and pass the bitstream through the other FPGAs. > > Does anyone know if these FPGAs continue to pass configuration data > after they enter user mode? > > Rick Assuming that the programming pins are not re-used by the design they can be "preserved" in their boot-up mode. However this doesn't solve the issue of programming only the second device via EEPROM unless the first one magically comes up configured. Generally if you have special requirements for programming or reprogramming single devices they should have their own EEPROM or you should add a separate device to configure them. It's pretty easy to accomplish this from a microcontroller using slave serial mode. The XCFxxS series and older XC17xx and XC18xx devices only have an address reset, not a select. So again which ever device you program from them must have its bitstream starting at the first location in the device. So really you have pretty limited choices without either multiple configuration devices or an external configuration controller. Regards, GaborArticle: 148344
Hi folks-
I've asked this question on various FPGA formums so please excuse my
persistence. I'm hoping different eyes might see my question and be able to
help.
I'm looking for an HDL replacement for sprintf() that will do a float to
string conversion using the "%.3E" format specification. Such a conversion
in C source code is laborius in code and hence time consuming. I need to
convert in about 20 usec on a NIOS on FPGA clocking at 100 MHz.
I'm guessing the best way to do it is to use some C code coupled with
various HDL modules to reduce the C processing load. Such a solution is
acceptable to me as long as I can meet my conversion time target. The best
solution would be all in HDL if possible. I prefer verilog but will take
anything that works. An IP purchase is better than trying to figure out
somthing that isn't finished or is academic but at this point anything I can
find is better than nothing.
Can anyone recommend a good HDL sub for sprintf("%.3E")?
Thanks for your help on this,
John Speth
--- news://freenews.netfront.net/ - complaints: news@netfront.net ---
Article: 148345
On Jul 9, 1:27=A0pm, "John Speth" <johnsp...@yahoo.com> wrote:
> Hi folks-
>
> I've asked this question on various FPGA formums so please excuse my
> persistence. =A0I'm hoping different eyes might see my question and be ab=
le to
> help.
>
> I'm looking for an HDL replacement for sprintf() that will do a float to
> string conversion using the "%.3E" format specification. =A0Such a conver=
sion
> in C source code is laborius in code and hence time consuming. =A0I need =
to
> convert in about 20 usec on a NIOS on FPGA clocking at 100 MHz.
>
> I'm guessing the best way to do it is to use some C code coupled with
> various HDL modules to reduce the C processing load. =A0Such a solution i=
s
> acceptable to me as long as I can meet my conversion time target. =A0The =
best
> solution would be all in HDL if possible. =A0I prefer verilog but will ta=
ke
> anything that works. =A0An IP purchase is better than trying to figure ou=
t
> somthing that isn't finished or is academic but at this point anything I =
can
> find is better than nothing.
>
> Can anyone recommend a good HDL sub for sprintf("%.3E")?
>
> Thanks for your help on this,
>
> John Speth
>
> --- news://freenews.netfront.net/ - complaints: n...@netfront.net ---
Have a look at the following SNUG paper:
http://bear.cwru.edu/VHDL/doc/snug2002_20040606_slides.pdf
and the following page:
http://bear.ces.case.edu/VHDL/index.html
I have used this in the past. It is a bit cumbersome for some
functions, but it works.
Cheers,
-- Amal
Article: 148346On Jul 7, 5:07=A0pm, John McCaskill <jhmccask...@gmail.com> wrote: > On Jul 7, 4:10=A0pm, Casey Smith <cjs1...@gmail.com> wrote: > > > > > > > I'm troubleshooting a design that uses a XC3S50 as a way to take a > > 125Mhz clock and, using 2 > > DCMs, output 4 copies of it shifted 45deg from one another. =A0The 1st > > DCM CLK0/90 ports give you the 0 and 90deg output clocks and the > > second > > DCM has a fixed phase offset so it's CLK0/90 ports give you the 45 and > > 135deg clks. =A0However, the client didn't provide any external feedbac= k > > of > > the clocks to the DCMs on the PCB and internal routing/gate delays are > > screwing up > > the phase relationship at the output pins of the FPGA. I'm having a > > hell of a time > > trying to constrain path delays to compensate. =A0Has anyone done > > anything > > like this before? =A0I have a post PAR simulation so I know what deltas > > I'm looking for. =A0My thought was that there must be some way to > > request a particular routing delay via a constraint. So far I've not > > had much luck. It's the only thing the device is doing so I have > > routing resources to burn.... the difference in routing delay I need > > to compensate for is ~1ns. =A0If I > > could match the internal DCM to PAD paths for the 0/90 outputs of each > > DCM I could use the phase offset of one of the DCMs to set the phase > > relationship between the two output clock groups and save a re-spin of > > the board. Thoughts? > > > Thanks, > > Casey > > Hello Casey, > > It sounds like you are trying to take the clock signals and drive them > directly out IO pins. That requires that the clocks leave the > dedicated clock routing an use the general purpose routing. That will > introduce skew to their phase relationship that is difficult to > control. > > There is a better way to do this. Use the DDR registers in the IOBs to > mirror the clock that is driving them by tying one of the inputs high, > and the other low. =A0By doing this, the clocks will stay on the > dedicated clock routing, and you can more precisely control their > phase relationship with the DCMs. > > While that is the approach that I would take, it is interesting to > note that you can also hand route a net in the FPGA editor, and then > have it saved as a directed routing constraint that you can put into > the UCF file so that it will be repeatable. I have done that once, but > only as a last resort. > > Regards, > > John McCaskillwww.FasterTechnology.com Thanks John, I've used the DDR forwarding trick before with success but it's not cutting it in this case. I have been exploring the FPGA editor but was hoping there might be an easier way. I'll give the hand route option another look. This problem might be the perfect opportunity to learn. CaseyArticle: 148347
Hi, I have a design that use some asynchronous signals. I have already set a FROM TO constraint in the ucf for the path. I am using a Spartan 3E 1600-5fg400 with Xilinx ISE 12 on top of that, I located the optimum path that the signal should take on the chip. If I let PAR run automatically, it does not map it on that path. I would like to know if there is a way that I can tell PAR that this signal has the highest priority and that it should route it first before routing anything else. Alternatively, is there a way I can manually set the route. I have done this before under "map -> Manually place and route" but when PAR runs, it remaps it. I would like a way to set it so that if the project is cleaned up using "project->clean project files", the manual route is not erased. It's hard to explain. Hopefully somebody has done this before. Thanks a lot, AmishArticle: 148348
On Jul 12, 10:32=A0am, Amish Rughoonundon <amishrughoonun...@gmail.com> wrote: > Hi, > =A0I have a design that use some asynchronous signals. I have already > set a FROM TO constraint in the ucf for the path. > > I am using a Spartan 3E 1600-5fg400 with Xilinx ISE 12 > > on top of that, I located the optimum path that the signal should take > on the chip. > > If I let PAR run automatically, it does not map it on that path. > > I would like to know if there is a way that I can tell PAR that this > signal has the highest priority and that it should route it first > before routing anything else. > > Alternatively, is there a way I can manually set the route. I have > done this before under "map -> Manually place and route" but when PAR > runs, it remaps it. > > I would like a way to set it so that if the project is cleaned up > using "project->clean project files", the manual route is not erased. > > It's hard to explain. Hopefully somebody has done this before. > > Thanks a lot, > Amish Hello Amish, Yes, it is possible to manually place and route a signal, and then put that information into the UCF file so you only have to do it once. I have done it, but only as a last resort. Can you tell us a bit about what you are trying to do with the asynchronous signals that needs this sort of placement? There may be a better way to accomplish your goal. If you really want to hand route the signals, use the design in FPGA Editor and set the edit mode to read/write. Select the net to route, and unroute it. Reroute it by hand. Then select Directed Routing Constraints from the Tools menu. This will bring up a new window that will let you select the nets you are interested in and will create placement and routing constraints that you can put into the UCF for the design. After that, these constraints will cause the tools to replicate the routing every time you run place and route. Regards, John McCaskill www.FasterTechnology.comArticle: 148349
On Jul 12, 12:36=A0pm, John McCaskill <jhmccask...@gmail.com> wrote:
> On Jul 12, 10:32=A0am, Amish Rughoonundon <amishrughoonun...@gmail.com>
> wrote:
>
>
>
>
>
> > Hi,
> > =A0I have a design that use some asynchronous signals. I have already
> > set a FROM TO constraint in the ucf for the path.
>
> > I am using a Spartan 3E 1600-5fg400 with Xilinx ISE 12
>
> > on top of that, I located the optimum path that the signal should take
> > on the chip.
>
> > If I let PAR run automatically, it does not map it on that path.
>
> > I would like to know if there is a way that I can tell PAR that this
> > signal has the highest priority and that it should route it first
> > before routing anything else.
>
> > Alternatively, is there a way I can manually set the route. I have
> > done this before under "map -> Manually place and route" but when PAR
> > runs, it remaps it.
>
> > I would like a way to set it so that if the project is cleaned up
> > using "project->clean project files", the manual route is not erased.
>
> > It's hard to explain. Hopefully somebody has done this before.
>
> > Thanks a lot,
> > Amish
>
> Hello Amish,
>
> Yes, it is possible to manually place and route a signal, and then put
> that information into the UCF file so you only have to do it once. =A0I
> have done it, but only as a last resort.
>
> Can you tell us a bit about what you are trying to do with the
> asynchronous signals that needs this sort of placement? There may be a
> better way to accomplish your goal.
>
> If you really want to hand route the signals, use the design in FPGA
> Editor and set the edit mode to read/write. =A0Select the net to route,
> and unroute it. Reroute it by hand. =A0Then select Directed Routing
> Constraints from the Tools menu. =A0This will bring up a new window that
> will let you select the nets you are interested in and will create
> placement and routing constraints that you can put into the UCF for
> the design.
>
> After that, these constraints will cause the tools to replicate the
> routing every time you run place and route.
>
> Regards,
>
> John McCaskillwww.FasterTechnology.com
Thanks for the quick answer. It seems to work now.
This is what I am trying to route. I need the fastest possible
response time under 5 ns.
dsp_ms_three_n is an external signal to the chip
s_done comes from a state machine running at 102.4 MHz which is also
the clock rate for the communication to a dsp actuating
dsp_ms_three_n
[CODE]
-- ACKNOWLEGEMENT
--
-- Intentional latch created to obtain
-- the fastest response time possible
--
p_doneLatch : process(s_done, dsp_ms_three_n)
begin
if(s_done =3D '1') then
s_doneLatch <=3D '1';
elsif(dsp_ms_three_n =3D '0') then
s_doneLatch <=3D '0';
end if;
end process p_doneLatch;
dsp_ack <=3D 'Z' when dsp_ms_three_n =3D '1' else s_doneLatch;
[/CODE]
I am not sure how to do this synchornously with incurring the
additional clock cycle and having to add double buffers on ms_three_n
Amish
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