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shoonya wrote: > Hi, > > I recently got the Actel Smartfusion eval kit. Since I use Linux, I am > running the windows Libero IDE under wine. I tried to install the Linux version of Libero, but gave up when it looked as though the tools would not work. Next I tried Win XP pro under the open source version of O/Sun VirtualBox. Install was easy, but screen cramped, and couldn't use USB. Finally installed the closed source version of VirtualBox. USB ports can be forwarded, and screen is larger once the windows and linux desktops are combined. Both USB connections to my Igloo nano board were recognised by Windows, and looked usable, but have not yet done any serious development. Jan CoombsArticle: 148101
Antti <antti.lukats@googlemail.com> wrote: > the X-7 roadmap and all device table are no online, > and the ARM11 is coming is also all public knowledge, but.. where? in > what family? > spartan is dead, now is Artix, und Kintex? but where is ARM11? > in BULLSHITIX-8 release? > I wonder. of course its very interesting to see how much mess Xilinx > is able > to organize with the 7 series, right now Xilinx online shop list > exactly 2 devices of Spartan-6ES both going to avnet no stock > there was initial stock of 45 pieces of Spartan-6 at digikey > after that was depleted digikey has not received any new s-6 silicon. > so, when comes spartan-6 general availability? > does it makes to wait? > or maybe it makes more sense to wait the Artix-7? > or maybe..look for alternatives? X*l*nx is going the *tm*l Way: Annnouce early, release later (or never) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148102
On Jun 21, 11:27=A0am, Antti <antti.luk...@googlemail.com> wrote: > the X-7 roadmap and all device table are no online, > and the ARM11 is coming is also all public knowledge, but.. where? in > what family? > > spartan is dead, now is Artix, und Kintex? but where is ARM11? > > in BULLSHITIX-8 release? > > I wonder. of course its very interesting to see how much mess Xilinx > is able > to organize with the 7 series, right now Xilinx online shop list > exactly 2 devices of Spartan-6ES both going to avnet no stock > there was initial stock of 45 pieces of Spartan-6 at digikey > after that was depleted digikey has not received any new s-6 silicon. > > so, when comes spartan-6 general availability? > does it makes to wait? > or maybe it makes more sense to wait the Artix-7? > or maybe..look for alternatives? > > Antti With great trepidation I write the following. Details on the future product with an ARM Cortex A9-MPcore (not ARM11) were not announced today. There is some limited information online here: http://www.xilinx.com/technology/roadmap/processing-platform.htm While the product name of Spartan will stop with the current Spartan-6 Family. The concepts that the Spartan name embodies, low cost, high volume and low power, will continue under the new Artix Family name. I understand your criticisms of the Spartan-6 production availability over the last few months. If you check the distributor stocking levels over the next 1-2 months you will see rapid improvement in this area. Ed McGettigan -- Xilinx Inc.Article: 148103
They would be better concentrating on just getting the announced Spartan-6 and Virtex-6 families actually out there in some numbers. I am having to switch my team to doing Altera boards whilst we are in limbo land between Spartan-3/Virtex-5 and nearly not available parts of Spartan-6/Virtex-6. As everyone who knows us we have been strong supporters of the Xilinx product line but we can't do anything without silicon. The 144 week lead times Xilinx/Avnet combination that often comes up just makes it worse and I have several new development boards ready to launch subject to actually having silicon to put on them. The new things coming do look good but I will surprised if they are really going t be available within 2 years and that might as well be 50 years as far as me deploying people into product development based on these parts. A lot will depend on what price, and what power profile, the new parts have. We all remember the Excalibar non- starter. There does seem to be something of a marketing war between Altera and Xilinx and I think this isn't helping. They both have good products currently but it wouldn't be the first time one or other went off and lost sight of what customers actually wanted. John Adair Enterpoint Ltd. On 21 June, 19:27, Antti <antti.luk...@googlemail.com> wrote: > the X-7 roadmap and all device table are no online, > and the ARM11 is coming is also all public knowledge, but.. where? in > what family? > > spartan is dead, now is Artix, und Kintex? but where is ARM11? > > in BULLSHITIX-8 release? > > I wonder. of course its very interesting to see how much mess Xilinx > is able > to organize with the 7 series, right now Xilinx online shop list > exactly 2 devices of Spartan-6ES both going to avnet no stock > there was initial stock of 45 pieces of Spartan-6 at digikey > after that was depleted digikey has not received any new s-6 silicon. > > so, when comes spartan-6 general availability? > does it makes to wait? > or maybe it makes more sense to wait the Artix-7? > or maybe..look for alternatives? > > AnttiArticle: 148104
Ed, We have a successful product based on V4FX, which uses pretty much every resource on that chip (PPC, MGTs, DSP48s, etc). We are looking at designing a higher performance version of that product. The only Xilinx path we have at the moment is V5, which is already 2 generations behind and the performance gain we will get is just barely enough... On the other hand, V8 or whatever it will be called seems to be too far away... In other words, I have to tell you that I don't appreciate Xilinx dropping PPC from the product line before a replacement was actually ready... That's not to mention cost of porting everything embedded to ARM when the replacement actually comes... /Mikhail "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:368a1eff-30d6-47b6-bec9-7330e15b5ee6@d8g2000yqf.googlegroups.com... On Jun 21, 11:27 am, Antti <antti.luk...@googlemail.com> wrote: > the X-7 roadmap and all device table are no online, > and the ARM11 is coming is also all public knowledge, but.. where? in > what family? > > spartan is dead, now is Artix, und Kintex? but where is ARM11? > > in BULLSHITIX-8 release? > > I wonder. of course its very interesting to see how much mess Xilinx > is able > to organize with the 7 series, right now Xilinx online shop list > exactly 2 devices of Spartan-6ES both going to avnet no stock > there was initial stock of 45 pieces of Spartan-6 at digikey > after that was depleted digikey has not received any new s-6 silicon. > > so, when comes spartan-6 general availability? > does it makes to wait? > or maybe it makes more sense to wait the Artix-7? > or maybe..look for alternatives? > > Antti With great trepidation I write the following. Details on the future product with an ARM Cortex A9-MPcore (not ARM11) were not announced today. There is some limited information online here: http://www.xilinx.com/technology/roadmap/processing-platform.htm While the product name of Spartan will stop with the current Spartan-6 Family. The concepts that the Spartan name embodies, low cost, high volume and low power, will continue under the new Artix Family name. I understand your criticisms of the Spartan-6 production availability over the last few months. If you check the distributor stocking levels over the next 1-2 months you will see rapid improvement in this area. Ed McGettigan -- Xilinx Inc.Article: 148105
On Jun 21, 3:29=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > They would be better concentrating on just getting the announced > Spartan-6 and Virtex-6 families actually out there in some numbers. I > am having to switch my team to doing Altera boards whilst we are in > limbo land between Spartan-3/Virtex-5 and nearly not available parts > of Spartan-6/Virtex-6. As everyone who knows us we have been strong > supporters of the Xilinx product line but we can't do anything without > silicon. The 144 week lead times Xilinx/Avnet combination that often > comes up just makes it worse and I have several new development boards > ready =A0to launch subject to actually having silicon to put on them. > > The new things coming do look good but I will surprised if they are > really going t be available within 2 years and that might as well be > 50 years as far as me deploying people into product development based > on these parts. A lot will depend on what price, and what power > profile, the new parts have. We all remember the Excalibar non- > starter. > > There does seem to be something of a marketing war between Altera and > Xilinx and I think this isn't helping. They both have good products > currently but it wouldn't be the first time one or other went off and > lost sight of what customers actually wanted. > > John Adair > Enterpoint Ltd. > > On 21 June, 19:27, Antti <antti.luk...@googlemail.com> wrote: > > > > > the X-7 roadmap and all device table are no online, > > and the ARM11 is coming is also all public knowledge, but.. where? in > > what family? > > > spartan is dead, now is Artix, und Kintex? but where is ARM11? > > > in BULLSHITIX-8 release? > > > I wonder. of course its very interesting to see how much mess Xilinx > > is able > > to organize with the 7 series, right now Xilinx online shop list > > exactly 2 devices of Spartan-6ES both going to avnet no stock > > there was initial stock of 45 pieces of Spartan-6 at digikey > > after that was depleted digikey has not received any new s-6 silicon. > > > so, when comes spartan-6 general availability? > > does it makes to wait? > > or maybe it makes more sense to wait the Artix-7? > > or maybe..look for alternatives? > > > Antti- Hide quoted text - > > - Show quoted text - > The 144 week lead times Xilinx/Avnet combination that often I have seen the same and it is just the result of faulty data. I had flagged this earlier and thought that it was being fixed, but it appears to have fallen through the cracks somewhere. > We all remember the Excalibar non-starter. That was an Altera product line (NIOS, MIPS, ARM processor+FPGA), not a Xilinx one. Ed McGettigan -- Xilinx Inc.Article: 148106
Hi guys, at first some background information: I'm doing a study project for some weeks now which is about "VHDL development environment for FPGA". The first goal was to set up ISE WebPack under Ubuntu Linux to work with the Nexys 2 board. This took me a lot of time because of the bad documentation of Digilent concerning the programming of the board under Linux. With the script nexys2prog I found a way to do this. Second task was to implement the MIPS I compatible CPU Plasma. I was able to do this with mainly some pinout-changes (ucf file). Third task was to build a gcc-cross-toolchain for mips-elf. Now I'm able to run programs (located in internal RAM on FPGA, ram_image.vhd) on the CPU and to communicate with the board via UART<->RS-232<->terminal. I want to load programs to external RAM via bootldr and execute them. Now my questions: 1. What is the cause that I did not find any information on the internet about an implementation of Plasma on Nexys 2 ??? 2. How can I interface the RAM Chip on Nexys 2 ? The Problem: Plasma needs 32 bit access, but the memory bus of the board is only 16 bits wide. This module (http://opencores.org/websvn,filedetails?repname=plasma&path=%2Fplasma%2Ftrunk%2Fvhdl%2Fplasma_if.vhd) interfaces with the Spartan-3 Starter Kit Board (http://www.digilentinc.com/Data/Products/S3BOARD/S3BOARD_RM.pdf - page 11). The memory interface of Nexys2 looks like this (RAM = IC13) (http://www.digilentinc.com/Data/Products/NEXYS2/Nexys2_rm.pdf - page 13-14) My idea: Memory should be a black box from CPU perspective which provides 32 bit access. In this black box, maybe with double clock: first 16 bit of data is at address x, second 16 bit is at address y. These two chunks of data should be read sequentially and then merged to a 32 bit word, write access vice versa. IMHO this will just be a few lines of code..but I just have no clue how to do it in VHDL. Anyone...ideas, suggestions ? Greetings, Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148107
On Jun 21, 6:11=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > With great trepidation I write the following. > ... I sincerely appreciate the voice of an engineer to help temper what appears to be a marketer's shameful act of offering vaporware to help obfuscate the "series 6" introduction woes. I don't use "vaporware" in a very negative sense but I thought the FPGA marketing people had learned their hard lessons that promising something way, way, way in advance of production is a bad thing. "I'd like an XC7A20-FTG256 please, any speed grade as long as the price is decent and the tools support the chip properly." Despite the mention of "early access" in the online teaser, I see a too-recent history of the road to production being long and labored. I'm excited for the future. But since every calendar year is like 15 years in the life of an FPGA (figured like dog-years) we'll see childhood, adolescence, and early adulthood transition toward middle- aged by the time I expect we'll see parts. Please help convince your marketing people to look at what's happened in the many, many years leading up to this announcement. Learn from those mistakes or repeat them. Happy engineers are profitable engineers.Article: 148108
On Mon, 21 Jun 2010 11:45:47 -0700, Rob Gaddi <rgaddi@technologyhighland.com> wrote: >On 6/21/2010 11:27 AM, Antti wrote: >> the X-7 roadmap and all device table are no online, >> and the ARM11 is coming is also all public knowledge, but.. where? in >> what family? >> >> spartan is dead, now is Artix, und Kintex? but where is ARM11? >> >> in BULLSHITIX-8 release? >> >> I wonder. of course its very interesting to see how much mess Xilinx >> is able >> to organize with the 7 series, right now Xilinx online shop list >> exactly 2 devices of Spartan-6ES both going to avnet no stock >> there was initial stock of 45 pieces of Spartan-6 at digikey >> after that was depleted digikey has not received any new s-6 silicon. >> >> so, when comes spartan-6 general availability? >> does it makes to wait? >> or maybe it makes more sense to wait the Artix-7? >> or maybe..look for alternatives? >> >> >> Antti > >Right now I'm working on two S6 projects, both of which are absolute >disasters due to problems with the toolchain. My DRAM problem from a >month ago, Xilinx ultimately told me was my problem and they washed >their hands of it. Now on my other project, version 12 of the tools >uses 10% more of the chip than version 11 and neither is willing to >respect a simple IOB=FORCE. I've got a WebCase crawling along on it, >but so far have been trained to not expect much from that process. Their silicon is quite good. But Xilinx seems to be in a place I've seen some other big-technology companies: their software and software culture are so broken they may never be fixed. The solution is simple: they should totally open up the architecture. Then all sorts of 3rd party EDA vendors would rush to offer us competitive software, spot tools and whole chains. That would soon give us choices between quality tools, and light a fire under the chairs of their in-house guys. JohnArticle: 148109
On 6/18/2010 11:25 AM, Gabor wrote: > On Jun 18, 1:27 pm, Rob Gaddi<rga...@technologyhighland.com> wrote: >> I'm no luck figuring out how to implement the timing constraints for >> something that, to my mind, ought to be pretty simple. I'm connected to >> an external synchronous logic chip. For now let's call it a regular >> 74HC74 flip flop, but the details are unimportant. My FPGA outputs D >> and CLK to the 74HC74, and reads back Q. >> >> The FPGA has a single global clock net, call it SysClk. I've got a >> state machine running on SysClk generating both data and clock for this >> widget; the clock is running at a sufficiently low rate that it's being >> generated by a simple, rising-edge only, divide-by-N from my master >> clock. My logic defines both D and CLK in a way that they're registered >> outputs and Q as a registered input with no logic; such that all of them >> should be able to be pushed into the IOBs. >> >> The 74HC74 datasheet tells me that I've got setup time (Ts), hold time >> (Th), and clock-to-output delay (Tcko). How do I go about communicating >> these requirements to the Xilinx toolchain? Clearly it's some >> combination of OFFSET constraints, but what are the magic words? >> >> UG612 discusses the use of the REFERENCE_PIN qualifier to indicate that >> the output data is referred to the output clock, but the example doesn't >> give any advice that would connect those OFFSET constraints to only >> define the relationship between D and CLK, not the entire world and CLK. >> And I can't seem to find any information whatsoever that would let me >> define the relationship between CLK and Q. >> >> I've gone through the Constraints Guide. I've gone through UG612. I've >> gone through Austin's 5 part series over on the Xilinx forums. And I'm >> still lost. Anyone have any revelations for me? >> >> -- >> Rob Gaddi, Highland Technology >> Email address is currently out of order > > Basically, you are using a source synchronous output clock to your > flip-flop. There is no constraint to my knowledge that would do > the job you're looking for which is to define the relative timing > on two outputs. This should be correct by design. i.e. if you > push both CLK and Q outputs into IOB flops, using DDR flops if > necessary for the clock, you should have essentially zero timing > difference between CLK and Q if they are switching on the same > edge of the same global clock. Make your Tsu and Th based on > the relative timing to the IOB flops, for example making CLK > go high on the falling edge of the internal clock and changing > Q on the next rising edge to get 1/2 cycle of hold time. > > HTH, > Gabor I was afraid that was the answer. Unfortunately I'm running into a miserable time of things with that answer. I've got 16 pins being driven from identical signals (the SCLK for 16 simultaneous ADCs). I'm turning on a few optimizations in the MAP stage in order to try to get some of the resource count down, including equivalent_register_removal. Unfortunately, this means that my 16 SCLKs are being equivalented down to only one flip-flop, which then fails MAP because it can no longer perform the IOB=FORCE. Basically, the tool cleverly decides to optimize down my logic without checking to see what constraints it's under. I went through the Spartan 6 HDL libraries, figuring I'd just give up on pretty code and instantiate an OFD like I would have on a Spartan 3. No such luck; they've pulled it out of the library. There's an ODDR, but that claims to need both of the clocks connected to it. There's an OFD in the schematic library, but you can't reference it from VHDL. Turning off equivalent_register_removal doesn't work, because my design, while only 80% full on LUTs, claims to have no place to place the rest and fails. And turning off equivalent_register_removal locally in the entity under question doesn't work, because the tools just flat out ignore me. This is, of course, all under ISE 11.5. Under version 12.1 the synthesis builds to take 10% more LUTs, making the design even more unplaceabler. So many walls, so little time to beat my head against each one. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148110
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> writes: > [...] > Their silicon is quite good. But Xilinx seems to be in a place I've > seen some other big-technology companies: their software and software > culture are so broken they may never be fixed. > > The solution is simple: they should totally open up the architecture. > Then all sorts of 3rd party EDA vendors would rush to offer us > competitive software, spot tools and whole chains. That would soon > give us choices between quality tools, and light a fire under the > chairs of their in-house guys. The linux version of the 12.1 ISE is a joke: custom build scripts, separate library directories, custom bashrc entries required, etc. (as opposed to an RPM and use of the system libraries). -- Randy Yates % "The dreamer, the unwoken fool - Digital Signal Labs % in dreams, no pain will kiss the brow..." mailto://yates@ieee.org % http://www.digitalsignallabs.com % 'Eldorado Overture', *Eldorado*, ELOArticle: 148111
On Jun 17, 4:29=A0am, rickman <gnu...@gmail.com> wrote: > Why is Google too dense to fix their SPAM problem? =A0There are so many > ways they could address the problem and as far as I can tell, they > treat it as a PR concern and have tried to give us a control that does > nothing! =A0You can flag posts as being spam very easily now. =A0Each pos= t > has a link at the bottom that lets you report spam. =A0There are times > when I flag every post that come into the groups I read. =A0I see > nothing happen with that SPAM. =A0The existing SPAM posts are not > deleted. =A0The same SPAM posts are not prevented. =A0In other words, it > is a control that is not wired into anything. I've actually been thinking about starting a series of forums to deal with this very problem. The "comp" and other hierarchies on usenet are simply too polluted with SPAM these days. The only way to break the cycle is to break away from usenet and move to a privately managed system that can enforce some rules. The boards, of course, would have to have some advertising to support the costs of setup and running, but would otherwise be free to users. Spammers would just not last very long at all. C.A.F. regulars could certainly be setup as moderators to raise the quality of the board even further. A modern board like that could include attachments and other very useful modern features. If this if of interest please email me off list. I'll decide based on the level of interest. x@y.z where: x =3D martin_05 y =3D rocketmail z =3D com -MartinArticle: 148112
On Jun 21, 7:37=A0pm, martin_05 <martin...@rocketmail.com> wrote: > On Jun 17, 4:29=A0am, rickman <gnu...@gmail.com> wrote: > > > Why is Google too dense to fix their SPAM problem? =A0There are so many > > ways they could address the problem and as far as I can tell, they > > treat it as a PR concern and have tried to give us a control that does > > nothing! =A0You can flag posts as being spam very easily now. =A0Each p= ost > > has a link at the bottom that lets you report spam. =A0There are times > > when I flag every post that come into the groups I read. =A0I see > > nothing happen with that SPAM. =A0The existing SPAM posts are not > > deleted. =A0The same SPAM posts are not prevented. =A0In other words, i= t > > is a control that is not wired into anything. > > I've actually been thinking about starting a series of forums to deal > with this very problem. =A0The "comp" and other hierarchies on usenet > are simply too polluted with SPAM these days. =A0The only way to break > the cycle is to break away from usenet and move to a privately managed > system that can enforce some rules. =A0The boards, of course, would have > to have some advertising to support the costs of setup and running, > but would otherwise be free to users. =A0Spammers would just not last > very long at all. =A0C.A.F. regulars could certainly be setup as > moderators to raise the quality of the board even further. =A0A modern > board like that could include attachments and other very useful modern > features. > > If this if of interest please email me off list. =A0I'll decide based on > the level of interest. > > x...@y.z > where: > > x =3D martin_05 > y =3D rocketmail > z =3D com > > -Martin These forums for the most part already exist: http://forums.xilinx.com http://www.alteraforums.com http://www.latticesemi.com/support/forums.cfm?source=3Dtopnav Ed McGettigan -- Xilinx Inc.Article: 148113
>shoonya wrote: >> Hi, >> >> I recently got the Actel Smartfusion eval kit. Since I use Linux, I am >> running the windows Libero IDE under wine. > >I tried to install the Linux version of Libero, but gave up when it >looked as though the tools would not work. > >Next I tried Win XP pro under the open source version of O/Sun >VirtualBox. Install was easy, but screen cramped, and couldn't use USB. > >Finally installed the closed source version of VirtualBox. USB >ports can be forwarded, and screen is larger once the windows and >linux desktops are combined. > >Both USB connections to my Igloo nano board were recognised by >Windows, and looked usable, but have not yet done any serious >development. > >Jan Coombs > Hi Jan, I don't want to buy a windows license. I'll need it if I have to run it under virtualbox. The flaspro3 programmer is implemented in a proasic chip - if only they provide a native linux driver for it. So for now I have installed it on an old laptop with windows xp on it which I have kept around for such situations :(. Too bad the tools get in the way of developing things. Regards Manish --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148114
On Jun 22, 9:39=A0am, "shoonya" <manish.paradkar@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >shoonya wrote: > >> Hi, > > >> I recently got the Actel Smartfusion eval kit. Since I use Linux, I am > >> running the windows Libero IDE under wine. > > >I tried to install the Linux version of Libero, but gave up when it > >looked as though the tools would not work. > > >Next I tried Win XP pro under the open source version of O/Sun > >VirtualBox. Install was easy, but screen cramped, and couldn't use USB. > > >Finally installed the closed source version of VirtualBox. USB > >ports can be forwarded, and screen is larger once the windows and > >linux desktops are combined. > > >Both USB connections to my Igloo nano board were recognised by > >Windows, and looked usable, but have not yet done any serious > >development. > > >Jan Coombs > > Hi Jan, > > I don't want to buy a windows license. I'll need it if I have to run it > under virtualbox. > > The flaspro3 programmer is implemented in a proasic chip - if only they > provide a native linux driver for it. > > So for now I have installed it on an old laptop with windows xp on it whi= ch > I have kept around for such situations :(. > > Too bad the tools get in the way of developing things. > > Regards > Manish > thats YOUR problem that you dont want to buy windows license you can of course program actel chip under linux, but not with flashpro, so its your choice, want flashpro, get windows, easy as that. windows license doesnt cost that much that it would a be real problem to use proper FPGA tools (flashpro) Antti PS we have our own actel flash tools, and yes they have open interface so they can be used under linux if anyone interestedArticle: 148115
"Antti" <antti.lukats@googlemail.com> wrote in message news:b45d75d9-16c6-4518-ac5a-2fe068a0f401@x27g2000yqb.googlegroups.com... > the X-7 roadmap and all device table are no online, > and the ARM11 is coming is also all public knowledge, but.. where? in > what family? > > spartan is dead, now is Artix, und Kintex? but where is ARM11? > > in BULLSHITIX-8 release? > > I wonder. of course its very interesting to see how much mess Xilinx > is able > to organize with the 7 series, right now Xilinx online shop list > exactly 2 devices of Spartan-6ES both going to avnet no stock > there was initial stock of 45 pieces of Spartan-6 at digikey > after that was depleted digikey has not received any new s-6 silicon. > > so, when comes spartan-6 general availability? > does it makes to wait? > or maybe it makes more sense to wait the Artix-7? > or maybe..look for alternatives? > > > Antti I started with Xilinx when 100 logic blocks was the biggest device they made. I gave up with them a few years ago because of the nonsense you describe. Vapourware, no stock, no distribution. I switched to Lattice and that was my best FPGA decision ever - not leading edge but it just works. Michael KellettArticle: 148116
On Mon, 21 Jun 2010 18:24:48 -0700, Rob Gaddi <rgaddi@technologyhighland.com> wrote: >> Basically, you are using a source synchronous output clock to your >> flip-flop. There is no constraint to my knowledge that would do >> the job you're looking for which is to define the relative timing >> on two outputs. This should be correct by design. i.e. if you >> push both CLK and Q outputs into IOB flops, using DDR flops if >> necessary for the clock, you should have essentially zero timing >> difference between CLK and Q if they are switching on the same >> edge of the same global clock. Make your Tsu and Th based on >> the relative timing to the IOB flops, for example making CLK >> go high on the falling edge of the internal clock and changing >> Q on the next rising edge to get 1/2 cycle of hold time. >> >> HTH, >> Gabor > >I was afraid that was the answer. Unfortunately I'm running into a >miserable time of things with that answer. I've got 16 pins being >driven from identical signals (the SCLK for 16 simultaneous ADCs). I'm >turning on a few optimizations in the MAP stage in order to try to get >some of the resource count down, including equivalent_register_removal. You should be able to attach an "equivalent-register-removal=no" attribute to the specific signal in VHDL source, and it should override the global setting (tools issues apart; i haven't tried on S6). I don't know if UCF would work - I put it in the source to prevent synthesis being too clever... But the documentation doesn't exactly make it obvious that you can override the (useful) global setting... >And turning off equivalent_register_removal locally in the >entity under question doesn't work, because the tools just flat out >ignore me. This is, of course, all under ISE 11.5. Under version 12.1 >the synthesis builds to take 10% more LUTs, making the design even more >unplaceabler. Try it on the signal... unfortunately you probably can't go back to ISE10, where it works... - BrianArticle: 148117
rickman wrote: > On Jun 16, 9:31 am, Symon <symon_bre...@hotmail.com> wrote: >> On 6/15/2010 12:57 PM, LC wrote: >> >>> Symon wrote: >>>> On 6/14/2010 1:45 PM, LC wrote: >>>>> Should I expect that this would be the right up limit I could do it ? >>>>> Is there any clever design of this frontend to allow higher speed ? >>>> Does XAPP265 give you any architectural hints that you can use in your >>>> Altera part? >>>> HTH., Syms. >>> Tks, Symon, >>> Indeed there are some variations induced by this reading that I'll try. >>> Thanks. >>> Luis C. >> Hi Luis, >> You might want to pay particular attention to the DDR registers in the >> IOBs. I expect your Altera part has the same features, but I dunno for >> sure. The registers mean that your internal logic can run at half the >> speed of the external signals. Which is nice. >> HTH, Syms. > > That's what I would suggest. By using the DDR registers, the data > stream can be split into odd/even words with parallel paths. Then > each stream would only need to run at half the rate on the I/O pins. > Since you already have the 500 MHz clock you can just divide that by > two to generate two enables, one for the odd and one for the even data > streams. I've never used the DDR registers. You probably want to > look closely at the example code that Altera provides. > > Rick Many thaks Folks, Very good tips. tks, Luis C.Article: 148118
Hey all, Does anyone know of an ASIC chip from NXP, Motorola etc which will interface a webcam using the UVC (USB video class) protocol. Ideally the chip would simple as possible and drop out 8/10/12/16-bits per clock cycle which I can then feed into the FPGA into a internal queue or 2D register matrix... I've heard several DSP chips would provide this functionallity, however I'm not sure what to look for... <EDIT> While writing this post I found my answer, google "UVC controller or interface" etc. an example chip from Genesys Logic would be the GL860A. Thought I might post this up if someone in the future comes looking for the answer...Article: 148119
<Update / Edit on my own thread> The GL860A is not the type of chip that I'm looking for. This chip takes analog video and encodes to a UVC compliant stream. What I'm looking for is a chip which activates the USB webcam and outputs the result as a simple stream of 1s and 0s representing the pixels.Article: 148120
Hi, I successfully ported Petalinux on the XUPV5-LX110T FPGA board using 8 KB of Data/Instruction Cache. My SDRAM is 256 MB (MT4HTF3264HY-667F1). However when I create a file (vi myFile) at the /var/tmp location, myFile cannot be bigger than 25 MB otherwise Petalinux will complain that my system is out of memory and it will log me off. Does anyone knows how to solve this issue. Any help will be greatly appreciated it. Petalinux version: 0.40-rc3 --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148121
On Jun 22, 8:26=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > ... > These forums for the most part already exist: > > http://forums.xilinx.com > http://www.alteraforums.com > http://www.latticesemi.com/support/forums.cfm?source=3Dtopnav > > Ed McGettigan > ... All, I definetly prefer some spam to the (possible) censorship by the brands... Obviously it's a personal opinion and I do know that a lot of spam could be a kind of censorship SandroArticle: 148122
On Jun 21, 7:37=A0pm, martin_05 <martin...@rocketmail.com> wrote: > enforce some rules. =A0The boards, of course, would have > to have some advertising to support the costs of setup and running, > but would otherwise be free to users. =A0Spammers would just not last > very long at all. =A0C.A.F. regulars could certainly be setup as > moderators to raise the quality of the board even further. =A0A modern > board like that could include attachments and other very useful modern > features. you can create a group within "google groups" and moderate it. It is "sponsored" by google-ads, which is nice. No banners, no popups, and usually the ads are relevant to the content of the page being currently viewed.Article: 148123
On Tue, 22 Jun 2010 07:45:05 -0700 (PDT), rich12345 <aiiadict@gmail.com> wrote: >On Jun 21, 7:37 pm, martin_05 <martin...@rocketmail.com> wrote: >> enforce some rules. The boards, of course, would have >> to have some advertising to support the costs of setup and running, >> but would otherwise be free to users. Spammers would just not last >> very long at all. C.A.F. regulars could certainly be setup as >> moderators to raise the quality of the board even further. A modern >> board like that could include attachments and other very useful modern >> features. > >you can create a group within "google groups" and moderate it. It is >"sponsored" by google-ads, which is nice. No banners, no popups, and >usually the ads are relevant to the content of the page being >currently viewed. So because of the spam-floods from googlegroups that render much of Usenet a less than happy experience for many users, one should move to googlegroups and put eyeballs on their sponsored advertisements? How nice of them to provide such a service... -- Rich Webb Norfolk, VAArticle: 148124
shoonya wrote: > I don't want to buy a windows license. I'll need it if I have to run it > under virtualbox. If you can borrow an XP pro install disk, and get something out of a skip with an XP pro sticker on it, then you have done your part towards keeping windows alive! Jan Coombs
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