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> >you can create a group within "google groups" and moderate it. =A0It is > >"sponsored" by google-ads, which is nice. =A0No banners, no popups, and > >usually the ads are relevant to the content of the page being > >currently viewed. > > So because of the spam-floods from googlegroups that render much of > Usenet a less than happy experience for many users, one should move to > googlegroups and put eyeballs on their sponsored advertisements? How > nice of them to provide such a service... No, I am talking about creating a set of forums on a privately owned server that has nothing whatsoever to do with any of the FPGA companies. I own a small company in California. We do use FPGA's among other things. I used to participate on this list actively probably 8 or 9 years ago and benefited greatly from both my participation and learning from others. Mostly lurking for the last few years. It's a shame to see CAF and other valuable usenet lists get clobbered with viagra and other crap. My intent would be to create a nice clean and professional environment that would be just as useful, if not more due to newer technologies, than the usenet lists but devoid of trash. Yes, the manufacturer-owned lists do exist...but they are manufacturer owned. I would aggregate a number of usenet lists into one service: fpga, embedded, robotics, design are just a few that come to mind. Each one would get its own area but one sign-up would provide entry into all. I am more than ready to put money on the table and human resources to make it happen. The google-hosted lists are pretty bland and lack sophistication. -MartinArticle: 148126
On Fri, 18 Jun 2010 07:43:04 -0700 (PDT) Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com> wrote: > Hi, >=20 > I am trying to use this FIFO design in a Spartan6: > http://www.asic-world.com/examples/verilog/asyn_fifo.html >=20 > Doing so makes Xst emit a shrill warning (Xst:3002) because a latch > construct does not play well with the Spartan6 architecture, as it has > both an asynchronous set and reset. And as the warning says, the > circuit is still built but results in poor timing. >=20 > The construct in question is: > always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous > Clear & Preset. > if (Rst_Status | Clear_in) > Status =3D 0; //Going 'Empty'. > else if (Set_Status) > Status =3D 1; //Going 'Full'. >=20 > To fix the warning and improve timing, I have replaced it with: > wire Clear_Status =3D Rst_Status | Clear_in; > always @(posedge Clear_Status, posedge Set_Status) > if (Clear_Status) > Status <=3D 1'b0; > else > Status <=3D 1'b1; >=20 > Would this design still work without metastability problems? >=20 > I guess the answer to this question is probably in the article > "Asynchronous FIFO in Virtex-II FPGAs" by Peter Alfke, but I cannot > find it anywhere for download. >=20 > Thanks, > S=C3=A9bastien > PS. I do not want to use CORE Generator FIFOs. I played with this code a while ago, and had the same trouble. Additionally, I was never able to convince myself that the design(s) were in fact without timing problems. This was some concern, as the decoupling of processor clock from I/O system clocks were dependant on getting working async FIFOs. After a while I started manually instantiating FIFO(36|36_72) blocks instead, as they have the async capability built-in. I even wrote some wrappers to make this instantiation slightly nicer, and in particular, to make them wider then 72 bits when necessary. For me this works just fine, and I haven't had a problem with FIFOs since.=20 When you say you do not want to use CORE generator FIFO's, do you mean you want to avoid using the hard BRAM-based FIFO's, or do you want to avoid CORE Generator?=20 //Oscar=20Article: 148127
On 6/22/2010 2:24 AM, Brian Drummond wrote: > On Mon, 21 Jun 2010 18:24:48 -0700, Rob Gaddi<rgaddi@technologyhighland.com> > wrote: > >>> Basically, you are using a source synchronous output clock to your >>> flip-flop. There is no constraint to my knowledge that would do >>> the job you're looking for which is to define the relative timing >>> on two outputs. This should be correct by design. i.e. if you >>> push both CLK and Q outputs into IOB flops, using DDR flops if >>> necessary for the clock, you should have essentially zero timing >>> difference between CLK and Q if they are switching on the same >>> edge of the same global clock. Make your Tsu and Th based on >>> the relative timing to the IOB flops, for example making CLK >>> go high on the falling edge of the internal clock and changing >>> Q on the next rising edge to get 1/2 cycle of hold time. >>> >>> HTH, >>> Gabor >> >> I was afraid that was the answer. Unfortunately I'm running into a >> miserable time of things with that answer. I've got 16 pins being >> driven from identical signals (the SCLK for 16 simultaneous ADCs). I'm >> turning on a few optimizations in the MAP stage in order to try to get >> some of the resource count down, including equivalent_register_removal. > > You should be able to attach an "equivalent-register-removal=no" attribute to > the specific signal in VHDL source, and it should override the global setting > (tools issues apart; i haven't tried on S6). > > I don't know if UCF would work - I put it in the source to prevent synthesis > being too clever... > > But the documentation doesn't exactly make it obvious that you can override the > (useful) global setting... > >> And turning off equivalent_register_removal locally in the >> entity under question doesn't work, because the tools just flat out >> ignore me. This is, of course, all under ISE 11.5. Under version 12.1 >> the synthesis builds to take 10% more LUTs, making the design even more >> unplaceabler. > > Try it on the signal... > > unfortunately you probably can't go back to ISE10, where it works... > > - Brian > Alas, no such luck. Tried putting it on the signal in the VHDL, MAP went along and happily disregarded it come optimization time. Next step was to turn on KEEP_HIERARCHY on the affected entities in the UCF. MAP doesn't like that either, and forces me to to turn on the undocumented XIL_MAP_KEEP_KH_ON_TERMINAL_BLOCKS environment variable in order to even attempt to build the design. Having done that, MAP again disregards me, merges the signals, and then complains that it can't fit the merged signals into IOBs. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148128
On Jun 22, 8:17=A0pm, martin_05 <martin...@rocketmail.com> wrote: > ... > No, I am talking about creating a set of forums on a privately owned > server that has nothing whatsoever to do with any of the FPGA > companies. and... who should be such private owner ? > ... > It's a shame to see CAF and other valuable usenet lists get clobbered > with viagra and other crap. I agree... but that happen because CAF is not a moderated group! Why? because was created not moderated! > My intent would be to create a nice clean > and professional environment that would be just as useful, if not more > due to newer technologies, than the usenet lists but devoid of trash. > Yes, the manufacturer-owned lists do exist...but they are manufacturer > owned. > > I would aggregate a number of usenet lists into one service: =A0fpga, > embedded, robotics, design are just a few that come to mind. =A0Each one > would get its own area but one sign-up would provide entry into all. > I am more than ready to put money on the table and human resources to > make it happen. =A0The google-hosted lists are pretty bland and lack > sophistication. > > -Martin I would avoid reinventing the wheel... If you like, try to create a new moderated usenet group and pray to move people involved in CAF in the new moderated group... but I think is not so easy (moving people I mean) The same google didn't reinvent the wheel ( not for their google groups at least ;-) ) their google group is little more than an interface to access usenet... RegardsArticle: 148129
On Tue, 22 Jun 2010 11:17:31 -0700 (PDT), martin_05 <martin_05@rocketmail.com> wrote: >> >you can create a group within "google groups" and moderate it. It is >> >"sponsored" by google-ads, which is nice. No banners, no popups, and >> >usually the ads are relevant to the content of the page being >> >currently viewed. >> >> So because of the spam-floods from googlegroups that render much of >> Usenet a less than happy experience for many users, one should move to >> googlegroups and put eyeballs on their sponsored advertisements? How >> nice of them to provide such a service... > >No, I am talking about creating a set of forums on a privately owned >server that has nothing whatsoever to do with any of the FPGA >companies. Roger that. Replying to the suggestion to move to GoogleGroups. >It's a shame to see CAF and other valuable usenet lists get clobbered >with viagra and other crap. My intent would be to create a nice clean >and professional environment that would be just as useful, if not more >due to newer technologies, than the usenet lists but devoid of trash. Take a look at http://www.embeddedrelated.com/index.php, which gateways comp.arch.embedded to and from a web forum, for some ideas. There is minimal spam so I'd guess that their moderators or their upstream feed does do some housekeeping. The advantage is that it still has Usenet visibility, both ways. -- Rich Webb Norfolk, VAArticle: 148130
There are now new user manuals and schematics for Polmaddie1, Polmaddie2 and Polmaddie3 boards. Polmaddie4 and Polmaddie5 to follow shortly. Jump page to all of these boards http://www.enterpoint.co.uk/polmaddie/polmaddie_family.html. John Adair Enterpoint Ltd.Article: 148131
"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:1f9483a3-5eab-4a11-9ca4-9d5ab9b49cbb@x21g2000yqa.googlegroups.com... I have seen the same and it is just the result of faulty data. I had flagged this earlier and thought that it was being fixed, but it appears to have fallen through the cracks somewhere. > We all remember the Excalibar non-starter. "That was an Altera product line (NIOS, MIPS, ARM processor+FPGA), not a Xilinx one." Hi Ed, Although it was the competition's announced but missed product, I think it is worth learning the lessons from others, not necessarily having to experience it yourself and learning the hard way. A & X have great products (as well as the other market players), but the announcements of having future ones in the next smallest node (65, 40, 28nm) is like a downward spiral, kind of war of who is announcing the biggest, faster devices, with more and faster interfaces, but at the end if we engineers are not able to use those beasts due to bad tool support, or errata, or simply no silicon available, then all that blah, blah is simply useless. Regards, Jaime ArangurenArticle: 148132
On Jun 21, 2:45=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: *snip* > Right now I'm working on two S6 projects, both of which are absolute > disasters due to problems with the toolchain. =A0My DRAM problem from a > month ago, Xilinx ultimately told me was my problem and they washed > their hands of it. Anyone else notice that they seem to have dropped the memory controller block (MCB) from the X7 product lineup? Not a great vote of confidence for the current Spartan-6 implementation. cheers, aaronArticle: 148133
On Jun 21, 9:24=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On 6/18/2010 11:25 AM, Gabor wrote: > > > > > > > On Jun 18, 1:27 pm, Rob Gaddi<rga...@technologyhighland.com> =A0wrote: > >> I'm no luck figuring out how to implement the timing constraints for > >> something that, to my mind, ought to be pretty simple. =A0I'm connecte= d to > >> an external synchronous logic chip. =A0For now let's call it a regular > >> 74HC74 flip flop, but the details are unimportant. =A0My FPGA outputs = D > >> and CLK to the 74HC74, and reads back Q. > > >> The FPGA has a single global clock net, call it SysClk. =A0I've got a > >> state machine running on SysClk generating both data and clock for thi= s > >> widget; the clock is running at a sufficiently low rate that it's bein= g > >> generated by a simple, rising-edge only, divide-by-N from my master > >> clock. =A0My logic defines both D and CLK in a way that they're regist= ered > >> outputs and Q as a registered input with no logic; such that all of th= em > >> should be able to be pushed into the IOBs. > > >> The 74HC74 datasheet tells me that I've got setup time (Ts), hold time > >> (Th), and clock-to-output delay (Tcko). =A0How do I go about communica= ting > >> these requirements to the Xilinx toolchain? =A0Clearly it's some > >> combination of OFFSET constraints, but what are the magic words? > > >> UG612 discusses the use of the REFERENCE_PIN qualifier to indicate tha= t > >> the output data is referred to the output clock, but the example doesn= 't > >> give any advice that would connect those OFFSET constraints to only > >> define the relationship between D and CLK, not the entire world and CL= K. > >> =A0 =A0And I can't seem to find any information whatsoever that would = let me > >> define the relationship between CLK and Q. > > >> I've gone through the Constraints Guide. =A0I've gone through UG612. = =A0I've > >> gone through Austin's 5 part series over on the Xilinx forums. =A0And = I'm > >> still lost. =A0Anyone have any revelations for me? > > >> -- > >> Rob Gaddi, Highland Technology > >> Email address is currently out of order > > > Basically, you are using a source synchronous output clock to your > > flip-flop. =A0There is no constraint to my knowledge that would do > > the job you're looking for which is to define the relative timing > > on two outputs. =A0This should be correct by design. =A0i.e. if you > > push both CLK and Q outputs into IOB flops, using DDR flops if > > necessary for the clock, you should have essentially zero timing > > difference between CLK and Q if they are switching on the same > > edge of the same global clock. =A0Make your Tsu and Th based on > > the relative timing to the IOB flops, for example making CLK > > go high on the falling edge of the internal clock and changing > > Q on the next rising edge to get 1/2 cycle of hold time. > > > HTH, > > Gabor > > I was afraid that was the answer. =A0Unfortunately I'm running into a > miserable time of things with that answer. =A0I've got 16 pins being > driven from identical signals (the SCLK for 16 simultaneous ADCs). =A0I'm > turning on a few optimizations in the MAP stage in order to try to get > some of the resource count down, including equivalent_register_removal. > =A0 Unfortunately, this means that my 16 SCLKs are being equivalented dow= n > to only one flip-flop, which then fails MAP because it can no longer > perform the IOB=3DFORCE. =A0Basically, the tool cleverly decides to optim= ize > down my logic without checking to see what constraints it's under. > > I went through the Spartan 6 HDL libraries, figuring I'd just give up on > pretty code and instantiate an OFD like I would have on a Spartan 3. =A0N= o > such luck; they've pulled it out of the library. =A0There's an ODDR, but > that claims to need both of the clocks connected to it. =A0There's an OFD > in the schematic library, but you can't reference it from VHDL. > > Turning off equivalent_register_removal doesn't work, because my design, > while only 80% full on LUTs, claims to have no place to place the rest > and fails. =A0And turning off equivalent_register_removal locally in the > entity under question doesn't work, because the tools just flat out > ignore me. =A0This is, of course, all under ISE 11.5. =A0Under version 12= .1 > the synthesis builds to take 10% more LUTs, making the design even more > unplaceabler. > > So many walls, so little time to beat my head against each one. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order If you have only a limited number of registers you want to prevent equivalent removal on, you can work around it by making them different (slightly) so they cannot be considered equivalent. For example, usually the behavior right after configuration is not very important, so I would make a shift register on my reset signal and use a different bit to reset each of the otherwise equivalent registers. regards, GaborArticle: 148134
On Jun 21, 9:24=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > I went through the Spartan 6 HDL libraries, figuring I'd just give up on > pretty code and instantiate an OFD like I would have on a Spartan 3. =A0N= o > such luck; they've pulled it out of the library. =A0There's an ODDR, but > that claims to need both of the clocks connected to it. =A0There's an OFD > in the schematic library, but you can't reference it from VHDL. > Normally, any of the primitives you see in the unisim library will be properly translated by map regardless of whether they are in the specific family libraries guide. Try using instantiated FD 's or FDxE 's with LOC constraints to put them into the IOBs ( disclaimer: haven't tried this with 12.x & S6, it has worked in older V4/V5 designs ) If you need to use the ODDR's, past families with two clock inputs on the DDR primitives have worked using a single global clock net - create a locally inverted clock signal in the HDL which then should be optimized into a local clock inversion in the IOB register structure. Or just use two global clocks. BrianArticle: 148135
On Jun 19, 6:00=A0pm, Randy Yates <ya...@ieee.org> wrote: > > However, we've observed that the block seems to be marginally > stable. At random, the clock output completely dies, usually > lasting somewhere between approximately 2 to 6 seconds. > How are you resetting the DCM ? Held in reset until well after the external clock oscillator is programmed and stable ? Watchdog type reset logic to make sure it actually locked at startup? > Looking at the input clock with a scope doesn't reveal any > particular problems. Have you looked at the internal-to-the-chip clock signal heading into the DCM by 'forwarding' it back out of the chip with an ODDRsomething output register? Other random thoughts: - VCCAUX Power supplies and the like are OK? - does a test design with just the clock generation & reset logic also randomly die? ( i.e. with all other I/O tied off to static levels ) - look at the input clock and DCM routing and placement in the FPGA editor- on the same side of chip, no wacky local routes in use? - old post about V2 DCM troubleshooting with Answer Record links but the V2 specific stuff probably doesn't apply: http://groups.google.com/group/comp.arch.fpga/msg/e469dd385fe2fcc7 BrianArticle: 148136
Hi, I am new to Altera Eclipse for quartus subscription 9.1 version. I want to learn NIOS programming. I go through the simpliest version on 'Getting Started' part in "Nios II Software Developer's Handbook". I create a project step by step according to the handbook (I have no NIOS II evaluation board at home). The project is created with 'Nios II Application and BSP from Template' option. In the end, I get the following message: ............... Unable to create project Reason: Failed to execute: ./create-this-app --no-make chmod: changing permissions of `.': Permission denied chmod: changing permissions of `./create-this-app': Permission denied .................... That is, it cannot generate an exec object file. Although I look through the handbook and Eclipse help, I still cannot know the reason. The book says 'create-this-app' is copied from an example. Does it mean computer automatically do that for me? Or, I copy that myself. I just want a 'Hellp world' message printf output. Which 'create-this- app' I should use? For a first time user, how to deal with 'create-this-app' ? Thanks for your help.Article: 148137
On Tue, 22 Jun 2010 13:59:46 -0700 (PDT), Aaron Holtzman <aholtzma@gmail.com> wrote: >On Jun 21, 2:45 pm, Rob Gaddi <rga...@technologyhighland.com> wrote: >*snip* >> Right now I'm working on two S6 projects, both of which are absolute >> disasters due to problems with the toolchain. My DRAM problem from a >> month ago, Xilinx ultimately told me was my problem and they washed >> their hands of it. > >Anyone else notice that they seem to have dropped the memory >controller block (MCB) from the X7 product lineup? Not a great vote of >confidence for the current Spartan-6 implementation. > We have a DDR2 ram interfaced to a S6/45. We can't get it to work. JohnArticle: 148138
On Jun 22, 1:19=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On 6/22/2010 2:24 AM, Brian Drummond wrote: > > > > > > > On Mon, 21 Jun 2010 18:24:48 -0700, Rob Gaddi<rga...@technologyhighland= .com> > > wrote: > > >>> Basically, you are using a source synchronous output clock to your > >>> flip-flop. =A0There is no constraint to my knowledge that would do > >>> the job you're looking for which is to define the relative timing > >>> on two outputs. =A0This should be correct by design. =A0i.e. if you > >>> push both CLK and Q outputs into IOB flops, using DDR flops if > >>> necessary for the clock, you should have essentially zero timing > >>> difference between CLK and Q if they are switching on the same > >>> edge of the same global clock. =A0Make your Tsu and Th based on > >>> the relative timing to the IOB flops, for example making CLK > >>> go high on the falling edge of the internal clock and changing > >>> Q on the next rising edge to get 1/2 cycle of hold time. > > >>> HTH, > >>> Gabor > > >> I was afraid that was the answer. =A0Unfortunately I'm running into a > >> miserable time of things with that answer. =A0I've got 16 pins being > >> driven from identical signals (the SCLK for 16 simultaneous ADCs). =A0= I'm > >> turning on a few optimizations in the MAP stage in order to try to get > >> some of the resource count down, including equivalent_register_removal= . > > > You should be able to attach an "equivalent-register-removal=3Dno" attr= ibute to > > the specific signal in VHDL source, and it should override the global s= etting > > (tools issues apart; i haven't tried on S6). > > > =A0 I don't know if UCF would work - I put it in the source to prevent = synthesis > > being too clever... > > > But the documentation doesn't exactly make it obvious that you can over= ride the > > (useful) global setting... > > >> And turning off equivalent_register_removal locally in the > >> entity under question doesn't work, because the tools just flat out > >> ignore me. =A0This is, of course, all under ISE 11.5. =A0Under version= 12.1 > >> the synthesis builds to take 10% more LUTs, making the design even mor= e > >> unplaceabler. > > > Try it on the signal... > > > unfortunately you probably can't go back to ISE10, where it works... > > > - Brian > > Alas, no such luck. =A0Tried putting it on the signal in the VHDL, MAP > went along and happily disregarded it come optimization time. > > Next step was to turn on KEEP_HIERARCHY on the affected entities in the > UCF. =A0MAP doesn't like that either, and forces me to to turn on the > undocumented XIL_MAP_KEEP_KH_ON_TERMINAL_BLOCKS environment variable in > order to even attempt to build the design. =A0Having done that, MAP again > disregards me, merges the signals, and then complains that it can't fit > the merged signals into IOBs. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order- Hide quoted text - > > - Show quoted text - I had a similar problem recently. Using the SAVE attribute prevented MAP from optimizing my logic away, even with increased effort level. You can look it up in the XST manual to see the details. Regards, SergioArticle: 148139
On 17 Giu, 15:11, "shoonya" <manish.paradkar@n_o_s_p_a_m.gmail.com> wrote: > Hi, > > I recently got the Actel Smartfusion eval kit. Since I use Linux, I am > running the windows Libero IDE under wine. > > While the application runs fine under wine, I am not able to program the > device with the Flashpro software. Seems like it is not able to talk to t= he > programmer. > > I know this is as much a wine issue, but i wanted to know if there is a > native software for linux which can be used to just program the device an= d > which supports smartfusion fpgas. > > And which can work on the free gold license. > > Thanks > Manish > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com You could try the 2 other ISP ways, DirectC and STAPL player. Both shoudl work under linux. http://www.actel.com/download/program_debug/directc/default.aspx http://www.actel.com/download/program_debug/stapl/default.aspx Regards, FabioArticle: 148140
F M <fmont67@gmail.com> wrote: > On 17 Giu, 15:11, "shoonya" <manish.paradkar@n_o_s_p_a_m.gmail.com> > wrote: > > Hi, > > > > I recently got the Actel Smartfusion eval kit. Since I use Linux, I am > > running the windows Libero IDE under wine. > > > > While the application runs fine under wine, I am not able to program the > > device with the Flashpro software. Seems like it is not able to talk > > to the programmer. > > > > I know this is as much a wine issue, but i wanted to know if there is a > > native software for linux which can be used to just program the > > device andwhich supports smartfusion fpgas. > > > > And which can work on the free gold license. > > > You could try the 2 other ISP ways, DirectC and STAPL player. Both > shoudl work under linux. > http://www.actel.com/download/program_debug/directc/default.aspx > http://www.actel.com/download/program_debug/stapl/default.aspx Are the BSDL 1532 programming algorithms available? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148141
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: ... > I understand your criticisms of the Spartan-6 production availability > over the last few months. If you check the distributor stocking > levels over the next 1-2 months you will see rapid improvement in this > area. Digikey now lists the full family, also as non-stock, with e.g. XC6SLX4-2TQG144C-NC expected August 4 at 8.12 Euro at 31 pieces. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148142
On 23 Giu, 11:19, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > F M <fmon...@gmail.com> wrote: > > On 17 Giu, 15:11, "shoonya" <manish.paradkar@n_o_s_p_a_m.gmail.com> > > wrote: > > > Hi, > > > > I recently got the Actel Smartfusion eval kit. Since I use Linux, I a= m > > > running the windows Libero IDE under wine. > > > > While the application runs fine under wine, I am not able to program = the > > > device with the Flashpro software. Seems like it is not able to talk > > > to the programmer. > > > > I know this is as much a wine issue, but i wanted to know if there is= a > > > native software for linux which can be used to just program the > > > =A0device andwhich supports smartfusion fpgas. > > > > And which can work on the free gold license. > > > You could try =A0the 2 other ISP ways, DirectC and STAPL player. Both > > shoudl work under linux. > > =A0 =A0http://www.actel.com/download/program_debug/directc/default.aspx > > =A0 =A0http://www.actel.com/download/program_debug/stapl/default.aspx > > Are the BSDL 1532 programming algorithms available? > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- The algo is inside the STAPL file, which is generated by Libero for Actel devices (under PROGRAMMING FILE button). Then should be available in linux also. What is needed in this case is a LINUX STAPL player. Actel in his site claims it is avaliable. I just had a look. In any case, being the STAPL player 'universal' (it doesn't know anything about device and algo, everithing is wrote in the STAPL file) you can take any available on the net; i.e. ACTEL STAPL player was derived from the ALTERA STAPL player, which released the sources under some open-soft license (big present for Actel). Pls note the I never tried this personally. ISP is a low priority of my working plan. Till now I just collected some info. I'll work on this subject as soon as I will be able to come out from the many problems I have to finish the design on A3PE3000. Cheers, FabioArticle: 148143
Hi all, I'm developping a firmware using Xilinx FPGA spartan3, I want to use an FPGA core which has the same functionality as altshift in Altera FPGA, I was thinking about using FIFO but I need to implement 4 taps. Anyone knows well about Altera and Xilinx could help me please? Thank you !!Article: 148144
Gladys <yuhui.b@gmail.com> wrote: > Hi all, > I'm developping a firmware using Xilinx FPGA spartan3, I want to use > an FPGA core which has the same functionality as altshift in Altera > FPGA, I was thinking about using FIFO but I need to implement 4 taps. > Anyone knows well about Altera and Xilinx could help me please? Thank > you !! What is "altshift"? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148145
On the Xilinx Spartan-3E Starter kit board there is an USB interface to program the FPGA chip via JTAG. However this part of the schematics is missing from the documentation: http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf I remember that someone actually did locate the connections around 2006/2007 and put the schematics online for that section. But I can't locate it. Someone knows where to find it ..? (The USB port is wired to the CY7C68013A-100AXC containing an 8051 cpu as the primary USB interface. I think it's connected to the XC2C64A-5VQ44C CPLD as well. I have seen the http://rmdir.de/~michael/xilinx/ page too)Article: 148146
On 23 juin, 13:33, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Gladys <yuhu...@gmail.com> wrote: > > Hi all, > > =A0I'm developping a firmware using Xilinx FPGA spartan3, I want to use > > an FPGA core which has the same functionality as altshift in Altera > > FPGA, I was thinking about using FIFO but =A0I need to implement 4 taps= . > > Anyone knows well about Altera and Xilinx could help me please? Thank > > you !! > > What is "altshift"? > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- altshift_taps: It's a megafuncthin provided by Altera FPGA, here is the user manual http://www.altera.com/literature/ug/ug_shift_register_ram_b= ased.pdf It's a RAM base shiftregister, actually I want to do image processing while receiving the real time pixel data, the image resolution is 1028H * 1024L and FPGA receives the data line by line, but I need a 5H x 5L real time image data so I want to know how could I realize it.Article: 148147
EvSpace <none@curr.com> wrote: > On the Xilinx Spartan-3E Starter kit board there is an USB interface to > program the FPGA chip via JTAG. However this part of the schematics is > missing from the documentation: > http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf > I remember that someone actually did locate the connections around 2006/2007 > and put the schematics online for that section. But I can't locate it. > Someone knows where to find it ..? There is some discussion (in german) on http://www.mikrocontroller.net/topic/142358#new -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 148148
I found that Xilinx provide an IP core called RAM-based Shift Register, the maximum depth is 1088, however, my image could have a high resolution of 3664 x 2748, which means I need a depth of 2748, is there any other methode to implement this? Thank youArticle: 148149
On Jun 23, 6:52=A0am, EvSpace <n...@curr.com> wrote: > On the Xilinx Spartan-3E Starter kit board there is an USB interface to > program the FPGA chip via JTAG. However this part of the schematics is > missing from the documentation:http://www.xilinx.com/support/documentatio= n/boards_and_kits/ug230.pdf > > I remember that someone actually did locate the connections around 2006/2= 007 > and put the schematics online for that section. But I can't locate it. > Someone knows where to find it ..? > > (The USB port is wired to the CY7C68013A-100AXC containing an 8051 cpu as > the primary USB interface. I think it's connected to the XC2C64A-5VQ44C > CPLD as well. I have seen thehttp://rmdir.de/~michael/xilinx/page too) Look at the schematics for the SP605 development board. They include the USB JTAG pages of the schematics, as do a few of the other newer development boards. Regards, John McCaskill www.FasterTechnology.com
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