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On Jan 3, 9:08=A0am, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > On 29 Dez. 2010, 17:32, Dave <starfire...@cableone.net> wrote: > > > In addition to the responses you've had so far, don't you need to > > include the port for the reset line input and also include it in your > > process sensitivity list? > > No as this seems to be a synchronous reset which is internal > generated. You might want to take another look. The OP coded an asynchronous reset but forgot to include the reset signal in the sensitivity list. KJArticle: 150226
On Jan 3, 9:45=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > > -- =A0No feasible entries for infix operator "+". Type error resolving > > infix expression "+" as type ieee.std_logic_1164.std_logic_vector. > > Lots of potential issues with this code, but try: > count <=3D count + "1"; -- now with quotes on the 1 > You might want to try your suggestion first, you'll get the exact same error message. You might also want to read my first post which has the solution. KJArticle: 150227
On Dec 30 2010, 7:56=A0am, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Hi, > I am designing a very simple cw keyer, and I am wondering why some > timings in reset signal is triggering timing violations. > The reason is most likely because the timing paths are not exactly the same. > My problem is that apparently symmetrical FSMs get warnings on one > instance while the other not. > But it is likely that they have different delays. > I got timing violations when reset duration is, for example 60ns or > 100ns in the testbench: > 60 or 100ns are exactly on the raising edge of the feeded fx2_clk (40ns > =A0 period). > > I got these warnings: > > WARNING:Simulator:29 - at 63.358 ns: Warning: Timing violation in > =A0 =A0 /test002/uut/dashstate_FSM_FFd1/ =A0$recrem<recovery>( RST:62.893= ns, > =A0 =A0 CLK:63.358 ns,991.000 ps) > > WARNING:Simulator:29 - at 63.370 ns: Warning: Timing violation in > =A0 =A0 /test002/uut/morsestate_FSM_FFd1/ =A0$recrem<recovery>( RST:62.95= 8 ns, > =A0 =A0 CLK:63.370 ns,991.000 ps) > > My question is: why I got the warning on dashstate and not on dotstate? Most likely because the path delay from the reset pin to the 'dotstate' process is not the same as it is to the other processes and just happens to not trigger a timing violation under the conditions being simulated. Take a look at the paths from the reset and clock pins to all of the loads. What you'll likely find is that the reset paths are different delays. > They are debouncers for the dot and dash paddle inputs and they are > identical. > Identical source code...not identical implementations, the routing delay will be different since they must be physically in different locations in the routed design. > I have similar problems on another FSM: > ... I would imagine so if you're not handling resets properly. > > The other question is: how is supposed async reset to be properly > handled? Should I ignore the warnings? > The short answer is no should not ignore this warning. The reason is that you are not properly handling a signal that is entering a clock domain. The longer answer is that since you're only reporting a problem with your reset signal, it is likely that you could get your design to work simply because the reset signal likely does not occur very often which could then lead you into believing that your design is correct. In fact, it is not. If you reset it often enough over the full temp/ voltage range of the part you would find that it does not always work. I'm assuming here that your reset signal is an input to your design and is not synchronized to your clock. Before using that signal anywhere in your design you must first properly synchronize that signal by bringing it into the input of exactly one flip flop. The output of that flip flop is potentially metastable for a short period of time so typically one would take the output of that flop and send it into a second flip flop. The output of that second flip flop would then be distributed throughout your design. You would also do well to perform static timing analysis. I'm guessing that you might be one who thinks that running a timing simulation proves that timing is correct. It doesn't. Only static timing analysis is capable of showing that timing is correct. Kevin JenningsArticle: 150228
Hello, I need to implement a measurement instrument in FPGA, where direct placement of several simple blocks (eg. DFFs) must be achieved. So I created an EDIF netlist, describing one subcircuit, and the rest (top level entity) coded in VHDL. The target architecture is Actel ProASIC3E, development suite Libero 9 & Synplify. The VHDL part has been synthesised using Synplify, producing well- looking EDIF. Then, I tried to compile (and I hoped then to P&R) the two .edn files using Actel Designer. However, here comes the failure. The "inner" subcircuit has not been wired together with the top entity, compiler returns error about unconnected inputs/outputs and when I look into structural VHDL output from the compiler, the inner entity is listed in, but with *empty* implementation. (I tried both GUI as well as commandline+Tcl Designer invocation, same results.) I listed the top level entity .edn as the last (ie. the second) in the list, as mentioned in instructions. Then, I created another project, entered random dummy VHDL entity with same i/o signals as the EDIF one mentioned above and synthesised by Synplify. I have tried the resulting .edn in place of the former one, same result. Please, do you have any EDIF example, which is working together with a VHDL or Verilog together in Actel tools? Or do you know, what am I doing wrong? Many thanks. Greetings, MarekArticle: 150229
On Dec 30 2010, 7:56=A0am, Giuseppe Marullo <giuseppe.marullonos...@iname.com> wrote: > Hi, > I am designing a very simple cw keyer, and I am wondering why some > timings in reset signal is triggering timing violations. > > My problem is that apparently symmetrical FSMs get warnings on one > instance while the other not. > > I got timing violations when reset duration is, for example 60ns or > 100ns in the testbench: > > ... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 // Initialize Inputs > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fx2_clk =3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 paddledot <=3D 1'b1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 paddledash =3D 1'b1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 resetpin =3D 1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 // Wait 100 ns for global reset to finish > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 #60; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 resetpin =3D 0; > > 60 or 100ns are exactly on the raising edge of the feeded fx2_clk (40ns > =A0 period). > > I got these warnings: > > WARNING:Simulator:29 - at 63.358 ns: Warning: Timing violation in > =A0 =A0 /test002/uut/dashstate_FSM_FFd1/ =A0$recrem<recovery>( RST:62.893= ns, > =A0 =A0 CLK:63.358 ns,991.000 ps) > > WARNING:Simulator:29 - at 63.370 ns: Warning: Timing violation in > =A0 =A0 /test002/uut/morsestate_FSM_FFd1/ =A0$recrem<recovery>( RST:62.95= 8 ns, > =A0 =A0 CLK:63.370 ns,991.000 ps) > > My question is: why I got the warning on dashstate and not on dotstate? > They are debouncers for the dot and dash paddle inputs and they are > identical. ...snip... I assume you are running a post-layout simulation which uses special models for the actual components in the FPGA and checks setup and hold times on FFs. This is a poor way to verify logic and an even poorer way to verify timing. As KJ said, you should be checking timing using static timing analysis. Your error is coming from the fact that your reset is going away on the active edge of the clock. There are two ways this will mess up your design. One is that the prop delays to various FFs is different so that the reset will be released on different FFs on different clock cycles possibly putting your FSMs and other logic into invalid states. The other is that a FF can go metastable and disrupt other logic following it also putting things into invalid states. I try to design my logic so it will not be disturbed by a poorly timed async reset. RickArticle: 150230
At least I can do addition of std_logic_vectors with no special settings in
Quartus 10.
But for integers, you need the numeric library.
The code below is some tested and implemented code I found on my drive.
-------------
architecture rtl of test is
signal testcnt : std_logic_vector(29 downto 0);
constant testval : std_logic_vector(29 downto
0):=(testcnt'high=>'1',0=>'1',others =>'0');
begin
process(clk,rst) begin
if(rising_edge(clk)) then
test<='0';
testcnt<=testcnt+"1";
if(rst='1' or testcnt>testval) then
testcnt<=(others=>'0');
test<='1';
end if;
end if;
end process;
end rtl;
"KJ" <kkjennings@sbcglobal.net> wrote in message
news:24672c6f-e84e-4475-b5c1-eb3835883b5a@j25g2000vbs.googlegroups.com...
On Jan 3, 9:45 am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
> > -- No feasible entries for infix operator "+". Type error resolving
> > infix expression "+" as type ieee.std_logic_1164.std_logic_vector.
>
> Lots of potential issues with this code, but try:
> count <= count + "1"; -- now with quotes on the 1
>
You might want to try your suggestion first, you'll get the exact same
error message. You might also want to read my first post which has
the solution.
KJ
Article: 150231"KJ" <kkjennings@sbcglobal.net> wrote in message news:16d20dfa-e437-44ce-992a-7fce6b4d4bc5@l8g2000yqh.googlegroups.com... On Dec 29, 10:43 am, Santosh <santos...@gmail.com> wrote: > I have got a clock divider code as follows: > architecture Behavioral of divClk8 is > signal count : std_logic_vector (3 downto 0) := "1111"; > signal reset : std_logic := '0'; > > begin > process(CLK) > begin > if(reset = '1') then > count <= "0000"; > elsif(rising_edge(CLK)) then > count <= count + 1; > > But when I try to compile it using ModelSim I get the following error > > -- No feasible entries for infix operator "+". Type error resolving > infix expression "+" as type ieee.std_logic_1164.std_logic_vector. > > >std_logic_vector signals do not have any math operators defined for >them. A std_logic_vector is just a collection of bits with no numeric >interpretation. To do what you want, you need to use a signal of type >unsigned which is defined in the package 'ieee.numeric_std'. To fix >up the code: > >- Add the line "use ieee.numeric_std.all" right after the line where >you currently have "library ieee" >- Change "signal count : std_logic_vector (3 downto 0)" to "signal >count : unsigned (3 downto 0)" > >Kevin Jennings Alternatively use VHDL2008's numeric_std_unsigned which is a replacement for the none standard std_logic_unsigned. You can now do unsigned arithmetic (like + 1) on std_logic_vectors without conversions. There is also a numeric_std_signed but Modelsim 10.0 doesn't seem to support it, Hans www.ht-lab.comArticle: 150232
he wrote:
> On 01/01/11 19:26, luudee wrote:
>> It seems this issue is coming up again and again, with each new ISE
>> release.
>>
>> I am running Fedora 14, x86_64, and installed ISE 12.4.
>>
>> And of course the platform USB cables stopped working ...
>>
>> libusb is installed, and the drivers are installed ....
>>
>> but impact is giving me this:
>> ........
>> AutoDetecting cable. Please wait.
>> If you are using the Platform Cable USB, please refer to the USB Cable
>> Installation Guide (UG344) to install the libusb package.
>> Connecting to cable (Usb Port - USB21).
>> Checking cable driver.
>> Linux release = 2.6.36.2.RU1.
>> WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the
>> cable
>> drivers. See Answer Record 22648.
>> Cable connection failed.
>> Connecting to cable (Parallel Port - parport0).
>> Linux release = 2.6.36.2.RU1.
>> WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the
>> cable
>> drivers. See Answer Record 22648.
>> Linux release = 2.6.36.2.RU1.
>> WARNING:iMPACT - Module parport_pc is not loaded. Please reinstall
>> the cable
>> drivers. See Answer Record 22648.
>> Cable connection failed.
>
> does fxload load the firmware? check lsusb for Product-ID 0008. The
> "tempnode" string in the udev-rules is case sensitive. Can't remember if
> upper or lower case is correct, but I had to change it once.
>
> Do you have the symlink /usr/lib/libusb.so -> /usr/lib/libusb-[Version].so
> This link was not created by default in my distribution and caused
> problems in previous releases(don't know about fedora)
>
> HTH
Update: ISE_DS 12.4 now searches for libusb.so in /usr/lib64 instead of
/usr/lib on 64bit machines.
-> Create a symlink /usr/lib64/libusb.so ->
/usr/lib64/libusb-[version].so and 12.4 detects the cable:
Release 12.4 - iMPACT M.81d (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Preference Table
Name Setting
StartupClock Auto_Correction
AutoSignature False
KeepSVF False
ConcurrentMode False
UseHighz False
ConfigOnFailure Stop
UserLevel Novice
MessageLevel Detailed
svfUseTime false
SpiByteSwap Auto_Correction
AutoInfer false
SvfPlayDisplayComments false
>>AutoDetecting cable. Please wait.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /opt/Xilinx/12.4/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030.
File version of /usr/share/xusbdfwu.hex = 1030.
Using libusb.
Kernel release = 2.6.18-194.26.1.el5.
Max current requested during enumeration is 74 mA.
Type = 0x0004.
Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1028.
File version of /opt/Xilinx/12.4/ISE_DS/ISE/data/xusb_xlp.hex = 1303.
Firmware hex file version = 1303.
Downloading /opt/Xilinx/12.4/ISE_DS/ISE/data/xusb_xlp.hex.
Downloaded firmware version = 1303.
PLD file version = 0012h.
PLD version = 0012h.
Type = 0x0004.
ESN option: 000013C1E1DF01.
>Identifying chain contents...'0': : Manufacturer's ID = Xilinx
xc6vlx240t, Version : 2
INFO:iMPACT:1777 -
Reading /opt/Xilinx/12.4/ISE_DS/ISE/virtex6/data/xc6vlx240t.bsd...
INFO:iMPACT:501 - '1': Added Device xc6vlx240t successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
INFO:iMPACT:1777 -
Reading /opt/Xilinx/12.4/ISE_DS/ISE/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
Elapsed time = 1 sec.
Elapsed time = 0 sec.
>----------------------------------------------------------------------
----------------------------------------------------------------------
Article: 150233Hello Marek, There are some challenges in merging EDIF netlists with Designer upon import. I would let Synplify do the merging for you. Just have your netlist in VHDL format and add it as an other source file. You can use the edn2vhdl tool to create the VHDL netlist. Regards, Daniel Leu Inicore Inc. On Jan 3, 10:14=A0am, robotron <hefais...@gmail.com> wrote: > Hello, > > I need to implement a measurement instrument in FPGA, where direct > placement of several simple blocks (eg. DFFs) must be achieved. So I > created an EDIF netlist, describing one subcircuit, and the rest (top > level entity) coded in VHDL. The target architecture is Actel > ProASIC3E, development suite Libero 9 & Synplify. > > The VHDL part has been synthesised using Synplify, producing well- > looking EDIF. Then, I tried to compile (and I hoped then to P&R) the > two .edn files using Actel Designer. However, here comes the failure. > The "inner" subcircuit has not been wired together with the top > entity, compiler returns error about unconnected inputs/outputs and > when I look into structural VHDL output from the compiler, the inner > entity is listed in, but with *empty* implementation. (I tried both > GUI as well as commandline+Tcl Designer invocation, same results.) I > listed the top level entity .edn as the last (ie. the second) in the > list, as mentioned in instructions. > > Then, I created another project, entered random dummy VHDL entity with > same i/o signals as the EDIF one mentioned above and synthesised by > Synplify. I have tried the resulting .edn in place of the former one, > same result. > > Please, do you have any EDIF example, which is working together with a > VHDL or Verilog together in Actel tools? Or do you know, what am I > doing wrong? Many thanks. > > Greetings, > MarekArticle: 150234
Hello, Daniel,
> There are some challenges in merging EDIF netlists with Designer upon
> import. I would let Synplify do the merging for you. Just have your
> netlist in VHDL format and add it as an other source file. You can use
> the edn2vhdl tool to create the VHDL netlist.
thank you for your answer. This is the problem: I need to bypass
synthesis step, since I am afraid, that some evil optimization could
damage my design. Even if it would work one, I have no guarantee, that
in next Synplify release it will result in exactly the same output
netlist.
However, I have been told the solution by Actel technical support, so
I am forwarding the reply:
-----
>From Sagar.Gosavi@microsemi.com Tue Jan 4 10:51:54 2011
Date: Tue, 4 Jan 2011 15:21:54 +0530
From: "Gosavi, Sagar" <Sagar.Gosavi@microsemi.com>
To: Marek Peca
Subject: RE: Actel Designer: how to compile VHDL top & EDIF submodule
together?:
489394-344304373
Hi Marek,
Thanks for contacting Actel Tech Support.
Can you please send me the design files for this project so that I
can understand the scenario better?
Between, if I understand the situation; are you observing some errors
like:
Error: CMP002: Net: CNT_16[0] is not driven
Error: CMP002: Net: CNT_16[1] is not driven
Error: CMP002: Net: CNT_16[2] is not driven
Error: CMP002: Net: CNT_16[3] is not driven
Also, if you find syn_black_box in your top level edn, kindly replace
it with the instance name of your subcircuit edn.
Note: The library name, cell name and the view name of the lower
level cell/edn has to match in its instantiation in the upper (in
this case, the top level) level
If above solution doesn't help, please send me your Project, so that
I can debug this issue better.
Have a great day ahead!
Thanks and Regards,
Sagar Gosavi
-----
So I have changed the library name to "work" and view name to
"syn_black_box" and now it works as expected, the Designer now
produces reasonably looking composite netlist. The EDIF excerpt looks
like:
(library work
(edifLevel 0)
(technology (numberDefinition))
(cell my_strange_circuit
(cellType GENERIC)
(view syn_black_box (viewType NETLIST)
...etc.
Greetings,
Marek
Article: 150235
On Jan 3, 7:14=A0pm, robotron <hefais...@gmail.com> wrote:
> Hello,
..
Time ago I had the same problem with Synplify and VHDL.
My first suggestion is to try with Mentor Precision compiler, recently
distributed with the actel suite.
Never tried but could be the painless solution.
If you want continue to work with vhdl+Symplify, follow the suggestion
from Daniel.
Symplify is able to make magic things also when you mix edif with vhdl/
verilog.
In my case I switched to Verilog+Symplify and everything went fine.
Some more details about this.
If I understood correctly from your post, the verilog version of what
you try to do should be something like the followings.
////// FILE: top.v
`timescale 1 ns/100 ps
module sub_mod_v (CLK,Q,D) /* synthesis syn_black_box */;
output Q;
input CLK;
input D;
endmodule
module top(Q_1, Q_0, CLK, D);
output Q_1;
output Q_0;
input CLK;
input D;
sub_mod_v sub_mod_v_0 (.CLK(CLK), .Q(Q_0), .D(D));
sub_mod_v sub_mod_v_1 (.CLK(CLK), .Q(Q_1), .D(D));
endmodule
////// FILE: sub_mod.v
`timescale 1 ns/100 ps
module sub_mod_v(CLK, Q, D);
input CLK;
output Q;
input D;
DFN1 DFN1_0 (.D(D), .CLK(CLK), .Q(Q));
endmodule
With Symplify,
* compile sub_mod.v after having disabled IO insertion. You get:
"sub_mod.edn"
and separately
* compile top.v . You get: "top.edn"
Then execute Designer and import the two .edn files with "top.edn"
at the end.
You should get a successful designer compiling (just tried).
Last suggestion if you want stay with VHDL (not recommended but it
works).
You can edit the edif TOP file and correct the 'mistake'. It is
related to how Symplify treat VHDL black box. To let you to begin, if
interested, here some tip.
/0/ Look inside top edif file looking for all lines like:
..
(instance sub_mod_0 (viewRef syn_black_box (cellRef sub_mod))
..
and modify them as in the following example
..
(instance sub_mod_0 (viewRef def_arch (cellRef sub_mod (libraryRef
work)))
..
Be sure that:
/1/ no other definition of 'sub_mod' exists inside TOP edif file. In
the case remove it.
/2/ 'libraryRef' names are the same in both EDIF files (here it is
'work')
/3/ 'viewRef' names are the same in both EDIF files (here it is
'def_arch').
Hope this help.
Fabio
Article: 150236Hi everyone, I've got a question. Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz clock. The clocks are in phase, i.e. a rising edge on the 100 MHz occurs at the same time as a rising edge 200 MHz clock. . In my application I want to process the data @ 200 MHz to reduce filter complexity, i.e. my filters would use only half of the multipliers compared to running the filters @ 100 MHz. However, the effective sampling rate would remain the same i.e. 100 MHz. I need to obtain a data valid signal enabled 50% of the time, since there would be a new data 1 cycle out of 2 on the 200 MHz clock. I could use an asynchronous FIFO to get the data valid @ 200 MHz, but I think this solution is overkill since both clocks are in phase-lock. What would you do? I want the data valid to be enabled 50% of the time, and I want the data_valid to be '1' when my 16 bits data sample change. Best regards BenjaminArticle: 150237
Benjamin Couillard <benjamin.couillard@gmail.com> wrote: >Hi everyone, I've got a question. > >Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz >clock. The clocks are in phase, i.e. a rising edge on the 100 MHz >occurs at the same time as a rising edge 200 MHz clock. > >. In my application I want to process the data @ 200 MHz to reduce >filter complexity, i.e. my filters would use only half of the >multipliers compared to running the filters @ 100 MHz. However, the >effective sampling rate would remain the same i.e. 100 MHz. I need to >obtain a data valid signal enabled 50% of the time, since there would >be a new data 1 cycle out of 2 on the 200 MHz clock. > >I could use an asynchronous FIFO to get the data valid @ 200 MHz, but >I think this solution is overkill since both clocks are in phase-lock. > >What would you do? I want the data valid to be enabled 50% of the >time, and I want the data_valid to be '1' when my 16 bits data sample >change. I'd use a timing constrain. If the tools know about the clocks coming from inside the FPGA the tools might create the timing constraints automatically based on the input clock. I know the XIlinx tools create such contraints automatically. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150238
On Jan 4, 3:42=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > >Hi everyone, I've got a question. > > >Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz > >clock. The clocks are in phase, i.e. a rising edge on the 100 MHz > >occurs at the same time as a rising edge 200 MHz clock. > > >. In my application I =A0want to process the data @ 200 MHz to reduce > >filter complexity, i.e. my filters would use only half of the > >multipliers compared to running the filters @ 100 MHz. However, the > >effective sampling rate would remain the same i.e. 100 MHz. =A0I need to > >obtain a data valid signal enabled 50% of the time, since there would > >be a new data 1 cycle out of 2 on the 200 MHz clock. > > >I could use an asynchronous FIFO to get the data valid @ 200 MHz, but > >I think this solution is overkill since both clocks are in phase-lock. > > >What would you do? I want the data valid to be enabled 50% of the > >time, and I want the data_valid to be '1' when my 16 bits data sample > >change. > > I'd use a timing constrain. If the tools know about the clocks coming > from inside the FPGA the tools might create the timing constraints > automatically based on the input clock. I know the XIlinx tools create > such contraints automatically. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > -------------------------------------------------------------- The first thing I tried is this DATA_VAL_200M <=3D DATA_VAL_100M and CLK_100M. Then I use this signal as a data_valid signal for my filter core running @ 200 MHz but with a sample rate of 100 MHz. It seems to work fine in synthesis i.e. Xilinx doesn't complain and does not output a warming, however in simulation I get some "glitches", basically I sometimes see a small red line at transitions. I think this is related to "delta cycles" in VHDL but I could be mistaken. Does anyone have a (better) solution?Article: 150239
On 1/4/2011 12:34 PM, Benjamin Couillard wrote: > Hi everyone, I've got a question. > > Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz > clock. The clocks are in phase, i.e. a rising edge on the 100 MHz > occurs at the same time as a rising edge 200 MHz clock. > > . In my application I want to process the data @ 200 MHz to reduce > filter complexity, i.e. my filters would use only half of the > multipliers compared to running the filters @ 100 MHz. However, the > effective sampling rate would remain the same i.e. 100 MHz. I need to > obtain a data valid signal enabled 50% of the time, since there would > be a new data 1 cycle out of 2 on the 200 MHz clock. > > I could use an asynchronous FIFO to get the data valid @ 200 MHz, but > I think this solution is overkill since both clocks are in phase-lock. > > What would you do? I want the data valid to be enabled 50% of the > time, and I want the data_valid to be '1' when my 16 bits data sample > change. > > > Best regards > > Benjamin Put a T flop on the 100 MHz clock. Now you've got a 50 MHz square wave, changing state every time you get a 100 MHz rising edge. Reregister that to the rising edge of the 200 MHz clock, now you've got a 50 MHz square wave changing state on every falling edge of the 100 MHz clock. XOR that with the previous value and reregister on the rising edge of the 200 MHz clock, now you've got a 100 MHz signal that the tools recognize as being on the 200 MHz clock domain that tells you which phase of the 100 MHz clock you're in. Distribute as needed. Or something like that. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 150240
OK, data is valid on the rising edge of 100M, right? Is it still valid (same data) on the falling edge too? If so, it really does not matter which edge of 100M you sample the data into your 200M domain does it? You just need to make sure you don't sample the same 100M data twice in 200M domain. Just set up a 200M signal that toggles every 200M clock. Use that as data valid. It does not matter which edge of 100M it is aligned with. Andy p.s. OK, it might matter if you are having problems making timing from the falling edge of 100m to the rising edge of 200M, but that is unlikely if the rest of it is all running at 200 anyway.Article: 150241
On 1/4/2011 12:50 PM, Benjamin Couillard wrote:
> The first thing I tried is this
> DATA_VAL_200M<= DATA_VAL_100M and CLK_100M.
The suggestion above was a constraint, not a gated clock.
> Then I use this signal as a data_valid signal for my filter core
> running @ 200 MHz but with a sample rate of 100 MHz.
> Does anyone have a (better) solution?
I would use a synchronous design with only one clock, 200Mhz.
No constraints necessary.
-- Mike Treseler
Article: 150242On 4 jan, 19:04, Mike Treseler <mtrese...@gmail.com> wrote: > On 1/4/2011 12:50 PM, Benjamin Couillard wrote: > > > The first thing I tried is this > > DATA_VAL_200M<=3D DATA_VAL_100M and CLK_100M. > > The suggestion above was a constraint, not a gated clock. I'm aware, though, I only added this "solution" to explain what I had done so far. I will try the previous solutions > > > Then I use this signal as a data_valid signal for my filter core > > running @ 200 MHz but with a sample rate of 100 MHz. > > Does anyone have a (better) solution? > > I would use a synchronous design with only one clock, 200Mhz. > No constraints necessary. > > =A0 =A0 =A0 =A0 =A0 =A0 -- Mike Treseler In a perfect world, that's what I would do, but this is not a new design, I need to add processing blocks in an almost finished FPGA. Almost everything else in on the 100 MHz clock. In order to save some space on the FPGA,my plan was to transfer the data to the 200 MHz clock, perform the filtering operations, and then align the data to the 100 MHz clock (by converting the data_out_valid on 200 MHz to 100 MHz). That way I will use less resources than performing the filtering operations at 100 MHz.Article: 150243
> > Alternatively use VHDL2008's numeric_std_unsigned which is a replacement for the > none standard std_logic_unsigned. You can now do unsigned arithmetic (like + 1) > on std_logic_vectors without conversions. > > There is also a numeric_std_signed but Modelsim 10.0 doesn't seem to support it, > > Hanswww.ht-lab.com Yes got it including numeric_std_unsigned.all; solves the problem. :)Article: 150244
what exactly is dual port ram... how it is different from single port ram...?Is data pin a bidirectional pin? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150245
On Jan 4, 9:06=A0pm, Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > On 4 jan, 19:04, Mike Treseler <mtrese...@gmail.com> wrote: > > > On 1/4/2011 12:50 PM, Benjamin Couillard wrote: > > > > The first thing I tried is this > > > DATA_VAL_200M<=3D DATA_VAL_100M and CLK_100M. > > > The suggestion above was a constraint, not a gated clock. > > I'm aware, though, I only added this "solution" to explain what I had > done so far. I will try the previous solutions > > > > > > Then I use this signal as a data_valid signal for my filter core > > > running @ 200 MHz but with a sample rate of 100 MHz. > > > Does anyone have a (better) solution? > > > I would use a synchronous design with only one clock, 200Mhz. > > No constraints necessary. > > > =A0 =A0 =A0 =A0 =A0 =A0 -- Mike Treseler > > In a perfect world, that's what I would do, but this is not a new > design, I need to add processing blocks in an almost finished FPGA. > Almost everything else in on the 100 MHz clock. In order to save some > space on the FPGA,my plan was to transfer the data to the 200 MHz > clock, perform the filtering operations, and then align the data to > the 100 MHz clock (by converting the data_out_valid on 200 MHz to 100 > MHz). That way I will use less resources than performing the filtering > operations at 100 MHz. I think Andy nailed it. A simple, continuous toggle flop in the 200 MHz domain could serve as your data valid in that domain. You can run your 100 MHz-generated data right on through assuming that par tools will time 100MHz and 200 MHz domains together (which should occur automatically if you set up your constraint to the input of the dcm, which should propagate to its outputs). If for any reason the data doesn't last for the entire 100 Mhz cycle, simply re-register when it is valid at 100 MHz and use THAT data instead. If for whatever reason your data source has gaps (i.e. stalls), maybe you'd want to use a dual-port (dual-clocked) buffer in between domains anyway and allow the read port (200 MHz domain) extract the data as it becomes available. - JohnArticle: 150246
Top result from a Google search: http://wiki.answers.com/Q/What_is_the_difference_between_single_port_ram_dual_port_ram_and_pseudo_dual_port_ram Other search engines are available... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150247
On Dec 30 2010, 12:57=A0pm, rickman <gnu...@gmail.com> wrote: > > For a company that is so good at search engines, why can't they > understand anything about how newsgroups should work? > > Rick Because they can't tell their donkey from their elbow? One of my favorites: Google recommends using a throw-away address for usenet posting, but forces you to use your primary gmail address for posting. Sigh. Heavy sigh. RKArticle: 150248
On Jan 2, 10:33=A0am, Andy Botterill <a...@plymouth2.demon.co.uk> wrote: > > If a few more people from this newsgroup took action we may be able to > get google to do something. > I suggest starting with something easier, like ending world hunger or creating lasting peace in the middle-east. RKArticle: 150249
On Jan 5, 11:20=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Dec 30 2010, 12:57=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > For a company that is so good at search engines, why can't they > > understand anything about how newsgroups should work? > > > Rick > > Because they can't tell their donkey from their elbow? > > One of my favorites: =A0Google recommends using a throw-away address for > usenet posting, but forces you to use your primary gmail address for > posting. > > Sigh. =A0Heavy sigh. > > RK You mean your primary gmail address isn't a throw-away?
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