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>Hi, > >I would like to implement an algorithm on a deconvolution for a Spartan6. >Do you know some references of implementation or algorithm that me help >in my task? > >Thank you > http://www.lmgtfy.com/?q=deconvolution fpga --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150351
On 01/11/2011 01:52 AM, RCIngham wrote: > [big snip] >> >> I'm not an FPGA whiz, but I've done a bit of work in them. Both times >> the problem said "processor", but the customer said "no processor". You >> end up with these gawdaful state machines that grow without bound, have >> lots of synthesis gotchas (at least when I do them), and as a >> consequence are maintenance nightmares. At least when I do them I end >> up with more lines of HDL than I would of assembly code to do it on a >> processor. Perhaps a better man than I could make these work and be >> maintainable -- but perhaps a better man than I could just convince the >> customer that yes, a processor is really what's needed. >> >> Were it me I would hesitate to make the mistake _again_, and I'd figure >> that the up-front work of figuring out how to shove a processor in there >> is going to be less than the subsequent work of maintaining a >> processor-less nightmare of my own creation. >> >> -- >> >> Tim Wescott >> Wescott Design Services >> http://www.wescottdesign.com >> > > I can think of a sensible reason for the "no-processor" requirement, where > the client already does DO-254 compliant design, but does not have the > infrastructure for DO-178 (despite DO-254 being derived from DO-178 in the > writing...). So, *lots* of expense to them from adding "software". > > As to the OP's problem, the solution rather depends on whether they are > going to make<10, ~1000, or>1E6 of them. That makes sense. By and large the "no processor" thing ends up being a semantic argument, but when you start applying large amounts of semantics (like DO-178) to a project, it makes sense. Maybe Rickman's "VHDL only" processor starts to make sense, if you can just call it a "state machine". -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 150352
On Jan 11, 10:20=A0am, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >Hi, > > >I would like to implement an algorithm on a deconvolution for a Spartan6= . > >Do you know some references of implementation or algorithm that me help > >in my task? > > >Thank you > > http://www.lmgtfy.com/?q=3Ddeconvolutionfpga =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Wow! And 2 of the top three hits in Google get me back to this thread...Article: 150353
Just a follow up on this... The proposal for the "programmable logic and FPGA design" StackEchange site= has now moved to the "commitment" stage (after having nearly 100 followers= and over 50 suggested questions). In order to keep this proposal going, pe= ople need to commit to participating -- post or answer 10 questions -- when= the site goes to beta. Go to http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fp= ga-design?referrer=3DYmxhQ2OJUo-FAaI1gMp5oQ2 then register/login, and press commit. cheers, saar.Article: 150354
Tim Wescott <tim@seemywebsite.com> wrote: (snip) > That makes sense. By and large the "no processor" thing ends up being a > semantic argument, but when you start applying large amounts of > semantics (like DO-178) to a project, it makes sense. > Maybe Rickman's "VHDL only" processor starts to make sense, if you can > just call it a "state machine". Well, the other time that "no processor" is important, is when you approach the speed of ethernet (more likely fast or gigabit ethernet) and can't stand the overhead. In that case, it would be usual to have a processor handle the slow stuff, like ARP and DHCP, and then arrange a simple state machine to handle the high-speed data transfers. That is, for example, how fast managed ethernet switches work. The hardware handles the simple cases without the processor, but the rare, more complicated, cases are done by a processor. -- glenArticle: 150355
pes <dontspamme@thanks.com> wrote: > I would like to implement an algorithm on a deconvolution for a Spartan6. > Do you know some references of implementation or algorithm that me help > in my task? My favorite reference on deconvolution is "Deconvolution of Images and Spectra" by Jansson. (That is, the second edition.) I just noticed that there is a "soon to be released" paperback version from bn.com for $10.97 (preorder price). The hardcover version was about $100 when I bought mine in 1997 (when it was new). It seems that a used one is now available for $350. Note specifically that the book is about non-linear deconvolution. Even if you are planning for linear deconvolution, it is a good reference to have. -- glenArticle: 150356
On Jan 11, 12:09=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > ok the issue has been resolved but i have no idea how.. > > Previously i was using xilinx 12.1 to synthesize and implement the code. > And it was showing the behavior i posted in my first post. > > Today, just to check, i synthesized the same code on xilinx 9.1 and it > worked. > I have no idea why wasn't it working on xilinx 12.1, when both the RTLs a= re > same. > > Has anyone else experienced this problem before ? > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com You mean the "works with ISE<12, fails with ISE=3D=3D12" problem? Yes, I experience that one a lot. AArticle: 150357
Our industry has a rich history of telling lies to the customer. Dec's PDP series was called a Parallel Data Processor so that it could be purchased by department heads on their budgets. If they called it a computer then it would need CEO approval. The whole idea of a black box equivalent is that you are free to optimise the inside as long as it meets the spec on the pins. Your customer should only spec their requirements and your job is to figure out the best way to meet them John Eaton --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150358
Gabor <ga...@alacron.com> wrote about the ML561 schematics: > According to the User Guide, you should have it on the CD that ships > with the board. - You do have the board? Yes, but not the CD. :-(Article: 150359
On Jan 11, 9:33=A0pm, "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > Our industry has a rich history of telling lies to the customer. Dec's PD= P > series was called a Parallel Data Processor so that it could be purchased > by department heads on their budgets. If they called it a computer then i= t > would need CEO approval. > > The whole idea of a black box equivalent is that you are free to optimise > the inside as long as it meets the spec on the pins. Your customer should > only spec their requirements and your job is to figure out the best way t= o > meet them > > John Eaton They did, one of the requirements is that there should be no software running on a processor. RickArticle: 150360
Yes, i mean that the RTL i synthesized using xilinx ISE 12.1 didn't work, FPGA got programmed but didnt show any functionality. Whereas i synthesized the same RTL using xilinx ISE 9.1 and it worked. Do you know its reason ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150361
rickman <gnuarm@gmail.com> wrote: (snip) > They did, one of the requirements is that there should be no software > running on a processor. It is questionable, but some might say that a state machine and its state table is software running on a processor. If the state table is generated from a high-level representation of the states, then it is somewhat more obvious. -- glenArticle: 150362
In article <rJednZ9NA4SkN7HQnZ2dnUVZ_rCdnZ2d@web-ster.com>, Tim Wescott <tim@seemywebsite.com> writes: >That makes sense. By and large the "no processor" thing ends up being a >semantic argument, but when you start applying large amounts of >semantics (like DO-178) to a project, it makes sense. > >Maybe Rickman's "VHDL only" processor starts to make sense, if you can >just call it a "state machine". When a state machine has a lot of states, it's often much easier to understand if you think of it as software. It depends somewhat on the branching structure. States that jump to many other states are harder to implement. It depends... You can build a special purpose "processor" with not much more than a ROM. You only need an ALU if you want to do arithmetic. If all you want to do is wiggle wires (like a typical state machine) they come out of the ROM. For something like swapping fields in a packet so you can send it back, all you need is a register you can load/store and some way to specify the address for the packet buffer. One disadvantage of using software to make a state machine is that you need to write the assembler. That's a lot simpler if you can start with one for another project. We used to implement branches by ORing the condition being tested into a low order address bit. That means the assembler has to be smart enough to allocate pairs of addresses. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 150363
On 1/12/2011 3:07 AM, Eric Smith wrote: > Gabor<ga...@alacron.com> wrote about the ML561 schematics: >> According to the User Guide, you should have it on the CD that ships >> with the board. - You do have the board? > > Yes, but not the CD. :-( Some companies have this newfangled thing called a telephone. You can use it to speak to them, even though you might be several miles away! I dunno if Xilinx (or the distributor you bought the board from) has one though. HTH., Syms.Article: 150364
hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray) writes: > One disadvantage of using software to make a state machine > is that you need to write the assembler. That's a lot simpler I once wrote an microcode assembler generator. It read the mnemonics, opcodes, arguments, bit fields from the verilog source and then generated and ran the assembler on the fly. There were only two hard-coded directives: org and label. That way you only had to maintain the verilog source and the assembler source code, but not the assembler itself. //Petter -- .sig removed by request.Article: 150365
On Jan 11, 10:30=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Yes, i mean that the RTL i synthesized using xilinx ISE 12.1 didn't work, > FPGA got programmed but didnt show any functionality. Whereas i synthesiz= ed > the same RTL using xilinx ISE 9.1 and it worked. > > Do you know its reason ? =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com There is a software defect in Version 12's synthesis (XST) phase. The same defect is present in Version 11. In addition, Version 12 has a software defect in the placer (MAP). That defect is not present in Version 11. <vent> I have lost (wasted) many (100 or more) billable hours describing these defects to Xilinx. After I was *finally* understood, the only response I heard was "Oh". </vent> Two known work-arounds: 1) Never update past ISE Version 10. 2) Use Quartus-II or ISP-Lever. Unfortunately, both prevent you from using the newest Xilinx parts. Oh well. RKArticle: 150366
d_s_klein <d_s_klein@yahoo.com> wrote: > There is a software defect in Version 12's synthesis (XST) phase. The > same defect is present in Version 11. > In addition, Version 12 has a software defect in the placer (MAP). > That defect is not present in Version 11. > <vent> > I have lost (wasted) many (100 or more) billable hours describing > these defects to Xilinx. After I was *finally* understood, the only > response I heard was "Oh". > </vent> Probably there is no visible trace of that error in the Xilinx answer data base. Could you perhaps describe these errors a little so we don't stumble on them? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 150367
On Jan 12, 2:56=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rickman <gnu...@gmail.com> wrote: > > (snip) > > > They did, one of the requirements is that there should be no software > > running on a processor. > > It is questionable, but some might say that a state machine and > its state table is software running on a processor. > > If the state table is generated from a high-level representation > of the states, then it is somewhat more obvious. > > -- glen That distinction is up to the customer to define, no? One thing I never do is buck the customer... or I should say, one thing I never do ANYMORE. I've done it before and it never works out to my best interest.... no matter how wrong the customer might be. RickArticle: 150368
On Jan 12, 6:33=A0am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > In article <rJednZ9NA4SkN7HQnZ2dnUVZ_rCdn...@web-ster.com>, > =A0Tim Wescott <t...@seemywebsite.com> writes: > > >Maybe Rickman's "VHDL only" processor starts to make sense, if you can > >just call it a "state machine". > > When a state machine has a lot of states, it's often much easier > to understand if you think of it as software. =A0It depends somewhat > on the branching structure. =A0States that jump to many other > states are harder to implement. =A0It depends... Branching is one of the simplest things to do. That is just a conditional, this is the next state or that is the next state. > You can build a special purpose "processor" with not much > more than a ROM. =A0You only need an ALU if you want to do > arithmetic. =A0If all you want to do is wiggle wires (like > a typical state machine) they come out of the ROM. "Processor" may be a grand word for what I am thinking. Typically all that is needed is a sequencer, which is just a way of addressing the ROM including the conditional flow of a state machine. Everything else, data flow, control circuitry, etc., is application specific and may or may not use a general purpose ALU like structure. > For something like swapping fields in a packet so you can > send it back, all you need is a register you can load/store > and some way to specify the address for the packet buffer. > > One disadvantage of using software to make a state machine > is that you need to write the assembler. =A0That's a lot simpler > if you can start with one for another project. My idea is to avoid all that. Your opcodes are just constants in VHDL that are used to define the contents of the ROM. No assembler needed. > We used to implement branches by ORing the condition being > tested into a low order address bit. =A0That means the assembler > has to be smart enough to allocate pairs of addresses. Simpler hardware, less simple software. RickArticle: 150369
On Jan 4, 2:42=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > >Hi everyone, I've got a question. > > >Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz > >clock. The clocks are in phase, i.e. a rising edge on the 100 MHz > >occurs at the same time as a rising edge 200 MHz clock. > > >. In my application I =A0want to process the data @ 200 MHz to reduce > >filter complexity, i.e. my filters would use only half of the > >multipliers compared to running the filters @ 100 MHz. However, the > >effective sampling rate would remain the same i.e. 100 MHz. =A0I need to > >obtain a data valid signal enabled 50% of the time, since there would > >be a new data 1 cycle out of 2 on the 200 MHz clock. > > >I could use an asynchronous FIFO to get the data valid @ 200 MHz, but > >I think this solution is overkill since both clocks are in phase-lock. > > >What would you do? I want the data valid to be enabled 50% of the > >time, and I want the data_valid to be '1' when my 16 bits data sample > >change. > > I'd use a timing constrain. If the tools know about the clocks coming > from inside the FPGA the tools might create the timing constraints > automatically based on the input clock. I know the XIlinx tools create > such contraints automatically. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > -------------------------------------------------------------- How do you feed the hungry monster ? Do you mean you have 2 data channels comming @100 Mhz, then you plan to use only one monster to eat the data at 200 Mhz ? how many bytes per second, is depends on the monsterArticle: 150370
On Dec 15 2010, 10:59=A0am, ghelbig <ghel...@lycos.com> wrote: > Sorry, but I need to vent. > > I have a design that works just fine with ISE-11.5, and fails 'PAR' > with ISE-12.3 > > I opened a web case about my design failing PAR. =A0The archive of the > project created with ISE was incomplete, so it has taken a while (six > weeks) to get all of the files transferred. > > I just got an email from Xilinx Tech Support: =A0"Your design fails PAR > with ISE-12, can you help ..." > > Sigh. =A0Heavy sigh. > > Thanks for listening, > G. Xilinx bugs always make my feet coldArticle: 150371
On Dec 22 2010, 1:01=A0pm, "MM" <mb...@yahoo.com> wrote: > You might want trying to run multiple strategies using either PlanAhead He can joint the beatAhead team to solve the problemArticle: 150372
On Jan 11, 2:09=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > ok the issue has been resolved but i have no idea how.. > > Previously i was using xilinx 12.1 to synthesize and implement the code. > And it was showing the behavior i posted in my first post. > > Today, just to check, i synthesized the same code on xilinx 9.1 and it > worked. > I have no idea why wasn't it working on xilinx 12.1, when both the RTLs a= re > same. > > Has anyone else experienced this problem before ? > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com the one that failed probably pulled out a netlist from your co-worker last year design, not a surprise bugArticle: 150373
On Jan 12, 9:42=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > d_s_klein <d_s_kl...@yahoo.com> wrote: > > There is a software defect in Version 12's synthesis (XST) phase. =A0Th= e > > same defect is present in Version 11. > > In addition, Version 12 has a software defect in the placer (MAP). > > That defect is not present in Version 11. > > <vent> > > I have lost (wasted) many (100 or more) billable hours describing > > these defects to Xilinx. =A0After I was *finally* understood, the only > > response I heard was "Oh". > > </vent> > > Probably there is no visible trace of that error in the Xilinx answer dat= a > base. > > Could you perhaps describe these errors a little so we don't stumble on > them? > > Thanks > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- My notes don't exist anymore, but... I had some Verilog that worked "just fine" with ISE <=3D 10, but with 11 and 12 PAR would fail to bind a LUT. The defect was traced to XST 11 and 12 - if I used the output of XST-10 then 11 or 12 could finish properly. Right now I'm fighting a different ISE problem that is consuming all of my attention: I have data that goes through 3 clock domains, A, B, and C. These domains are connected with 2-clock/asynch FIFOs from coregen. The FIFOs are hard placed in the UCF, and regions A and C have non-overlapping area constraints. B is allowed to go "wherever" to connect then up. If I make a small change in the logic in area "A", then area "C" fails timing, and it fails by a LOT. Looking at the timing report, the net delay(s) have 25% logic, 75% route. If I go back to "working" and extract/constrain placement information, it gets worse... Argh.Article: 150374
On 12/15/2010 4:59 PM, ghelbig wrote: > Sorry, but I need to vent. > > I have a design that works just fine with ISE-11.5, and fails 'PAR' > with ISE-12.3 > > I opened a web case about my design failing PAR. The archive of the > project created with ISE was incomplete, so it has taken a while (six > weeks) to get all of the files transferred. > > I just got an email from Xilinx Tech Support: "Your design fails PAR > with ISE-12, can you help ..." > > Sigh. Heavy sigh. > > Thanks for listening, > G. If you think designing with their parts is bad, you should try logging onto glassdoor.com and find out what people who claim to be employees think of working at the place. Syms.
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