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If you didn't see it already in our our newsletter we have a new PCIe devopment board based on an Altera Cyclone-IV GX. The new board keeps most of the mechanicals and features of our Raggedstone product range but extends the bandwidth capability of the product range. The Raggedstone3 is capabile of bandwidths exceeding 800 MBytes/s over it's X4 PCIe interface. Initial details of this product http://www.enterpoint.co.uk/raggedstone/raggedstone3.html. Anyone at ESC this week can see the board there on our stand. I am expecting this board to ship to customers in low numbers in June or July with a significant ramp in shipping numbers after that. John Adair Enterpoint Ltd.Article: 151651
Also new this week is our XC3SD3400A Coprocessor module. Not surprisingly it is based on a Xilinx Spartan-3A DSP XC3SD3400A FPGA. Module has JTAG, SPI configuration and a 6A core voltage regulator as support features. The module can also be set up for external JTAG and configuration. A range of pinning options are available so you plug the module into your own boards or even as an add-on to many of our own products. More details http://www.enterpoint.co.uk/oem_industrial/xc3sd3400a_coprocessor.html. John Adair Enterpoint Ltd.Article: 151652
i have implemented a powerpc based embedded system in a xilinix
vertex-2pro device and trying out an extremely simple program. Here is
the code.
#include "xparameters.h"
#include "xbasic_types.h"
#include "xgpio.h"
#include "xstatus.h"
XGpio GpioOutput;
int main()
{
Xuint32 status;
unsigned long i = 0;
unsigned long j = 0;
// Initialize the GPIO driver so that it's ready to use,
status = XGpio_Initialize(&GpioOutput,
XPAR_GENERIC_GPIO_DEVICE_ID);
if (status != XST_SUCCESS)
return XST_FAILURE;
// Set the direction for all signals to be outputs
XGpio_SetDataDirection(&GpioOutput, 1, 0x0);
while(1)
{
XGpio_DiscreteWrite(&GpioOutput, 1, 0xFFFFFFF1);
while(i < 10000000)
{
i++;
}
XGpio_DiscreteWrite(&GpioOutput, 1, 0xFFFFFFF2);
while(j < 10000000)
{
j++;
}
i = 0;
j = 0;
}
return 0;
}
As can be seen, this program just blinks two LED's. However what i see
is two dimmed LED's. They are dimmed because they blink very fast. It
appears like two inner while loops are just skipped. Can anybody guess
a reason?
Thanks
Article: 151653
On May 2, 9:34=A0am, Manusha <manusha1...@gmail.com> wrote:
> i have implemented a powerpc based embedded system in a xilinix
> vertex-2pro device and trying out an extremely simple program. Here is
> the code.
>
> #include "xparameters.h"
> #include "xbasic_types.h"
> #include "xgpio.h"
> #include "xstatus.h"
>
> XGpio GpioOutput;
>
> int main()
> {
> =A0 =A0 =A0 =A0 Xuint32 status;
> =A0 =A0 =A0 =A0 unsigned long i =3D 0;
> =A0 =A0 =A0 =A0 unsigned long j =3D 0;
>
> // Initialize the GPIO driver so that it's ready to use,
> =A0 status =3D XGpio_Initialize(&GpioOutput,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XPAR_G=
ENERIC_GPIO_DEVICE_ID);
> =A0 if (status !=3D XST_SUCCESS)
> =A0 =A0 return XST_FAILURE;
> =A0 // Set the direction for all signals to be outputs
> =A0 XGpio_SetDataDirection(&GpioOutput, 1, 0x0);
>
> =A0 =A0 =A0 =A0 while(1)
> =A0 =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XGpio_DiscreteWrite(&GpioOutput, 1, 0xFFF=
FFFF1);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 while(i < 10000000)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i++;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XGpio_DiscreteWrite(&GpioOutput, 1, 0xFFF=
FFFF2);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 while(j < 10000000)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 j++;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i =3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 j =3D 0;
>
> =A0 =A0 =A0 =A0 }
> =A0 =A0 =A0 =A0 return 0;
>
> }
>
> As can be seen, this program just blinks two LED's. However what i see
> is two dimmed LED's. They are dimmed because they blink very fast. It
> appears like two inner while loops are just skipped. Can anybody guess
> a reason?
>
> Thanks
Compilers usually optimize out loops like this. You should try using
the timer functions to wait for a specific amount of time.
Ed McGettigan
--
Xilinx Inc.
Article: 151654
On May 2, 10:53=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> On May 2, 9:34=A0am, Manusha <manusha1...@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > i have implemented a powerpc based embedded system in a xilinix
> > vertex-2pro device and trying out an extremely simple program. Here is
> > the code.
>
> > #include "xparameters.h"
> > #include "xbasic_types.h"
> > #include "xgpio.h"
> > #include "xstatus.h"
>
> > XGpio GpioOutput;
>
> > int main()
> > {
> > =A0 =A0 =A0 =A0 Xuint32 status;
> > =A0 =A0 =A0 =A0 unsigned long i =3D 0;
> > =A0 =A0 =A0 =A0 unsigned long j =3D 0;
>
> > // Initialize the GPIO driver so that it's ready to use,
> > =A0 status =3D XGpio_Initialize(&GpioOutput,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XPAR=
_GENERIC_GPIO_DEVICE_ID);
> > =A0 if (status !=3D XST_SUCCESS)
> > =A0 =A0 return XST_FAILURE;
> > =A0 // Set the direction for all signals to be outputs
> > =A0 XGpio_SetDataDirection(&GpioOutput, 1, 0x0);
>
> > =A0 =A0 =A0 =A0 while(1)
> > =A0 =A0 =A0 =A0 {
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XGpio_DiscreteWrite(&GpioOutput, 1, 0xF=
FFFFFF1);
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 while(i < 10000000)
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i++;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XGpio_DiscreteWrite(&GpioOutput, 1, 0xF=
FFFFFF2);
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 while(j < 10000000)
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 j++;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i =3D 0;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 j =3D 0;
>
> > =A0 =A0 =A0 =A0 }
> > =A0 =A0 =A0 =A0 return 0;
>
> > }
>
> > As can be seen, this program just blinks two LED's. However what i see
> > is two dimmed LED's. They are dimmed because they blink very fast. It
> > appears like two inner while loops are just skipped. Can anybody guess
> > a reason?
>
> > Thanks
>
> Compilers usually optimize out loops like this. =A0You should try using
> the timer functions to wait for a specific amount of time.
>
> Ed McGettigan
> --
> Xilinx Inc.
Thanks. I disabled optimizations and now it works fine.
Article: 151655>Compilers usually optimize out loops like this. You should try using >the timer functions to wait for a specific amount of time. Sometimes you want delays that are short, perhaps shorter than the unknown overhead of calling some library routine. I think the recipe to run the compiler in dumb/stupid mode that doesn't do any optomizations like that should be well documented. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 151656
John Adair <g1@enterpoint.co.uk> wrote: >Also new this week is our XC3SD3400A Coprocessor module. Not >surprisingly it is based on a Xilinx Spartan-3A DSP XC3SD3400A FPGA. >Module has JTAG, SPI configuration and a 6A core voltage regulator as >support features. The module can also be set up for external JTAG and >configuration. > >A range of pinning options are available so you plug the module into >your own boards or even as an add-on to many of our own products. > >More details http://www.enterpoint.co.uk/oem_industrial/xc3sd3400a_coprocessor.html. Interesting. Price tag? -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151657
On 05/02/2011 08:29 PM, Manusha wrote:
> On May 2, 10:53 pm, Ed McGettigan<ed.mcgetti...@xilinx.com> wrote:
>> On May 2, 9:34 am, Manusha<manusha1...@gmail.com> wrote:
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>> i have implemented a powerpc based embedded system in a xilinix
>>> vertex-2pro device and trying out an extremely simple program. Here is
>>> the code.
>>
>>> #include "xparameters.h"
>>> #include "xbasic_types.h"
>>> #include "xgpio.h"
>>> #include "xstatus.h"
>>
>>> XGpio GpioOutput;
>>
>>> int main()
>>> {
>>> Xuint32 status;
>>> unsigned long i = 0;
>>> unsigned long j = 0;
>>
>>> // Initialize the GPIO driver so that it's ready to use,
>>> status = XGpio_Initialize(&GpioOutput,
>>> XPAR_GENERIC_GPIO_DEVICE_ID);
>>> if (status != XST_SUCCESS)
>>> return XST_FAILURE;
>>> // Set the direction for all signals to be outputs
>>> XGpio_SetDataDirection(&GpioOutput, 1, 0x0);
>>
>>> while(1)
>>> {
>>> XGpio_DiscreteWrite(&GpioOutput, 1, 0xFFFFFFF1);
>>> while(i< 10000000)
>>> {
>>> i++;
>>> }
>>> XGpio_DiscreteWrite(&GpioOutput, 1, 0xFFFFFFF2);
>>> while(j< 10000000)
>>> {
>>> j++;
>>> }
>>> i = 0;
>>> j = 0;
>>
>>> }
>>> return 0;
>>
>>> }
>>
>>> As can be seen, this program just blinks two LED's. However what i see
>>> is two dimmed LED's. They are dimmed because they blink very fast. It
>>> appears like two inner while loops are just skipped. Can anybody guess
>>> a reason?
>>
>>> Thanks
>>
>> Compilers usually optimize out loops like this. You should try using
>> the timer functions to wait for a specific amount of time.
>>
>> Ed McGettigan
>> --
>> Xilinx Inc.
>
> Thanks. I disabled optimizations and now it works fine.
Instead of disabling optimizations, try this:
volatile unsigned long i = 0;
volatile unsigned long j = 0;
With the 'volatile' qualifier, the compiler is not allowed to optimize
away load/stores to that variable. The rest of your code will still be
optimized. Disabling all optimization isn't guaranteed to work anyway.
btw, it's more compact to use a 'for' loop, and only a single variable:
for( i = 0; i < 1000000; i++ );
Article: 151658On 02/05/2011 20:29, Manusha wrote: > On May 2, 10:53 pm, Ed McGettigan<ed.mcgetti...@xilinx.com> wrote: >> On May 2, 9:34 am, Manusha<manusha1...@gmail.com> wrote: >> >> <skip> >>> As can be seen, this program just blinks two LED's. However what i see >>> is two dimmed LED's. They are dimmed because they blink very fast. It >>> appears like two inner while loops are just skipped. Can anybody guess >>> a reason? >> >>> Thanks >> >> Compilers usually optimize out loops like this. You should try using >> the timer functions to wait for a specific amount of time. >> >> Ed McGettigan >> -- >> Xilinx Inc. > > Thanks. I disabled optimizations and now it works fine. No, your program does /not/ work - it is still broken. There is no such thing as code that "works fine with optimisations disabled". You should correct your program - and do that from day 1 on your first blinking light test program. Ed gave you the best solution - when you want something to run at specific times, use timers (timer functions, timer library calls, RTOS functions, hardware timers, or whatever is appropriate for your platform). If you want to have a simple loop for a rough delay or for testing, the easiest way is to declare your loop variables to be "volatile" (as "volatile unsigned long int i = 0;"). This is telling your compiler how you want it to treat that variable - it should always read and write it exactly as written in the source code, rather than generating faster or smaller code.Article: 151659
Manusha <manusha1980@gmail.com> wrote:
>On May 2, 10:53=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>> On May 2, 9:34=A0am, Manusha <manusha1...@gmail.com> wrote:
>>
>>
>> > i have implemented a powerpc based embedded system in a xilinix
>> > vertex-2pro device and trying out an extremely simple program. Here is
>> > the code.
>>
>> > #include "xparameters.h"
>> > #include "xbasic_types.h"
>> > #include "xgpio.h"
>> > #include "xstatus.h"
>>
>> > XGpio GpioOutput;
>>
>> > int main()
>> > {
>> > =A0 =A0 =A0 =A0 Xuint32 status;
>> > =A0 =A0 =A0 =A0 unsigned long i =3D 0;
>> > =A0 =A0 =A0 =A0 unsigned long j =3D 0;
>>
>> > // Initialize the GPIO driver so that it's ready to use,
>> > =A0 status =3D XGpio_Initialize(&GpioOutput,
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0XPAR=
>_GENERIC_GPIO_DEVICE_ID);
>> > =A0 if (status !=3D XST_SUCCESS)
>> > =A0 =A0 return XST_FAILURE;
>> > =A0 // Set the direction for all signals to be outputs
>> > =A0 XGpio_SetDataDirection(&GpioOutput, 1, 0x0);
>>
>> > =A0 =A0 =A0 =A0 while(1)
>> > =A0 =A0 =A0 =A0 {
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XGpio_DiscreteWrite(&GpioOutput, 1, 0xF=
>FFFFFF1);
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 while(i < 10000000)
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i++;
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 XGpio_DiscreteWrite(&GpioOutput, 1, 0xF=
>FFFFFF2);
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 while(j < 10000000)
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 {
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 j++;
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i =3D 0;
>> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 j =3D 0;
>>
>> > =A0 =A0 =A0 =A0 }
>> > =A0 =A0 =A0 =A0 return 0;
>>
>> > }
>>
>> > As can be seen, this program just blinks two LED's. However what i see
>> > is two dimmed LED's. They are dimmed because they blink very fast. It
>> > appears like two inner while loops are just skipped. Can anybody guess
>> > a reason?
>>
>> > Thanks
>>
>> Compilers usually optimize out loops like this. =A0You should try using
>> the timer functions to wait for a specific amount of time.
>>
>> Ed McGettigan
>> --
>> Xilinx Inc.
>
>Thanks. I disabled optimizations and now it works fine.
Which compiler did you use? Smart C compilers do not get rid of empty
loops because they are often used to wait for small periods of time.
There is a difference between optimising and breaking a program!
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------
Article: 151660Hey guys! Terasic Technologies is holding a contest to WIN the newly released Altera DE0-Nano! Head over to http://www.terasic.com.tw/events/DE0_Nano_Contest/ to leave a comment and win one today!!! Thanks, Allen Houng Terasic Technologies www.terasic.comArticle: 151661
On May 3, 4:59=A0am, n...@puntnl.niks (Nico Coesel) wrote: > Which compiler did you use? Smart C compilers do not get rid of empty > loops because they are often used to wait for small periods of time. > There is a difference between optimising and breaking a program! Why is the compiler breaking the program, when the loop is removed? When it ignores whitespace, does it break the program too?Article: 151662
In that kind of loop you should always use the qualifier volatile to avoid optimizations as you should do for any hw register mapped in memory...to avoid caching problems... Carlo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151663
On 05/03/2011 10:59 AM, Nico Coesel wrote: > Which compiler did you use? Smart C compilers do not get rid of empty > loops because they are often used to wait for small periods of time. > There is a difference between optimising and breaking a program! If this optimization breaks your program, it was poorly written in the first place. Use 'volatile' and it can't happen. Empty loops could be the result of other optimizations, perhaps as a result of some #define settings. For example, you could have code targeted for a multi-CPU environment, with a #define saying how many CPUs you have. For the case that this number equals '1', a lot of code could be redundant, and you'd want the compiler to optimize it away, even if it looks like a delay loop.Article: 151664
The module is GBP =A345, USD $75, 55=80 without a programming cable. John Adair Enterpoint Ltd. On May 3, 6:25=A0am, n...@puntnl.niks (Nico Coesel) wrote: > John Adair <g...@enterpoint.co.uk> wrote: > >Also new this week is our XC3SD3400A Coprocessor module. Not > >surprisingly it is based on a Xilinx Spartan-3A DSP XC3SD3400A FPGA. > >Module has JTAG, SPI configuration and a 6A core voltage regulator as > >support features. The module can also be set up for external JTAG and > >configuration. > > >A range of pinning options are available so you plug the module into > >your own boards or even as an add-on to many of our own products. > > >More detailshttp://www.enterpoint.co.uk/oem_industrial/xc3sd3400a_coproc= essor.html. > > Interesting. Price tag? > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > --------------------------------------------------------------Article: 151665
On Apr 27, 10:34=A0am, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > On Apr 26, 8:40=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Apr 26, 10:07=A0pm, "mary" <marysowji.99@n_o_s_p_a_m.gmail.com> > > wrote: > > > > hi all, > > > > i have a doubt regarding no.of slices in xlinx > > > > what are slices? > > > what are LUT? in xilinx > > > > 1)the no.of slice constant in every version or does it vary? > > > > 2)can the area of an architecture be decreased if we say no.of slices= are > > > decreased. > > > is this type of approach is correct? > > > or > > > 3) how can we say a area of architecture is decreased? > > > > 4)i am implementing project which is having the no.of slices in order= of > > > hundreds. > > > where as the previous technique implemented have the no.of slices in = order > > > of thousands from =A0this can we conclude that the area is decreased. > > > A LUT is a "look up table" and are how an FPGA implements > > combinatorial logic. =A0For all practical purposes it is a block of > > memory with the logic inputs used as the address and the data output > > used as the logic output. =A0The memory contents defines that logic > > function implemented. =A0Is that what you are asking? > > > For a long time all LUTs in Xilinx parts had four inputs although they > > did some funky things with multiplexers to allow two or even four of > > the four input LUTS to be combined into five and even six input LUTS. > > In some of the newer parts in the high end logic families they provide > > six input LUTS. =A0This is partly because the parts are getting so larg= e > > that, like the CPUs in PCs they are having trouble finding ways to use > > the larger number of transistors. =A0So they are making the LUTs > > larger. > > > A slice is just a grouping of LUTs and FFs and some connective > > structure into the repeated unit of the FPGA. =A0The number of LUTs and > > FFs vary with family. =A0Originally LUTs had two LUTs and two FFs. > > According to the manual "Each Virtex-6 FPGA slice contains four LUTs > > and eight flip-flops", but they also use the term "Logic Cells" which > > is not a countable entity in a part, it is a marketing number like > > "gates". > > > Using the number of slices used is not a good metric for the size of a > > design because if one LUT is used, the slice is counted as used. > > Better to count the number of LUTs and FF used. =A0You can have 100% > > slice utilization and still fit more into a chip. =A0But when 100% of > > the LUTs and FFs are used, you will be hard pressed to add anything to > > that design! > > > Rick > > The OP should thank you for doing their (class) homework for them. > > RK Wow, I don't know homework can be done easily online today. The question is, does he remember anything afterward ? I think he doesArticle: 151666
On 05/03/2011 11:37, allen wrote: > Hey guys! > > Terasic Technologies is holding a contest to WIN the newly released > Altera DE0-Nano! Head over to http://www.terasic.com.tw/events/DE0_Nano_Contest/ > to leave a comment and win one today!!! For some reason, this contest is set up to use Facebook. I don't use Facebook (and no, I won't start using it either), so thanks, but this contest is not for me. -- Torfinn Ingolfsen, NorwayArticle: 151667
> The question is, does he remember anything afterward ? I think he does Hmm. You could make him solve a (homework) excercise, to find out if he does?Article: 151668
A related question: From same site as previous post, I downloaded the packages for ise 11.1 as = I wanted modelsim to use the same fixed point arithmetic as ISE eventually = would use for synthesis and implementation. Now, ISE is at version 13 and I= wonder if anything has improved regarding fixed point arithmetic since 11.= 1. Division was commented out as 11.1 obviously had problems. I can't use I= SIM as my code make it barf at me, and modelsim is not allowed to distribut= e the said ieee libraries, so I have to do it myself anyway. --=20 SvennArticle: 151669
>A related question: >From same site as previous post, I downloaded the packages for ise 11.1 as = >I wanted modelsim to use the same fixed point arithmetic as ISE eventually = >would use for synthesis and implementation. Now, ISE is at version 13 and I= > wonder if anything has improved regarding fixed point arithmetic since 11.= >1. Division was commented out as 11.1 obviously had problems. I can't use I= >SIM as my code make it barf at me, and modelsim is not allowed to distribut= >e the said ieee libraries, so I have to do it myself anyway. > >--=20 >Svenn > You are more likely to get a response if you ask the question at the Xilinx forums, e.g.: http://forums.xilinx.com/t5/Synthesis/bd-p/SYNTHBD --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151670
On Apr 27, 11:34=A0am, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > On Apr 26, 8:40=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Apr 26, 10:07=A0pm, "mary" <marysowji.99@n_o_s_p_a_m.gmail.com> > > wrote: > > > > hi all, > > > > i have a doubt regarding no.of slices in xlinx > > > > what are slices? > > > what are LUT? in xilinx > > > > 1)the no.of slice constant in every version or does it vary? > > > > 2)can the area of an architecture be decreased if we say no.of slices= are > > > decreased. > > > is this type of approach is correct? > > > or > > > 3) how can we say a area of architecture is decreased? > > > > 4)i am implementing project which is having the no.of slices in order= of > > > hundreds. > > > where as the previous technique implemented have the no.of slices in = order > > > of thousands from =A0this can we conclude that the area is decreased. > > > A LUT is a "look up table" and are how an FPGA implements > > combinatorial logic. =A0For all practical purposes it is a block of > > memory with the logic inputs used as the address and the data output > > used as the logic output. =A0The memory contents defines that logic > > function implemented. =A0Is that what you are asking? > > > For a long time all LUTs in Xilinx parts had four inputs although they > > did some funky things with multiplexers to allow two or even four of > > the four input LUTS to be combined into five and even six input LUTS. > > In some of the newer parts in the high end logic families they provide > > six input LUTS. =A0This is partly because the parts are getting so larg= e > > that, like the CPUs in PCs they are having trouble finding ways to use > > the larger number of transistors. =A0So they are making the LUTs > > larger. > > > A slice is just a grouping of LUTs and FFs and some connective > > structure into the repeated unit of the FPGA. =A0The number of LUTs and > > FFs vary with family. =A0Originally LUTs had two LUTs and two FFs. > > According to the manual "Each Virtex-6 FPGA slice contains four LUTs > > and eight flip-flops", but they also use the term "Logic Cells" which > > is not a countable entity in a part, it is a marketing number like > > "gates". > > > Using the number of slices used is not a good metric for the size of a > > design because if one LUT is used, the slice is counted as used. > > Better to count the number of LUTs and FF used. =A0You can have 100% > > slice utilization and still fit more into a chip. =A0But when 100% of > > the LUTs and FFs are used, you will be hard pressed to add anything to > > that design! > > > Rick > > The OP should thank you for doing their (class) homework for them. > > RK Yeah, you may be right. But if test questions are asking about vague things like "slices" then he needs a new professor. RickArticle: 151671
This is what I posted on the xilinx forum http://forums.xilinx.com/t5/Synth=
esis/ieee-proposed-fixed-pkg-all-in-Xilinx-ISE-12-1/m-p/76151/highlight/fal=
se#M2428
I usually value comp.arch.fpga as a superior source of information.
<crosspost start>
I just want to pick up this issue for ISE 12.3 for Spartan 3A DSP.
I see differences between the ieee_proposed.fixed_pkg in $Xilinx/vhdl/src/i=
eee_proposed and the compatibility package for ISE 11.1 on http://www.eda-s=
tds.org/fphdl/. I have enabled the division in the package from eda-stds.or=
g to test if 12.3 handles the division as I want to implement a cumulative =
moving average algorithm which includes a division.
In both cases, ISE barfs at me with the message:
ERROR:Xst:769 - "/opt/Xilinx/12.3/ISE_DS/ISE/vhdl/src/ieee_proposed/fixed_p=
kg_c.vhd" line 2059: Operator <INVALID OPERATOR> must have constant operand=
s or first operand must be power of 2
VHDL code is something like:
architecture example of some_module is
signal cma : sfixed (3 downto -9); --! signed fixed accumu=
lator for average
signal avg_count : integer; --! Counter for number =
of phase measurements
begin
p_out_mux_reg : process (clk_96m) is
variable tmp : sfixed (2 downto -9); --! A temp value depend=
ing on size of phase (pi or 2pi)
begin
if rising_edge(clk_96m) then
if sel_out =3D '1' then
tmp :=3D sum_pi2_sfix;
else
tmp :=3D diff_ab2_sfix;
end if;
-- only accumulate average when value from cordic is updated.
if rdy_cordic =3D '1' then
cma <=3D resize(cma + (tmp - cma)/avg_count, cma);
avg_count <=3D avg_count + 1;
end if;
-- when measurement starts, initialize accumulator.
if enable_mea =3D '1' then
cma <=3D resize(tmp, cma);
avg_count <=3D 0;
end if;
end if;
end process;
end example;
I wonder if the Xilinx ieee_proposed is meant for VHDL-2008 or if it is use=
ful for VHDL-93, too.
Modelsim and Rtlvision is able to make something useful out of my cma, but =
ISE isn't.
Since ISE barfs at the same line, independently of Xilinx code or eda-stds.=
org code, I guess the problem lies within ISE, but I hope I am wrong.
--=20
Svenn
Article: 151672On 5/2/2011 1:42 PM, John Adair wrote: > If you didn't see it already in our our newsletter we have a new PCIe > devopment board based on an Altera Cyclone-IV GX. The new board keeps > most of the mechanicals and features of our Raggedstone product range > but extends the bandwidth capability of the product range. The > Raggedstone3 is capabile of bandwidths exceeding 800 MBytes/s over > it's X4 PCIe interface. > > Initial details of this product http://www.enterpoint.co.uk/raggedstone/raggedstone3.html. > Anyone at ESC this week can see the board there on our stand. > > I am expecting this board to ship to customers in low numbers in June > or July with a significant ramp in shipping numbers after that. > > John Adair > Enterpoint Ltd. Hi John, I have a question for you (and the group) about PCIe. Let's say I build a PCIe target in my Altera device, and let's say for the sake of argument that it's a Ethernet MAC. My Linux single board computer (SBC) has a software driver for this Ethernet device. As the Linux boots, it sees the PCIe device and loads the driver. What happens if, without rebooting the SBC, I reconfigure the Altera part? How does the OS react to the PCIe device vanishing from the bus and then subsequently reappearing? Thanks, Symon.Article: 151673
Jim Granville <j.m.granville@gmail.com> writes: > Or, you could wait for the MachXO2 breakout ;) > - and I see they now have this real, at $29. > > http://www.latticesemi.com/products/developmenthardware/developmentkits/machxo2picokit.cfm Interesting offering from Lattice again. Too bad the price is quite different from $29 for those of us on the wrong side of the pond...Article: 151674
The Logic Accessible Clocks are entailed for example in http://www.cisl.columbia.edu/courses/spring-2004/ee4340/restricted_handouts/xapp200.pdf. I do not see much explanation of the concept. But, I would expect some when sys_clk_fb is registered by in-sync clk2. Sinse both clocks switch at the same time, the setup/hold time, the basics of HW design, are violated for sure!
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