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Gabor,
Per the reference manual, you use three processes: one for each (rise/fall)=
register, and one for a mux controlled by the clock level. You have to eith=
er use opposite edges of the same clock signal, or use two clocks from the =
same DCM that are 180 degrees apart in phase. As with most things in the re=
ference manual, they often support additional means (e.g. a single process =
with two clocks or both edges of one clock, mutually exclusive, as specifie=
d in 1076.6). I know they support dual-edged processes in which the same si=
gnal/variable is not assigned on both edges, so I suppose you could do it i=
n at most two, if not a single process (using variables for the registers a=
nd a mux assignment to the output signal after the last "end if":
process (rst, clk) is
variable qr, qf: std_logic;
begin
if rst then
qr :=3D '0';
qf :=3D '0';
elsif rising_edge(clk) then
qr :=3D d;
elsif falling_edge(clk) then
qf :=3D d;
end if;
output <=3D (qr and clk) or (qf and not clk);
end process;
It's been a long time since I used synplify for a xilinx platform, so I don=
't know if the 1076.6 method works or not (including a double-edge process =
with assignments on both edges to the same output signal). Note that synpli=
fy does not support inferrence for all target architectures that have DDR o=
utput registers.=20
Andy
Article: 154976
jonesandy@comcast.net wrote:
> Gabor,
>
> Per the reference manual, you use three processes: one for each (rise/fall)register, and one for a mux controlled by the clock level. You have to either use opposite edges of the same clock signal, or use two clocks from the same DCM that are 180 degrees apart in phase. As with most things in the reference manual, they often support additional means (e.g. a single process with two clocks or both edges of one clock, mutually exclusive, as specified in 1076.6). I know they support dual-edged processes in which the same signal/variable is not assigned on both edges, so I suppose you could do it in at most two, if not a single process (using variables for the registers and a mux assignment to the output signal after the last "end if":
>
> process (rst, clk) is
> variable qr, qf: std_logic;
> begin
> if rst then
> qr := '0';
> qf := '0';
> elsif rising_edge(clk) then
> qr := d;
> elsif falling_edge(clk) then
> qf := d;
> end if;
> output <= (qr and clk) or (qf and not clk);
> end process;
>
> It's been a long time since I used synplify for a xilinx platform, so I don't know if the 1076.6 method works or not (including a double-edge process with assignments on both edges to the same output signal). Note that synplify does not support inferrence for all target architectures that have DDR output registers.
>
> Andy
I'm sure there's many ways to describe this in a single process in VHDL,
I was sondering what the Verilog template looked like (since the thread
started off on that vein).
For VHDL I could see a single process without variables like:
process (rst, clk1, clk2) is
begin
if rst then
ouput <= '0';
else
if rising_edge(clk1) then
output <= d1;
end if;
if rising_edge(clk2) then
output <= d2;
end if;
end if;
end process;
Where this version more nearly models the Xilinx style dual clock,
dual D DDR flops. You could also use a synchronous reset (in the
primitive this is a parameter or generic). But in any case I
don't see how you'll model this in a single Verilog always block,
and if not, then there is an unusual exception for synthesis needed
to infer this without multi-source errors, or else it would need
two processes with two separate signals and an external mux, all
of which the synthesis tool would understand how to pack into
one DDR flop.
-- Gabor
Article: 154977Did you try just loading the data ? Some ee devices simply over-writeArticle: 154978
jg wrote: > Did you try just loading the data ? > Some ee devices simply over-write Yes, I tried this, and it didn't work. After a number of people on other forums suggested the same, I tried it again, and it worked! So, I must have had a dirty contact on the chip that didn't connect to the programming socket. Thanks! JonArticle: 154979
Hi, Installation of 11.0Beta (the first complete download of Libero SoC 11.0) i= s ok and runs. When downloading and applying the SPA patch or SP1 patch, li= bero_bin exits with a missing symbol in a dynamic library. I note that in my installation a binary diff between the libero_bin of the = various patch levels does not indicate a change. There is, however, a chang= e in one of the dynamic libraries, libappipc.so, included with Libero SoC 1= 1.0. Most of the api changes were pure types, so I binary-patched the liber= o_bin file myself and managed to get Libero SoC SP1 to run a bit longer. In= the end I had to give up on a function which had had an extra argument add= ed in SP1. Microsemi seems to only support RHEL 5.4 and I use Debian Sid. I managed to= get Libero 10.1 and the initial 11.0Beta running, so it is not that it doe= sn't run on Debian. I think Microsemi has forgotten to include changes to l= ibero_bin in their SPA and SP1 patches, but before I trigger a support case= on an unsupported operating system, I wanted to see if anybody here has Li= bero SoC up and running on Linux. --=20 SvennArticle: 154980
The Raspberry Pi JTAG programmer: http://panteltje.com/panteltje/raspberri_pi/Article: 154981
Took the hassle to download a CentOS 5.6 image from virtualboxes.org and install Libero SoC 11Beta and upgrade to SP1 inside that virtualbox. First thing I noted was that 'patch' did not complain about an invalid RTP file when patching to SP1. Then I packed the whole Libero_v11Beta directory and transferred it to Debian. Works. Need to note that Libero SoC is very much hardwired to RHEL in some script files in Libero/bin and Synplify/bin, but it is possible to fix this in an editor. -- SvennArticle: 154982
On 03/14/2013 13:03, Jan Panteltje wrote: > The Raspberry Pi JTAG programmer: > http://panteltje.com/panteltje/raspberri_pi/ Neat. If one doesn't want to use the Pi as a JTAG adapter, other options exist. Like the GoodFET: http://goodfet.sourceforge.net/ HTH -- Torfinn Ingolfsen, NorwayArticle: 154983
On 2013-01-19 12:54, oguzyilmazlist@gmail.com wrote: > Hello, > > I am searching for a fpga accelerated ethernet card solution for facing tcp sessions before OS. The solution should complete > 3 way handshake before operating system/driver stage. This implies it should create SYN-ACK packets and wait for 3rd step ACK. > This implies it should keep a connection/session table. Generally, I am waiting high connection rate (1M conn per second for > 1 Gbps connection) and high number of live sessions. > > I would be grateful for any redirection. Sorry for bothering if this is the wrong community for the subject. > > Regards, > > Oguz > Have been looking at this problem for some time, but for 10 GbE. You will need FPGA Card. Looking at Bittware and Hightec-Global which both provide example designs and Linux Drivers. For offloading, we are looking at Fraunhofer, but there are others like PLDA, Intilog, Fiberblaze. Fraunhofer will release some special features which will be needed, but may not affect decisions for other applications. BR Ulf SamuelssonArticle: 154984
On 14/03/2013 12:56, Svenn Are Bjerkem wrote: > Took the hassle to download a CentOS 5.6 image from virtualboxes.org and install Libero SoC 11Beta and upgrade to SP1 inside that virtualbox. First thing I noted was that 'patch' did not complain about an invalid RTP file when patching to SP1. > > Then I packed the whole Libero_v11Beta directory and transferred it to Debian. > > Works. > > Need to note that Libero SoC is very much hardwired to RHEL in some script files in Libero/bin and Synplify/bin, but it is possible to fix this in an editor. > Interesting, that was the same method I used to get Precision installed on my Gentoo box. Many tools and updates later I gave up and like you installed CentOS. If you want to use EDA tools under Linux than you can save yourself a lot of hacking by using one of the Redhat clones. This is no guarantee everything will work fine, I had to yum libXext, libXtst, libXft and ncurses just to get the Modelsim DE installer to run under Centos 6.1 but at least the procedure was simple and all other tools (so far) installed without an issue. Thanks for the info, Hans www.ht-lab.comArticle: 154985
> I am searching for a fpga accelerated ethernet card solution for facing t= cp >sessions before OS. The solution should complete 3 way handshake before= operating >system/driver stage. This implies it should create SYN-ACK pack= ets and wait for >3rd step ACK. This implies it should keep a connection/se= ssion table. Generally, >I am waiting high connection rate (1M conn per sec= ond for 1 Gbps connection) and >high number of live sessions. DINI provides this: http://www.dinigroup.com/new/TOE.phpArticle: 154986
mike_la_jolla <mdini@dinigroup.com> wrote: >> I am searching for a fpga accelerated ethernet card solution for >> facing tcp sessions before OS. The solution should complete 3 way >> handshake before operating system/driver stage. This implies it >> should create SYN-ACK packets and wait for >3rd step ACK. This >> implies it should keep a connection/session table. Generally, I >> am waiting high connection rate (1M conn per second for 1 Gbps >> connection) and high number of live sessions. > > DINI provides this: http://www.dinigroup.com/new/TOE.php No, they require "setup/teardown of TCP sessions" to be handled by the CPU.Article: 154987
> No, they require "setup/teardown of TCP sessions" to be handled by the CPU. Sorry. You are correct. Your best bet would be PLDA or Intilop.Article: 154988
Dear All, Is there a tutorial for using Quartus II without the GUI? Ie. how to create a new project, how to configure PLL's, how to bind signals to physical pins etc? I have been writing Verilog code with my favourite editor already and I would like to get rid of the GUI system completely because I feel the schematic capture is not so good. It also produces lots of files and I have no idea of which files I should keep in CVS and which ones are just compile time junk.. Thanks! -jmArticle: 154989
Jukka Marin <jmarin@pyy.embedtronics.fi> writes: > Dear All, > > Is there a tutorial for using Quartus II without the GUI? Ie. how to create > a new project, how to configure PLL's, how to bind signals to physical pins > etc? I don't know of a tutorial but most project settings are in the qsf file, including device type and pin assignments. Qpf is presumably also needed although at least mine don't have much information in them. As for PLLs, I've done them in Megawizard Plug-In Manager and put all the generated files in a separate directory. Same thing with any IP blocks.Article: 154990
On 03/21/2013 09:48 AM, Jukka Marin wrote: > Dear All, > > Is there a tutorial for using Quartus II without the GUI? Ie. how to create > a new project, how to configure PLL's, how to bind signals to physical pins > etc? > > I have been writing Verilog code with my favourite editor already and I would > like to get rid of the GUI system completely because I feel the schematic > capture is not so good. It also produces lots of files and I have no idea > of which files I should keep in CVS and which ones are just compile time > junk.. > > Thanks! > > -jm > The files to keep are those that are put into the compressed file that is generated when you archive your project from the menu. OTOH, you may use the TCL shell to create projects, etc. A quick search gave http://extras.springer.com/2001/978-0-306-47635-8/an/an195.pdf PereArticle: 154991
Anssi Saari <as@sci.fi> writes: >> Is there a tutorial for using Quartus II without the GUI? Ie. how to create >> a new project, how to configure PLL's, how to bind signals to physical pins >> etc? Not exactly a tutorial but check out The Quartus Handbook: http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf Vol 2. Chapter 2 and 3 contains information about scripting. You can also download the individual chapters: http://www.altera.com/literature/hb/qts/qts_qii52002.pdf Then there is the Quartus II scripting reference manual: http://www.altera.com/literature/manual/TclScriptRefMnl.pdf //Petter -- .sig removed by request.Article: 154992
Jukka Marin <jmarin@pyy.embedtronics.fi> wrote: > I have been writing Verilog code with my favourite editor already and I would > like to get rid of the GUI system completely because I feel the schematic > capture is not so good. It also produces lots of files and I have no idea > of which files I should keep in CVS and which ones are just compile time > junk.. I don't see why you need to throw out the IDE just because you don't like the schematic capture... For a makefile example, try: $ quartus_sh --help=makefile Files you probably want in version control: *.qpf [project file] *.qsf [settings file] *.qsys [qsys project] *.sopc [sopc builder project] *.v [verilog] *.vhd [VHDL] *.sv [system verilog] *.bsf [schematic capture] *.sdc [timing constraints] *.cdf [programmer config] *.tcl [scripts for various tools - qsys, system console, quartus, etc] Possibly the contents of the ip/ directory [components for qsys] Not synthesis/ [output of qsys] Not db/ [build temporary files] Possibly *.qip [references to files in the sub-hierarchy] Quartus 12.1 is better at keeping the generated files (reports etc) separate from your design files. TheoArticle: 154993
(1) I need to prototype Arm A5 processor in Xilinx V7 2000 FPGA. A5 has AX= I bus and Xilinx supports DDR3 Controller+AXI bus using Core gen. Thus I c= an actually use the DRAM with A5 in FPGA. The thing is that in our actual = ASIC, we are using different DDR3/DDR4 memroy controller that has different= set of DRAM registers. From software development side I need to be able t= o support these registers in Xilinx. Is it possible to modify the Xilinx C= oregen generated Verilog DDR3 controller significantly? Or do I need to h= ave separate wrapper between the ARM core and DDR3 memory controller on AXI= bus? (2) Also linting tools like vavlog and vaelab may not be valid for FPGA. In= that case what are the RTL linting tools which we have to run for qualifyi= ng ASIC RTL for FPGA (3) I am thinking that the FPGA V72000 is big enough to support both the A5= , DDR3 memory controller and other devices such SPI, I2C and possibly PCIe.= I am not sure if I need to paritition this in multiple FPGAs. =20 (4) Is the Chipscope still the best way to get visibility into the design a= nd debug? Or is there a better solution? (5) If I am not concerned about performance, I am not sure how much time sh= ould I allocate for this type of task? Is it 3 month effort? I have done = some FPGA development using both Altera and Xilinx Prompt response is greatly appreciated.Article: 154994
I'm using Synplify and trying to infer some DSP designs into DSP48s. Somet= imes it works well, but it's sporadic. I'd like the DSP48s to be cascaded = using the ACOUT/ACIN dedicated paths, and sometimes this works, but in othe= r designs it puts the delay lines in fabric. It seems to be very sensitive= to the "syn_retiming" attribute on certain nets, even though this doesn't = seem to be related to retiming at all. I'm also doing convergent rounding = and want my "tie detector" to be pulled into the DSP48's PATTERNDETECT, whi= ch, again, works sometimes and sometimes doesn't, even in code written almo= st exactly the same in a different module. (Using VHDL.) And sometimes Sy= nplify will move all the registers around and put some in fabric. I'll hav= e A1, A2, B1, B2, M, and P registers, and Synplify will pull A1 into the fa= bric, A2 into A1, M into A2, and then leave out the M register. Is there a= ny good way to make it do what I want without instantiating DSP48s, which I= 'd rather avoid?Article: 154995
On Saturday, 19 January 2013 11:54:49 UTC, oguzyil...@gmail.com wrote: > Hello, >=20 >=20 >=20 > I am searching for a fpga accelerated ethernet card solution for facing t= cp sessions before OS. The solution should complete 3 way handshake before = operating system/driver stage. This implies it should create SYN-ACK packet= s and wait for 3rd step ACK. This implies it should keep a connection/sessi= on table. Generally, I am waiting high connection rate (1M conn per second = for 1 Gbps connection) and high number of live sessions. >=20 >=20 >=20 > I would be grateful for any redirection. Sorry for bothering if this is t= he wrong community for the subject. >=20 >=20 >=20 > Regards, >=20 >=20 >=20 > Oguz I would reccomend you to be very careful in choosing a TOE. I have worked for a company that in order to "save time to marked" used one= of these Off shield TOE... and I have never seen working correctly! good luck!Article: 154996
I tried building a small project in ISE 10.1 using the CoolRunner II CPLD XC2C128 and ran into a problem with pullups. I defined a few inputs with pullup in the UCF file, and the mapper complained about a conflict between keeper and pullup on the same pin. I had to set unused pins and inputs to default to pullup to get rid of the error, otherwise I just got the keeper and no pullup. it seems the ucf command for pullup isn't being obeyed. Is the CoolRunner II only able to have pullups if they are used on all (input) pins? Thanks, JonArticle: 154997
Jon Elson wrote: > I tried building a small project in ISE 10.1 using the > CoolRunner II CPLD XC2C128 and ran into a problem with pullups. > I defined a few inputs with pullup in the UCF file, and > the mapper complained about a conflict between keeper > and pullup on the same pin. I had to set unused pins > and inputs to default to pullup to get rid of the error, > otherwise I just got the keeper and no pullup. it seems > the ucf command for pullup isn't being obeyed. Is the > CoolRunner II only able to have pullups if they are used > on all (input) pins? Yup, that's it, now I remember seeing that in the data sheet, not very boldly described, either. The selection of keeper or pullup/pulldown is a GLOBAL option for all inputs. Well, at least what I saw was consistent with the docs. JonArticle: 154998
On 3/24/2013 12:50 PM, Jon Elson wrote: > Jon Elson wrote: > >> I tried building a small project in ISE 10.1 using the >> CoolRunner II CPLD XC2C128 and ran into a problem with pullups. >> I defined a few inputs with pullup in the UCF file, and >> the mapper complained about a conflict between keeper >> and pullup on the same pin. I had to set unused pins >> and inputs to default to pullup to get rid of the error, >> otherwise I just got the keeper and no pullup. it seems >> the ucf command for pullup isn't being obeyed. Is the >> CoolRunner II only able to have pullups if they are used >> on all (input) pins? > Yup, that's it, now I remember seeing that in the data sheet, not > very boldly described, either. The selection of keeper or > pullup/pulldown is a GLOBAL option for all inputs. > Well, at least what I saw was consistent with the docs. > > Jon > You can select whether you have any termination on a pin-by-pin basis, but for those pins that have termination, it must be the same. So in effect pullup vs. keeper vs. pulldown is global, but any of these vs. tristate is available on a pin-by-pin basis. -- GaborArticle: 154999
To just know a bit more what possibly went wrong, I installed Beta, SPA and= SP1 into separate directories. Then I binary-diffed the libero_bin files a= nd found that interface to the dynamic library libappipc.so had changed fro= m Beta to SPA. Since the difference in three of four cases were just intege= r arguments changing to bool arguments, I could replace the letter in hexed= it, and SPB would run up until creating the design. Then the fourth differe= nce would fail as the interface to the dynamic library had gotten one more = argument. I would not try to hack that in hexedit. (I had the sw SP1 runnin= g from CentOS anyway) I concluded that the RTPatch thing which Microsemi us= es to upgrade the java-driven original install failed when run on Debian. R= TPatch is a commercial binary patch app, and Microsemi is still using versi= on 6 while the company offers version 10. I tried to run RTpatch on command line to try to learn more, but without mu= ch documentation, I could not get any deeper into the problem. Installing v= irtualbox and CentOS VDI and then Libero SoC Sp1 on top of that, took less = time than I wasted on my investigations into direct installation and upgrad= e. A bigger problem is that FlashPro4 is not supported on Linux, but I guess t= hat is what we have virtualbox for. --=20 Svenn
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