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> > @Tim @Adam > then i need some help regarding my project > the help is that .... > we just encode telemetry or on the Other Hand > Packet telemetry encoder listed 8 thing .... > > The Packet Telemetry Encoder (PTME) VHDL model comprises several encoders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises the following: > * Telemetry Encoder (TME) > * Reed-Solomon Encoder (RSE) > * Turbo Encoder (TE) > * Pseudo-Randomiser (PSR) > * Non-Return-to-Zero Mark encoder (NRZ) > * Convolutional Encoder (CE) > * Split-Phase Level modulator (SP) > * Clock Divider (CD) > we encode just Telemetry encoder or > all of the other encoder > i'm confuse > Do you expect from me ( us ) answer to this question ? In my opinion it is lot of work if you going to implement all of them. Only RSE is big enough for you I think. AdamArticle: 156626
On Thursday, May 15, 2014 2:41:43 PM UTC+5, Adam G=F3rski wrote: > > >=20 > > @Tim @Adam >=20 > > then i need some help regarding my project >=20 > > the help is that .... >=20 > > we just encode telemetry or on the Other Hand >=20 > > Packet telemetry encoder listed 8 thing .... >=20 > > >=20 > > The Packet Telemetry Encoder (PTME) VHDL model comprises several encode= rs and modulators implementing the Consultative Committee for Space Data Sy= stems (CCSDS) recommendations and the European Space Agency (ESA) Procedure= s, Standards and Specifications (PSS) for telemetry and channel coding. Th= e Packet Telemetry Encoder (PTME) VHDL model comprises the following: >=20 > > * Telemetry Encoder (TME) >=20 > > * Reed-Solomon Encoder (RSE) >=20 > > * Turbo Encoder (TE) >=20 > > * Pseudo-Randomiser (PSR) >=20 > > * Non-Return-to-Zero Mark encoder (NRZ) >=20 > > * Convolutional Encoder (CE) >=20 > > * Split-Phase Level modulator (SP) >=20 > > * Clock Divider (CD) >=20 > > we encode just Telemetry encoder or >=20 > > all of the other encoder >=20 > > i'm confuse >=20 > > >=20 >=20 >=20 > Do you expect from me ( us ) answer to this question ? >=20 > In my opinion it is lot of work if you going to implement all of them. >=20 > Only RSE is big enough for you I think. >=20 >=20 >=20 > Adam @adam @tim you both are right ,,but something really interesting fact that you don't k= now . the fact is that my Supervisor is not command from these kinds of topic.... so after your some solid reason ...=20 here just one question is asked to u ... the question is.................. implement only one telemetry encoder=20 7OSI model layer i think only implement on telemetry encoder=20 and other encoder don't use 7OSI layer model because The second phase will be the implementation of all layers of standard on FP= GA using the VHDL language. Each layer will be implemented as a separate mo= dule and simulation will be performed. what can you suggest for me ???Please just Technical help for both of youArticle: 156627
Dear Saqib, > > > then i need some help regarding my project Hans (Tiggeler) has gave you an excellent overview of what exactly is avail= able regarding CCSDS Telemetry Encoder IP. I am interested in helping you (I provide paid support). So if this is an academic exercise, and plagiarism is not tolerated o_O the= n someone has to start from the specs (either directly you or the contracte= e).=20 Do you have a deadline and budget to see if this is feasible?=20 Best regards Nikolaos Kavvadias http://www.nkavvadias.com >=20 > >=20 >=20 > > > the help is that .... >=20 > >=20 >=20 > > > we just encode telemetry or on the Other Hand >=20 > >=20 >=20 > > > Packet telemetry encoder listed 8 thing .... >=20 > >=20 >=20 > > > >=20 > >=20 >=20 > > > The Packet Telemetry Encoder (PTME) VHDL model comprises several enco= ders and modulators implementing the Consultative Committee for Space Data = Systems (CCSDS) recommendations and the European Space Agency (ESA) Procedu= res, Standards and Specifications (PSS) for telemetry and channel coding. = The Packet Telemetry Encoder (PTME) VHDL model comprises the following: >=20 > >=20 >=20 > > > * Telemetry Encoder (TME) >=20 > >=20 >=20 > > > * Reed-Solomon Encoder (RSE) >=20 > >=20 >=20 > > > * Turbo Encoder (TE) >=20 > >=20 >=20 > > > * Pseudo-Randomiser (PSR) >=20 > >=20 >=20 > > > * Non-Return-to-Zero Mark encoder (NRZ) >=20 > >=20 >=20 > > > * Convolutional Encoder (CE) >=20 > >=20 >=20 > > > * Split-Phase Level modulator (SP) >=20 > >=20 >=20 > > > * Clock Divider (CD) >=20 > >=20 >=20 > > > we encode just Telemetry encoder or >=20 > >=20 >=20 > > > all of the other encoder >=20 > >=20 >=20 > > > i'm confuse >=20 > >=20 >=20 > > > >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Do you expect from me ( us ) answer to this question ? >=20 > >=20 >=20 > > In my opinion it is lot of work if you going to implement all of them. >=20 > >=20 >=20 > > Only RSE is big enough for you I think. >=20 > >=20 >=20 > >=20 >=20 > >=20 >=20 > > Adam >=20 >=20 >=20 >=20 >=20 >=20 >=20 > @adam @tim >=20 > you both are right ,,but something really interesting fact that you don't= know . >=20 > the fact is that my Supervisor is not command from these kinds of topic..= .. >=20 >=20 >=20 > so after your some solid reason ...=20 >=20 > here just one question is asked to u ... >=20 > the question is.................. >=20 > implement only one telemetry encoder=20 >=20 >=20 >=20 >=20 >=20 > 7OSI model layer i think only implement on telemetry encoder=20 >=20 > and other encoder don't use 7OSI layer model because >=20 > The second phase will be the implementation of all layers of standard on = FPGA using the VHDL language. Each layer will be implemented as a separate = module and simulation will be performed. >=20 >=20 >=20 > what can you suggest for me ???Please just Technical help for both of yo= uArticle: 156628
@Nikolaos Kavvadias on 22may inital +progressive seminar going to held an and on 20june final presenentation due to lack of time that's why i come on that platform otherwise i made myself this projectArticle: 156629
> @Nikolaos Kavvadias > > on 22may inital +progressive seminar going to held an > > and on 20june final presenentation > > due to lack of time that's why i come on that platform > > otherwise i made myself this project > > Are you kidding? AdamArticle: 156630
@adam i'm not kidding thats why i'm also so sad for this situationArticle: 156631
>> this is my univ.level project Look, if your supervisor cannot help you, go find a student advisor. Something has obviously gone wrong. The university pays those guys to help you fix it. Your university will be unhappy (mild understatement) if they find you hiring consultants on your own initiative. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156632
@mnentwig our univ. can't paid for our project . they only provide the equipment ..if only they r available in our labzzArticle: 156633
Saqib Saqi wrote:
> @mnentwig
> our univ. can't paid for our project .
> they only provide the equipment ..if only they r available in our labzz
There are many here who will help you but you need to start by being an
engineer.
Lets start by getting a design document together. A simple document of
project goals and solutions.
Start with a simple description of goals
Add to it some lists to get started.
1) What information you need to do this project.
2) What information do you have?
3) Where can you find the rest of the information?
possible answers
- It is a standard
- It is available by a google search.
- Don't know. (This group may be able to give you hints if you ask)
Start the engineering
What resources are needed.
Time available to execute one cycle
Code size constraints
Data size constraints
Tools needed to do the implementation
How are you going to test it
What is the critical part that everything else depends on
Sketch out the all of the pieces needed for a solution
Design documents can be any convenient form.
The purpose of design documents is to focus your thinking.
I use either a spread sheet as an electronic blackboard or text/graphic
editor.
There are no short cuts.
If you ask an engineering question, this group will help.
The solution needs to be yours
w..
Article: 156634On 14/5/2014 10:15 PM, glen herrmannsfeldt wrote: > Ang Zhi Ping <angzhiping@gmail.com> wrote: Snip > If you drive them Z, the outputs should tristate, if X then they > will be either 0 or 1, whatever the synthesis finds easier. According to ModelSim, they appear as X. I guess synthesis tools defaults unassigned logic to 'X'. They are definitely not driven to 'Z'. > What to you mean by "unpredictable"? That these 'X' values may propagate to other parts of the hardware logic on the FPGA. --- This email is free from viruses and malware because avast! Antivirus protection is active. http://www.avast.comArticle: 156635
On 5/16/2014 10:13 PM, Ang Zhi Ping wrote: > On 14/5/2014 10:15 PM, glen herrmannsfeldt wrote: >> Ang Zhi Ping <angzhiping@gmail.com> wrote: > > Snip > >> If you drive them Z, the outputs should tristate, if X then they >> will be either 0 or 1, whatever the synthesis finds easier. > > According to ModelSim, they appear as X. I guess synthesis tools > defaults unassigned logic to 'X'. They are definitely not driven to 'Z'. Yes, you need to drive all inputs to a known value to get meaningful behavior. You seem to be talking about outputs of a module being not driven. I don't understand that. How can the code not drive the output? If you specify output values only for certain input values, the output will be held to the previous values for the undefined input conditions which is also known as a memory element or a flip-flop. >> What to you mean by "unpredictable"? > > That these 'X' values may propagate to other parts of the hardware logic > on the FPGA. Yes, that is the point of the value 'X' or 'U'. It usually indicates and error and will propagate through the design to all affected parts. The simulation value 'X' won't alter the logic inferred. That is defined by your code. But static inputs are often removed from the design because they aren't needed to define the logic. '0' AND anything is always a '0', so the AND gate driven by a '0' is removed. Logic driven by an 'X' often produces an 'X' regardless of the other inputs, so no logic needs to be produced in that case, just an 'X' generator. Can you explain why you don't define an output value for some "modes" and not others? What does "mode" correspond to in your design? Is the mode defined by some of the logic inputs or is this a parameter to the code that defines the type of module you intend to be generated? There might be a way to do what you are looking for, but I can't say because I don't understand what you are doing. -- RickArticle: 156636
On Friday, May 16, 2014 10:13:35 PM UTC-4, Ang Zhi Ping wrote:
>=20
> According to ModelSim, they appear as X. I guess synthesis tools
> defaults unassigned logic to 'X'. They are definitely not driven to 'Z'.
>=20
No. As I stated in my first post, those outputs will be driven to 0 by Qua=
rtus. Simply check the synthesis report. That assumes that those undriven=
outputs are connected to something. An unconnected output will not be syn=
thesized at all since it will be optimized out.
>=20
> > What to you mean by "unpredictable"?
>=20
> That these 'X' values may propagate to other parts of the hardware logic
> on the FPGA.
>=20
That's what you should expect. If you have an output that has no logic beh=
ind it then that output will get assigned an unknown ('U') and that unknown=
will propagate downstream.
Kevin Jennings
Article: 156637On 17/5/2014 5:30 PM, rickman wrote: > On 5/16/2014 10:13 PM, Ang Zhi Ping wrote: >> On 14/5/2014 10:15 PM, glen herrmannsfeldt wrote: >>> Ang Zhi Ping <angzhiping@gmail.com> wrote: >> >> Snip >> >>> If you drive them Z, the outputs should tristate, if X then they >>> will be either 0 or 1, whatever the synthesis finds easier. >> >> According to ModelSim, they appear as X. I guess synthesis tools >> defaults unassigned logic to 'X'. They are definitely not driven to 'Z'. > > Yes, you need to drive all inputs to a known value to get meaningful > behavior. You seem to be talking about outputs of a module being not > driven. I don't understand that. How can the code not drive the > output? If you specify output values only for certain input values, the > output will be held to the previous values for the undefined input > conditions which is also known as a memory element or a flip-flop. Apparently undriven outputs is legal syntax in Verilog. Quartus emit a warning on undriven ports though. >>> What to you mean by "unpredictable"? >> >> That these 'X' values may propagate to other parts of the hardware logic >> on the FPGA. > > Yes, that is the point of the value 'X' or 'U'. It usually indicates > and error and will propagate through the design to all affected parts. > The simulation value 'X' won't alter the logic inferred. That is > defined by your code. But static inputs are often removed from the > design because they aren't needed to define the logic. '0' AND anything > is always a '0', so the AND gate driven by a '0' is removed. Logic > driven by an 'X' often produces an 'X' regardless of the other inputs, > so no logic needs to be produced in that case, just an 'X' generator. > > Can you explain why you don't define an output value for some "modes" > and not others? What does "mode" correspond to in your design? Is the > mode defined by some of the logic inputs or is this a parameter to the > code that defines the type of module you intend to be generated? I have a datapath which does not need to read/write to some BRAMs for certain modes, whereas it needs for others. The mode is determined by an input port, and not a parameter. > There might be a way to do what you are looking for, but I can't say > because I don't understand what you are doing. > --- This email is free from viruses and malware because avast! Antivirus protection is active. http://www.avast.comArticle: 156638
On 17/5/2014 7:07 PM, KJ wrote:
> On Friday, May 16, 2014 10:13:35 PM UTC-4, Ang Zhi Ping wrote:
>>
>> According to ModelSim, they appear as X. I guess synthesis tools
>> defaults unassigned logic to 'X'. They are definitely not driven to 'Z'.
>>
>
> No. As I stated in my first post, those outputs will be driven to 0 by Quartus. Simply check the synthesis report. That assumes that those undriven outputs are connected to something. An unconnected output will not be synthesized at all since it will be optimized out.
You're right.
>>
>>> What to you mean by "unpredictable"?
>>
>> That these 'X' values may propagate to other parts of the hardware logic
>> on the FPGA.
>>
>
> That's what you should expect. If you have an output that has no logic behind it then that output will get assigned an unknown ('U') and that unknown will propagate downstream.
>
> Kevin Jennings
>
---
This email is free from viruses and malware because avast! Antivirus protection is active.
http://www.avast.com
Article: 156639On 5/17/2014 8:29 AM, Ang Zhi Ping wrote: > On 17/5/2014 5:30 PM, rickman wrote: >> On 5/16/2014 10:13 PM, Ang Zhi Ping wrote: >>> On 14/5/2014 10:15 PM, glen herrmannsfeldt wrote: >>>> Ang Zhi Ping <angzhiping@gmail.com> wrote: >>> >>> Snip >>> >>>> If you drive them Z, the outputs should tristate, if X then they >>>> will be either 0 or 1, whatever the synthesis finds easier. >>> >>> According to ModelSim, they appear as X. I guess synthesis tools >>> defaults unassigned logic to 'X'. They are definitely not driven to 'Z'. >> >> Yes, you need to drive all inputs to a known value to get meaningful >> behavior. You seem to be talking about outputs of a module being not >> driven. I don't understand that. How can the code not drive the >> output? If you specify output values only for certain input values, the >> output will be held to the previous values for the undefined input >> conditions which is also known as a memory element or a flip-flop. > > Apparently undriven outputs is legal syntax in Verilog. Quartus emit a > warning on undriven ports though. No one said it was illegal syntax. It is not valid semantics for describing synthesizable hardware. >>>> What to you mean by "unpredictable"? >>> >>> That these 'X' values may propagate to other parts of the hardware logic >>> on the FPGA. >> >> Yes, that is the point of the value 'X' or 'U'. It usually indicates >> and error and will propagate through the design to all affected parts. >> The simulation value 'X' won't alter the logic inferred. That is >> defined by your code. But static inputs are often removed from the >> design because they aren't needed to define the logic. '0' AND anything >> is always a '0', so the AND gate driven by a '0' is removed. Logic >> driven by an 'X' often produces an 'X' regardless of the other inputs, >> so no logic needs to be produced in that case, just an 'X' generator. >> >> Can you explain why you don't define an output value for some "modes" >> and not others? What does "mode" correspond to in your design? Is the >> mode defined by some of the logic inputs or is this a parameter to the >> code that defines the type of module you intend to be generated? > > I have a datapath which does not need to read/write to some BRAMs for > certain modes, whereas it needs for others. > > The mode is determined by an input port, and not a parameter. Here is your fallacy. If the mode is determined by an input port, the hardware can't change between different modes. You are thinking in terms of the software without understanding what hardware will be produced. Ok, so what *does* the data path need to do? Describe exactly what it does without disconnecting things. To be honest, I'm not sure I understand your problem. In all the time I have designed logic, I have never considered a situation where I didn't define an output. I think you could look at the problem in a better way, but since I don't know your problem, it is hard for me to say. -- RickArticle: 156640
Hello sirs, I'm working on this problem for some days, and I'll be grateful if anyone c= ould help. I have a fpga cyclone II design and I need analyze its power consumption. My problem is: In these results of power analysis by the powerplay analyzer ************************************************************ Total Thermal Power Dissipation --------288.49 mW Core Dynamic Thermal Power Dissipation 23.05 mW Core Static Thermal Power Dissipation 219.88 mW <------ here! I/O Thermal Power Dissipation --------45.56 mW Power Estimation Confidence High: user provided sufficient toggle rate data ************************************************************* the Core static thermal power dissipation is very high comparing with the o= ther rates. And, by what I know, that occur because the fpga components whi= ch I'm not using at the design are consuming power. So, I need to know if there is any way to reduce this dissipation. Maybe di= sabling these components or elaborating better my design. I'm searching pll stuff and clock managements workarounds, but I'm not sure= if this is the correct way to solve my problem. Thanks by your attention. Pedro L=E1zaro. My environment. Softwares I'm using in my problem: For synthesis: Quartus II 9.1 For the power analysis: PowerPlay Power Analyzer tool in Quartus For simulation at gate level: Modelsim-altera 10.0c SO: Ubuntu 12.04Article: 156641
On Monday, May 19, 2014 8:29:25 AM UTC+3, Pedro Lazaro wrote: > Hello sirs, >=20 > I'm working on this problem for some days, and I'll be grateful if anyone= could help. >=20 > I have a fpga cyclone II design and I need analyze its power consumption. >=20 > My problem is: > In these results of power analysis by the powerplay analyzer >=20 > ************************************************************ >=20 > Total Thermal Power Dissipation --------288.49 mW >=20 > Core Dynamic Thermal Power Dissipation 23.05 mW >=20 > Core Static Thermal Power Dissipation 219.88 mW <------ here! >=20 > I/O Thermal Power Dissipation --------45.56 mW >=20 > Power Estimation Confidence High: user provided sufficient toggle rate da= ta >=20 > ************************************************************* >=20 > the Core static thermal power dissipation is very high comparing with the= other rates. And, by what I know, that occur because the fpga components w= hich I'm not using at the design are consuming power. >=20 >=20 >=20 > So, I need to know if there is any way to reduce this dissipation. Maybe = disabling these components or elaborating better my design. >=20 >=20 >=20 > I'm searching pll stuff and clock managements workarounds, but I'm not su= re if this is the correct way to solve my problem. >=20 >=20 >=20 > Thanks by your attention. >=20 >=20 >=20 > Pedro L=E1zaro. >=20 >=20 >=20 >=20 >=20 > My environment. >=20 > Softwares I'm using in my problem: >=20 > For synthesis: Quartus II 9.1 >=20 > For the power analysis: PowerPlay Power Analyzer tool in Quartus >=20 > For simulation at gate level: Modelsim-altera 10.0c >=20 > SO: Ubuntu 12.04 It looks like you (or your predecessors, or your boss) had chosen wrong FPG= A device. Low dynamic power indicates that device does virtually nothing. So, it almo= st certainly was possible to fit your task into much smaller device, e.g. E= P2C20 or even EP2C5 instead of big device (what is it, EP2C70 ?) that you a= re using now. As to your question, after device was chosen, very little could be done. Th= e best you can do is to keep it at the lowest possible temperature - static= power consumption strongly depends on the temperature. Also there is a hope that Altera power estimator is to pessimistic.Article: 156642
Is there any legal way to lower the supply voltage? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156643
On 5/19/2014 1:29 AM, Pedro Lazaro wrote: > Hello sirs, > > I'm working on this problem for some days, and I'll be grateful if anyone could help. > > I have a fpga cyclone II design and I need analyze its power consumption. > > My problem is: > In these results of power analysis by the powerplay analyzer > ************************************************************ > Total Thermal Power Dissipation --------288.49 mW > Core Dynamic Thermal Power Dissipation 23.05 mW > Core Static Thermal Power Dissipation 219.88 mW <------ here! > I/O Thermal Power Dissipation --------45.56 mW > Power Estimation Confidence High: user provided sufficient toggle rate data > ************************************************************* > the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power. > > So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design. > > I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem. > > Thanks by your attention. > > Pedro Lázaro. > > > My environment. > Softwares I'm using in my problem: > For synthesis: Quartus II 9.1 > For the power analysis: PowerPlay Power Analyzer tool in Quartus > For simulation at gate level: Modelsim-altera 10.0c > SO: Ubuntu 12.04 I assume by now you know that the static power of an FPGA is not a function of your design, but rather of the chip. To lower the static current you need to change chips. Lattice makes the iCE40 devices with static current in the 100 uA range. These are not large parts, but hold a fair amount of logic. They also have a non-volatile configuration storage if needed. Lattice also makes other devices that are low on power consumption although not as low as the iCE40. Check out the XO2 and the XP2 lines. -- RickArticle: 156644
rickman <gnuarm@gmail.com> wrote: > On 5/19/2014 1:29 AM, Pedro Lazaro wrote: >> Hello sirs, >> >> I'm working on this problem for some days, and I'll be grateful if anyone could help. >> >> I have a fpga cyclone II design and I need analyze its power consumption. >> >> My problem is: >> In these results of power analysis by the powerplay analyzer >> ************************************************************ >> Total Thermal Power Dissipation --------288.49 mW >> Core Dynamic Thermal Power Dissipation 23.05 mW >> Core Static Thermal Power Dissipation 219.88 mW <------ here! >> I/O Thermal Power Dissipation --------45.56 mW >> Power Estimation Confidence High: user provided sufficient toggle rate data >> ************************************************************* >> the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power. >> >> So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design. >> >> I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem. >> >> Thanks by your attention. >> >> Pedro L?zaro. >> >> >> My environment. >> Softwares I'm using in my problem: >> For synthesis: Quartus II 9.1 >> For the power analysis: PowerPlay Power Analyzer tool in Quartus >> For simulation at gate level: Modelsim-altera 10.0c >> SO: Ubuntu 12.04 > > I assume by now you know that the static power of an FPGA is not a > function of your design, but rather of the chip. To lower the static > current you need to change chips. Lattice makes the iCE40 devices with > static current in the 100 uA range. These are not large parts, but hold > a fair amount of logic. They also have a non-volatile configuration > storage if needed. Lattice also makes other devices that are low on > power consumption although not as low as the iCE40. Check out the XO2 > and the XP2 lines. Well, Lattice XP2 is a neat chip indeed, but it doesn't really fall into the "low static power consumption" category. MarkoArticle: 156645
Hi everybody, I'm a beginner in FPGA and I need your help. I'm working with EDK 12.4 and ML507 VIRTEX5 board. My goal is to connect the MBLite opencore processor to the Xilinx Microblaze. The problem is that MBLite support only Wishbone bus as interface or the Microblaze can support FSL and PLB Bus. In this situation, the two softcores processors don't have the same bus support. I want to know if there is a way to interface the MBLite with Microblaze? Thanks in advance --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156646
Hi I have just gotten a custom FPGA board in house and I am having trouble
programming it.
The FPGA I am using the Actel(Microsemi) Igloo AGL250V2-FGG1441
There is a 10 pin JTAG header on the board.
And I am using Microsemi's FlashPro3 to program it.
The header of the FlashPro3 is 12 pins. There is a extra pin called
VJTAGENB - that is used for IGLOO nano devices so I have left that pin
unconnected.
When I try and program the device with FlashPro I get the following error
messages:
Error: programmer '71917' : Signal Integrity Failure
Integrity Check Pattern Not Found.
Integrity Check Pattern :
550FAAF000FF0000FFFF
IrScan Error.
TDO stuck at 0
Chain Analysis Failed.
Error: programmer '71917' : Data Bit length : 8272
Error: programmer '71917' : Compare Data : 000108080008649......
Error: programmer '71917' : Scan Chain FAILED.
I have tried two board and they get the same error. I have also scoped the
JTAG lines and they look the same of two board. The trst seems to stay low
and tms seems to switch up and down at higher fequecy then tck before
settling on low. Not sure how to post the scope pictures here. Let me know
if you want to see them or any of info I forgot to add.
The igloo app note, says that this error could mean by a broken td0 net,
are there any other possible reasons.
---------------------------------------
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Article: 156647On 5/22/2014 1:54 PM, Marko Zec wrote: > rickman <gnuarm@gmail.com> wrote: >> On 5/19/2014 1:29 AM, Pedro Lazaro wrote: >>> Hello sirs, >>> >>> I'm working on this problem for some days, and I'll be grateful if anyone could help. >>> >>> I have a fpga cyclone II design and I need analyze its power consumption. >>> >>> My problem is: >>> In these results of power analysis by the powerplay analyzer >>> ************************************************************ >>> Total Thermal Power Dissipation --------288.49 mW >>> Core Dynamic Thermal Power Dissipation 23.05 mW >>> Core Static Thermal Power Dissipation 219.88 mW <------ here! >>> I/O Thermal Power Dissipation --------45.56 mW >>> Power Estimation Confidence High: user provided sufficient toggle rate data >>> ************************************************************* >>> the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power. >>> >>> So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design. >>> >>> I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem. >>> >>> Thanks by your attention. >>> >>> Pedro L?zaro. >>> >>> >>> My environment. >>> Softwares I'm using in my problem: >>> For synthesis: Quartus II 9.1 >>> For the power analysis: PowerPlay Power Analyzer tool in Quartus >>> For simulation at gate level: Modelsim-altera 10.0c >>> SO: Ubuntu 12.04 >> >> I assume by now you know that the static power of an FPGA is not a >> function of your design, but rather of the chip. To lower the static >> current you need to change chips. Lattice makes the iCE40 devices with >> static current in the 100 uA range. These are not large parts, but hold >> a fair amount of logic. They also have a non-volatile configuration >> storage if needed. Lattice also makes other devices that are low on >> power consumption although not as low as the iCE40. Check out the XO2 >> and the XP2 lines. > > Well, Lattice XP2 is a neat chip indeed, but it doesn't really fall > into the "low static power consumption" category. Yeah, sorry, I forgot. It is the XO2 they are pushing for that along with the iCE40 line. -- RickArticle: 156648
In article <wO6dndAmYvIb3uPOnZ2dnUVZ_oydnZ2d@giganews.com>, makni <99260@embeddedrelated> wrote: > >I'm a beginner in FPGA and I need your help. >I'm working with EDK 12.4 and ML507 VIRTEX5 board. My goal is to connect >the MBLite opencore processor to the Xilinx Microblaze. The problem is that >MBLite support only Wishbone bus as interface or the Microblaze can support >FSL and PLB Bus. In this situation, the two softcores processors don't have >the same bus support. >I want to know if there is a way to interface the MBLite with Microblaze? You'll have to give a few more details. Just what are you trying to do? Perusing the opencores website, I see that the MBlite is just an open source version of the Microblaze itself. It's probably not identical but close enough the the Xilinx Microblaze. Looks like whomever created it wanted a mblaze in Altera FPGAs. Now, you're basically trying to put two microblazes on an Xilinx board? What's being shared between the two microblazes? Memory? Peripherals? Just a bus bridge on either one of the buses to the other one would work. Details such has which bus, how much bandwidth, latency, etc, all depend on what you're tryin to do. --MarkArticle: 156649
On 5/22/2014 2:45 PM, elenappli wrote: > Hi I have just gotten a custom FPGA board in house and I am having trouble > programming it. > The FPGA I am using the Actel(Microsemi) Igloo AGL250V2-FGG1441 > There is a 10 pin JTAG header on the board. > And I am using Microsemi's FlashPro3 to program it. > The header of the FlashPro3 is 12 pins. There is a extra pin called > VJTAGENB - that is used for IGLOO nano devices so I have left that pin > unconnected. > When I try and program the device with FlashPro I get the following error > messages: > Error: programmer '71917' : Signal Integrity Failure > Integrity Check Pattern Not Found. > Integrity Check Pattern : > 550FAAF000FF0000FFFF > IrScan Error. > TDO stuck at 0 > Chain Analysis Failed. > Error: programmer '71917' : Data Bit length : 8272 > Error: programmer '71917' : Compare Data : 000108080008649...... > Error: programmer '71917' : Scan Chain FAILED. > > I have tried two board and they get the same error. I have also scoped the > JTAG lines and they look the same of two board. The trst seems to stay low > and tms seems to switch up and down at higher fequecy then tck before > settling on low. Not sure how to post the scope pictures here. Let me know > if you want to see them or any of info I forgot to add. > > The igloo app note, says that this error could mean by a broken td0 net, > are there any other possible reasons. I think you mean a broken tdo net. The point is the TDO signal is not going to the 1 state at the JTAG interface. It could be a TDO failure or any of the other JTAG signals. Can you verify connectivity from the JTAG connector to the FPGA pins? Do you have all the right power supply voltages on the FPGA pins including the I/O supply voltages? JTAG should take priority over all other control pins to the FPGA so the configuration interface signals shouldn't matter, just the JTAG pins. -- Rick
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