Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi everybody, I'am working on the massively parallel processing on chip (MPPSoC)on ML507 virtex5 board. I'm looking for an open source softcore processor which I can interface it to Microblaze processor (for example: in my design i need a master processor which is the xilinx microblaze and 4 slave opensource processor which are connected to Microblaze). I found a three Microblaze clones(aeMB, MB Lite and OpenFire) but I don't know how to integrate them in EDK, If there is someone who can guide me to know what's the suitable opencore that can be implemented into EDK and connected to Microblaze. Thanks in advance. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 156476
Hi Makni, makni <99260@embeddedrelated> wrote: [] > I found a three Microblaze clones(aeMB, MB Lite and OpenFire) but I don't > know how to integrate them in EDK, If there is someone who can guide me to > know what's the suitable opencore that can be implemented into EDK and > connected to Microblaze. I'm not familiar with EDK, but MBlite has a WishBone wrapper. It shouldn't be that difficult to integrate it within your SOC. Out of curiosity, why using the Microblaze when you can use the MBlite? IIRC only few instructions are not implemented in the MBlite version. Morevoer the processor is highly configurable with additional hardware operations (hard multiplier and hard barrel shifter). We are currently working on adding an fpu to that core, but it is still unclear what will be the license (sigh!). AlArticle: 156477
hi i need viterbi decoder code for my project where convolutional encoder is used for encoding please if possible can you give some websites regard this. thank youArticle: 156478
On Thursday, April 3, 2014 5:57:01 PM UTC+1, wza...@gmail.com wrote: > > As the core is supposed to be used in an Open Source project, I'd like to avoid using the 10-Gigabit Ethernet PCS/PMA available from Xilinx. If you're doing 10G Ethernet and open sourcing it, please send us a link to your OS project. Sounds interesting, thanks. RupertArticle: 156479
Hi everyone, does anyone out there know a group specialized on systemc? I'm interested in tlm modeling and platform virtualization. Thanks in advance, Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 156480
On 09/04/2014 14:00, alb wrote: > Hi everyone, > > does anyone out there know a group specialized on systemc? I'm > interested in tlm modeling and platform virtualization. > > Thanks in advance, > > Al > Hi Al, http://forums.accellera.org/forum/14-systemc-tlm-transaction-level-modeling/ You can sign up on the main page, http://forums.accellera.org/ Regards, Hans. www.ht-lab.comArticle: 156481
On Wed, 09 Apr 2014 16:59:17 +1000, Chris Jones <lugnut808@spam.yahoo.com> wrote: >On 09/04/2014 03:25, John Larkin wrote: >> >> >> I got a spreadsheet from Altera that lists the on-chip power supply >> bypass caps on an Arria II GX95 FPGA. I was kind of shocked to see 32 >> listed capacitors, most around 1 nf, but a Vcc_core (0.9 volt) cap of >> 501 nF. I was told that these caps are on-chip, not in-package. >> >> Is that possible? 501 nF on an FPGA chip? >> >> > >Sounds quite likely. The original DEC Alpha CPU had about 100nF on die, >and that was in the 90s. Decoupling capacitors normally use gate oxide >as the dielectric, so on more modern processes the capacitance could be >greater. They might not use the thinnest gate oxide for the capacitors >these days as the leakage current per area starts to get quite large >with very low voltage transistors. Apparently it is done. There are patents for paving over the top of a chip with power distribution metalization, dielectric, and ground. The numbers make sense. I'd just never heard of this before. It's mentioned in an Altera appnote. This is great, and largely negates their own silly guidelines for on-pcb bypassing, which we routinely ignored anyhow. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentationArticle: 156482
Hi everyone, how can you perform a 'check constraints' run in batch mode with synplify pro? Background: I'm trying to slowly moving my entire flow remotely and in batch mode in order to support continuous integration. I'd like to separate the constraint check phase from the mapping phase in order to make sure constraints are properly 'spelled' since a mapping phase would require ~20minutes and it would be a shame to realize only at the end of it that one of them had a ',' instead of '.'! Any pointer is appreciated, Al -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 156483
Hi Hans, In news.groups.questions HT-Lab <hans64@htminuslab.com> wrote: [] >> does anyone out there know a group specialized on systemc? I'm >> interested in tlm modeling and platform virtualization. [] > http://forums.accellera.org/forum/14-systemc-tlm-transaction-level-modeling/ thanks for the pointer. I actually knew about that forum, but I kind of dislike web-forums in general and I'd prefer to read and post articles through my newsreader rather than a clumsy web-interface. I also do not like the idea to splitting communities and I may imagine the accellera forum would be the best choice indeed... Maybe I should try to look for an http-to-nntp bridge instead. AlArticle: 156484
On 09/04/2014 16:03, alb wrote: > Hi Hans, > In news.groups.questions HT-Lab <hans64@htminuslab.com> wrote: > [] >>> does anyone out there know a group specialized on systemc? I'm >>> interested in tlm modeling and platform virtualization. > [] >> http://forums.accellera.org/forum/14-systemc-tlm-transaction-level-modeling/ > > thanks for the pointer. I actually knew about that forum, but I kind of > dislike web-forums in general and I'd prefer to read and post articles > through my newsreader rather than a clumsy web-interface. > > I also do not like the idea to splitting communities I fully agree with you, unfortunately setting up say comp.lang.systemc is a lengthy process. Having said that, the SystemC forums are actually quite good and this is all thanks to a handfull of experts who answers all questions. Regards, Hans. www.ht-lab.com and I may imagine > the accellera forum would be the best choice indeed... Maybe I should > try to look for an http-to-nntp bridge instead. > > Al >Article: 156485
In comp.arch.fpga o pere o <me@somewhere.net> wrote: (snip) > Just out of curiosity, which tools exist/do you use to go from > verilog/VHDL to layout? If you are interested in which tools, you might be interested in: https://class.coursera.org/vlsicad-002 Which teaches how some of the tools work, though it is a little late to start now if you want a certificate. -- glenArticle: 156486
On Friday, March 28, 2014 11:03:46 AM UTC+5:30, ahmad...@gmail.com wrote: > Still gives out error if you have clock for other signals.. in other modules.. > > > > "Pack:1107 - Unable to combine the following symbols into a single IOB" > > > > I tried to set the "clock buffers" to just 1 so that It can contain the 1st clock in Project and It worked for Me! ERROR:MapLib:93 - Illegal LOC on IPAD symbol "autman" or BUFGP symbol "autman_BUFGP" (output signal=autman_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site. same wrrer how to solve???? wher is this tabArticle: 156487
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "autman" or BUFGP symbol "autman_BUFGP" (output signal=autman_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site. same error how to solve this problem i am using 9.1 ver.Article: 156488
Hi Hans, In comp.arch.fpga HT-Lab <hans64@htminuslab.com> wrote: [] >> thanks for the pointer. I actually knew about that forum, but I kind of >> dislike web-forums in general and I'd prefer to read and post articles >> through my newsreader rather than a clumsy web-interface. >> >> I also do not like the idea to splitting communities > > I fully agree with you, unfortunately setting up say comp.lang.systemc > is a lengthy process. > I think the process is not so long and I can even volunteer to write up an RFD but the real point is whether there will be enough traffic to justify a new group. I guess I'll need to show up on those forums first and get a feeling whether a group will be useful or not. I know of certain forums which map one to one newsgroup content in order to allow user to choose their favourite interface, without breaking the community, but this will require some efforts on the accellera side. > Having said that, the SystemC forums are actually quite good and this is > all thanks to a handfull of experts who answers all questions. The added value of having a newsgroup is the possibility to cross-post efficiently especially when you want two languages to interact. I'm considering the possibility to have my model written in SystemC while the testbench written in vhdl, leveraging the benefits of the OSVVM library. It might be that systemc forums are equally followed by lots of vhdl experts, but IMHO the possibility to merge the two world on usenet greatly improves the quality of the thread. AlArticle: 156489
sagarmemane4@gmail.com wrote: > On Friday, March 28, 2014 11:03:46 AM UTC+5:30, ahmad...@gmail.com wrote: >> Still gives out error if you have clock for other signals.. in other modules.. >> >> >> >> "Pack:1107 - Unable to combine the following symbols into a single IOB" >> >> >> >> I tried to set the "clock buffers" to just 1 so that It can contain the 1st clock in Project and It worked for Me! > > ERROR:MapLib:93 - Illegal LOC on IPAD symbol "autman" or BUFGP symbol > "autman_BUFGP" (output signal=autman_BUFGP), IPAD-IBUFG should only be LOCed > to GCLKIOB site. > > same wrrer > how to solve???? > > wher is this tab My first guess is that you have unwittingly created latches in your design, because "autman" doesn't sound like the typical signal name for a clock. Check your synthesis warnings for latches. On the other hand, if "autman" is actually a clock signal, then the error message is pretty explicit in saying it should be assigned to a global clock-capable pin. If you already have a board layout and want to try to reduce the error to a warning, you could add this to your .ucf file: NET "autman" CLOCK_DEDICATED_ROUTE = FALSE; On the other hand, whether that works or not depends on which FPGA family you're working with. Some of the newer devices have no way to use general routing resources to hook up clocks. -- GaborArticle: 156490
Hi, My name is Harnhua; I'm one of Plunify's founders and I just wanted to chim= e in on a much-loved topic. @alb: Naturally we agree wholeheartedly with what you said. If you are willing an= d interested, let's have a chat and maybe we can propose a trial project wi= th the vendor to implement the system you envisioned? @Hans: I respectfully disagree with your comments - we are proving that it is a vi= able business model. Do you wonder why the big 3 aren't moving to the cloud? They have tried, an= d are still trying, but their current sales organizations are simply too de= eply entrenched in their lucrative all-you-can-eat models to ever want to c= hange. That's a big obstacle they have to overcome. Only the smaller EDA co= mpanies see the benefits and are more agile -- we are working with a few wh= o wish to remain anonymous for now. No less than Joe Costello, former CEO of Cadence, has commented that in the= end, only customers can lead the change, not the big 3. And people wonder = why the EDA and chip design industry are perceived as "sunset industries" n= owadays, steadily losing all the innovation we once had. It is because of t= he fear of change. Plunify is our effort to try to affect a change, but it is not change for t= he sake of changing. More and more customers are seeing the benefits of off= loading compute-intensive tasks to pay-by-the-hour datacenters. We've been = inspired by seeing cases where an engineering team accomplished in 3 days t= asks that would have taken them a whole month to do! If you don't mind, may I understand more of your concerns with using a clou= d service? That will help educate us on how we can improve. @Sean: I understand what you said about not having designs that are big enough to = require a server farm, and agree that it is mostly trust, not (merely) tech= nology that is the issue with entrusting a 3rd-party in another country wit= h your confidential data. The point I'd like to make is, why judge us before you even get to know us?= One of our first suggestions to customers is to NOT share their latest and= greatest designs if they don't feel good doing so, and just offload their = tedious tasks on stable designs, whatever they are comfortable with. For th= e record, we do encrypt your data before it is stored, if you want to store= it. We are Singapore-based, and you can choose European servers if you are= concerned about your data falling under US jurisdiction. And we're regular= engineers and software developers. Do let's have a chat if you're interest= ed in finding out more. We spend all our time making sure that our platform is secure and that supp= orted design flows function smoothly at scale. This is what's putting bread= on the table so you can be sure that we will move heaven and earth to make= our stuff work as customers'd expect it to. As cheesy as it might sound, t= he belief that Plunify can contribute to our industry as a whole also keeps= our team motivated. Cheers, HarnhuaArticle: 156491
It is official now- Lattice is out with ECP5. Which seems awfull lot like XO3H under new name, which suggests that this is new high-end of their offer. Highest model has 85K luts. Seems reasonable. At 90K or higher, ECP was never that cheap, so this makes sense. They also kept only smallest, cheapest packages. They seem determined at staying in that niche. Which might not be so bad, we just have to see prices.Article: 156492
Am 08.04.2014 22:09, schrieb Phil Hobbs: > They used to sell DIP sockets with built-in bypass caps....which > unfortunately had about an inch of lead length. I played around with a spectrum analyzer & tracking gen. and noted the results, waiting for Xilinx ISE some years ago. Those funny sockets are at he end: < http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf > Cheers, GerhardArticle: 156493
In comp.arch.fpga Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: > In article <esb8k9p3f1v40o1qmisrc8n9qptft26sll@4ax.com>, > John Larkin <jlarkin@highlandtechnology.com> writes: > > >Is that possible? 501 nF on an FPGA chip? > > If nothing else, I'd be very syspicious of any claims with > that level of accuracy. My guess is a typo. It could just be that their parasitic extraction tool told them capacitance was 501.596683nF and Marketing didn't understand about significant figures. TheoArticle: 156494
BTW, XO3L so far seems as heavy dissapointment. Not only it wasn't improved WRT to XO2 ( there is nothing from what was promised), they removed FLASH block as it was done in XO2 and plopped in NCVM block, which is "multi-time progammable". Which means TWICE. XO2 offered at least 10k programming cycles. So not only is this not good for prototyping, now it's understandable why there is no talk about UFM. It still might be that XO3L is just "Celeron" part of the spectrum and that fully fledged XO3 is to come. But prices at Digikey do not seem to follow that reduction in silicon and resources. XO3L is priced around XO2 of the same declared size. So far, this is dissapointing. Unless this is just uverture to XO3 and Sapphire. One can still hope. ;o)Article: 156495
On 04/10/2014 03:25 PM, Gerhard Hoffmann wrote: > Am 08.04.2014 22:09, schrieb Phil Hobbs: > >> They used to sell DIP sockets with built-in bypass caps....which >> unfortunately had about an inch of lead length. > > I played around with a spectrum analyzer & tracking gen. and > noted the results, waiting for Xilinx ISE some years ago. > > Those funny sockets are at he end: > < > http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf > > > > Cheers, > > Gerhard Very nice, thanks. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.netArticle: 156496
On Thu, 10 Apr 2014 21:25:35 +0200, Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> wrote: >Am 08.04.2014 22:09, schrieb Phil Hobbs: > >> They used to sell DIP sockets with built-in bypass caps....which >> unfortunately had about an inch of lead length. > >I played around with a spectrum analyzer & tracking gen. and >noted the results, waiting for Xilinx ISE some years ago. > >Those funny sockets are at he end: >< >http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf > > > >Cheers, > >Gerhard I do that sort of thing with TDR. https://dl.dropboxusercontent.com/u/53724080/TDR/TDR_0.1_slow.JPG https://dl.dropboxusercontent.com/u/53724080/TDR/TDR_0.1uF.JPG And here's the TDR of a PCB power plane, against the adjacent ground plane, in a multilayer PCB. https://dl.dropboxusercontent.com/u/53724080/TDR/TDR_3Vplane.JPG The flat pulse is the 50 ohm hardline. It slams down to about 1 ohm when the TDR step hits the PCB plane. For all practical purposes, the power plane is a perfect capacitor, and adding bypass caps, pretty much anywhere, increases its capacitance. So there's no big incentive to put the bypass caps very close to ICs. -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentationArticle: 156497
On a sunny day (Thu, 10 Apr 2014 21:25:35 +0200) it happened Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> wrote in <bqo9hfF3jv2U1@mid.individual.net>: played around with a spectrum analyzer & tracking gen. and >noted the results, waiting for Xilinx ISE some years ago. > >Those funny sockets are at he end: >< >http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf > > Thank you, that is good info, I can do something with that. But tantals are not that bad? Just too big?Article: 156498
Dne =C4=8Detrtek, 10. april 2014 21:10:16 UTC je oseba Brane2 napisala: > Unless this is just uverture to XO3 and Sapphire. One can still hope. ;o) This is freshly added on Lattice's site: "The MachXO3-H FPGA family is a higher density family that will have more a= dvanced features such as PCIe, Gigabit Ethernet, etc." If this is not just some marketing BS maneuvering, there is still a glimpse= of hope for the May announcement. :o)Article: 156499
alb <al.basili@gmail.com> wrote: > any good reference on STA? I know roughly well the principles but I've > always wanted to get a deeper understanding of this - vast - subject, > especially the algorithms behind it. Ok, I did some homework on my side and found a couple of references: 1. Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) (S. Gangadharan, S. Churiwala) - ISBN-10: 1461432685 | ISBN-13: 978-1461432685 | Edition: 2013 2. Static Timing Analysis for Nanometer Designs: A Practical Approach (J. Bhasker, R.Chadha) - ISBN-10: 0387938192 | ISBN-13: 978-0387938196 | Edition: 2009 3. Timing (Sachin Sapatnekar) - ISBN-10: 1441954082 | ISBN-13: 978-1441954084 | Edition: 2004 Any idea about their added value? On Amazon there's a review on 2. which is not very encouraging, here's an excerpt: > I'm disappointed with "Static Timing Analysis for Nanometer > Designs"[...] There's little to nothing about how timing analysis > itself is done; [...] I'm not a timing expert, but for a "book [that] > can be used as a reference for a graduate course in chip design" (p. > xivv), the exposition stayed quite rudimentary. Most explanations are > predicated on a common clock, and some issues with setup and hold on > multi-cycle paths are not mentioned; Well, if anyone has read any of the above and has a comment I would certainly appreciate it. Al
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z