Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Sun, 10 Nov 2013 00:04:09 -0800, koyel.aphy wrote: > Hi, > > I am unable to understand that how a PC communicate with FPGA. I have > used Xilinx software to implement codes and then connected a USB cable > to Xilinx test kit that did all jobs for me. Of course I assigned the > chip pins with the signal names through Xilinx software itself. I am > unaware what happens after I connect the USB cable to the kit. Please > tell me what devices are in between the PC and the chip in the kit and > how does the PC communicate with the chip or loads the design into the > chip? > > thanks Koyel The design is loaded into the FPGA through a synchronous serial connection. There should be some Xilinx data sheet that describes the process. If they haven't changed things since I last really paid attention that synchronous serial connection can be used by a processor (on-board or external) to push a bitstream into the FPGA, or it can be used at boot up for the FPGA to suck a bitstream out of a serial flash chip. In a production system with a separate microprocessor, you can keep the FPGA design in the processor flash memory, and load the FPGA from the microprocessor -- Xilinx has app notes that detail that process, too. I remember doing that during a period when the biggest Xilinx FPGAs were quite a bit bigger than the biggest Xilinx serial flash chips, and 'big' microcontrollers all tended to come equipped for external flash. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 156026
On Sun, 10 Nov 2013 00:54:56 -0800, eyecatcherdear wrote: > Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3 clocks > of 150MHz, 112.5MHz and 14.063MHz. I can't produce them with one pll > core since it does not generate the exact clock. If i concatenate two > cores, the second core does not produce clock. ( i set one core with > input clock as external and other as hardwired). I need help to produce > these 3 clocks. Do they have to be synchronized somehow? Do they have to be generated on- chip? Do they need to be extra high precision? Can they be extra-low precision? A brute-force method, if you have board space and don't want to spend time messing with the FPGA, is to just use three oscillators. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 156027
On Mon, 11 Nov 2013 09:28:24 +0000, Tom Gardner <spamjunk@blueyonder.co.uk> wrote: >On 11/11/13 03:08, John Larkin wrote: >> On Sun, 20 Oct 2013 08:47:57 +0100, Tom Gardner <spamjunk@blueyonder.co.uk> >> wrote: >> >>> On 20/10/13 03:02, Paul Rubin wrote: >>>> Tom Gardner <spamjunk@blueyonder.co.uk> writes: >>>>> I'd like to pick people's brains about aspects of >>>>> different *suppliers* of Zynq boards. >>>> >>>> Do you know anything about the microzed? I just heard of it, and it >>>> looks interesting: >>>> >>>> http://microzed.org >>>> http://linuxgizmos.com/tiny-sbc-runs-linux-on-xilinx-zynq-arm-fpga/ >>>> >>>> Also the Zybo: >>>> >>>> http://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO >>> >>> They do indeed look interesting for my purposes, but I only >>> know what I can read on the web. >>> >>> So, we would /both/ like some info about the suppliers :) >>> >>> >> >> We're just starting on a uZed signal-processing project. It will be a uZed >> plugged into a motherboard that has power, clock, signal input and output >> networks, ADC, DAC, connectors, and miscellaneous stuff. We bought two uZed >> boards from Avnet and they power up running Linux. My programmer and FPGA guys >> are just now learning how to write a C app that interacts with the FPGA, but the >> documentation seems good and they are making good progress. I'll be doing the >> architecture and designing the hardware. >> >> I took some pictures. The ones in the ZED documentation are mediocre. >> >> https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_Top.JPG >> >> https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_Bottom.JPG >> >> https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_End.JPG > >Thanks, that's useful, and I will be *most* interested to hear how >it goes. > >Out of curiosity, how long ago did you buy them and how long did >they take to materialise? Currently Avnet are showing no stock >and 5 weeks lead time. > >Worryingly, it has been "5 weeks" for the past 3 weeks - so I'm >concerned that Avnet have "lost interest" in the board. Any info >about Avnet's support practices would be useful. > It took about a week to get two, several weeks ago. They can probably find some for good customers. We buy a lot of stuff from them, and it was "get us a couple and we'll design them in." The good part is that the design, including Gerbers, is fully public, so we (or someone) can build them if we have to. It will save us a ton of time, as compared to doing all that pcb-layout/flash/dram/ethernet/power supply/software stuff ourselves. I hope they are serious about it. They have sure invested a lot so far. The carrier/demo board is apparently not real yet. We'll have our own application board first, with spare room, so we'll add in some development hooks for future projects. Suggestions are welcome.... Mictor connector for a logic analyzer Pots for the ADC inputs A few SMB connectors for scope trigger/signal snooping Shunts to measure Vcc and bank currents Easy ways to vary iobank voltages Dip switches and LEDs Temperature sensor IC Clock oscillators -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generatorsArticle: 156028
On 11/10/13, 3:54 AM, eyecatcherdear@gmail.com wrote: > Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3 > clocks of 150MHz, 112.5MHz and 14.063MHz. I can't produce them with > one pll core since it does not generate the exact clock. If i > concatenate two cores, the second core does not produce clock. ( i > set one core with input clock as external and other as hardwired). I > need help to produce these 3 clocks. > First, realize that you will NEVER get EXACT frequencies, if only because your input frequency input won't be exact (hopefully fairly close if it is a crystal, but all sources have errors). You also don't need exact, but the thing that needs the clock should have specs for how close it needs to be (and sometimes it is a "not to exceed" limit for things like processor or memory clocks). Using this you may well find that one PLL can generate all the frequencies. If your 150 and 112.5 can be ever so slightly high, then one choice would be to use an internal frequencey of 450.016 MHz (14.063*32) and then divide that by 3 and 4 for the two high speed clocks, which puts them less than 36 ppm high.Article: 156029
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> writes: > The good part is that the design, including Gerbers, is fully public,... > I hope they are serious about it. They have sure invested a lot so far. That big wire on the back of the board in your photo is interesting. Although red in color, it looks like what's traditionally called a "blue wire", i.e. maybe they're out of stock right now because the board is in the process of being revved.Article: 156030
I've been using Ise WebPack 10.1 for some time, as it is the last version that supported the Spartan 2E chips. I don't do a lot on the 2E anymore, but there are a number of units in the field with those chips. Anyway, I'm still using Spartan 3A and 3AN, as well as 9500XL and Coolrunner II CPLDs. I recently realized my main desktop computer has been running 12 years straight, and is probably living on borrowed time. So, I'm trying to set up a new system. Xilinx doesn't allow WebPack 10.1 to run on X86_64 systems, but some people report workarounds. So far, I have not gotten it to install on Linux. I installed the 32-bit libraries and bypassed the first-level setup script, but I get to a page where you enter your Xilinx registration code, and then it allows you to select the components you want, but WebPack is greyed out. So, apparently at that script it also detects the 64-bit system. Then, I tried downloading the current version of Vivado WebPack, but it supports only a VERY small range of -7 parts, and no CPLDs. Didn't seem like a very useful piece of software. And, there's no way I can afford $4000 to be allowed to run 5-year old software. What gives? WebPack used to be a completely viable option for developing on the mid-range parts from several families. I'm going to try copying over all my files from the 10.1 install on the old machine and see if that works. If not, does anyone know what older Ise Webpack will support Spartan 3A plus CPLD's and run on a 64-bit Linux system? I tried looking this up on Xilinx.com, but it was REALLY difficult to find any mention of what chips are supported by what software. Thanks for any tips! JonArticle: 156031
On Mon, 11 Nov 2013 16:40:56 -0600 Jon Elson <jmelson@wustl.edu> wrote: > I've been using Ise WebPack 10.1 for some time, as it is the last version > that supported the Spartan 2E chips. I don't do a lot on the > 2E anymore, but there are a number of units in the field with > those chips. Anyway, I'm still using Spartan 3A and 3AN, as > well as 9500XL and Coolrunner II CPLDs. I recently realized > my main desktop computer has been running 12 years straight, > and is probably living on borrowed time. So, I'm trying to > set up a new system. Xilinx doesn't allow WebPack 10.1 to > run on X86_64 systems, but some people report workarounds. > So far, I have not gotten it to install on Linux. I > installed the 32-bit libraries and bypassed the first-level > setup script, but I get to a page where you enter your > Xilinx registration code, and then it allows you to select the > components you want, but WebPack is greyed out. So, apparently > at that script it also detects the 64-bit system. > > Then, I tried downloading the current version of Vivado WebPack, > but it supports only a VERY small range of -7 parts, and no > CPLDs. Didn't seem like a very useful piece of software. > And, there's no way I can afford $4000 to be allowed to run > 5-year old software. What gives? WebPack used to be a completely > viable option for developing on the mid-range parts from > several families. > > I'm going to try copying over all my files from the 10.1 > install on the old machine and see if that works. If not, does > anyone know what older Ise Webpack will support Spartan 3A > plus CPLD's and run on a 64-bit Linux system? I tried looking > this up on Xilinx.com, but it was REALLY difficult to find any > mention of what chips are supported by what software. > > Thanks for any tips! > > Jon Xilinx's software, in my experience, does not play well with others. I've taken to running even my later versions in VirtualBox VMs. This way whatever nonsensical fights FlexLM wants to have with other programs can get trapped in individual sandboxes. So it seems by that logic, you should be able to set up a VM running a 32-bit OS (I've had excellent luck with CentOS, far better than anything Debian derived), and install 10.1 on it. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 156032
On Monday, November 11, 2013 4:28:24 AM UTC-5, Tom Gardner wrote: > Out of curiosity, how long ago did you buy them and how long did > they take to materialise? Currently Avnet are showing no stock > and 5 weeks lead time. > > Worryingly, it has been "5 weeks" for the past 3 weeks - so I'm > concerned that Avnet have "lost interest" in the board. Any info > about Avnet's support practices would be useful. I ordered one mid-September when the leadtime was "1 week". That sounded a little suspicious so I went to web chat support and got "4 weeks" as the real leadtime. It does sound like they're preparing a new rev.Article: 156033
Rob Gaddi wrote: > Xilinx's software, in my experience, does not play well with others. > I've taken to running even my later versions in VirtualBox VMs. This > way whatever nonsensical fights FlexLM wants to have with other > programs can get trapped in individual sandboxes. > > So it seems by that logic, you should be able to set up a VM running a > 32-bit OS (I've had excellent luck with CentOS, far better than > anything Debian derived), and install 10.1 on it. > Yes, FlexLM, even on Windows, was a messy and very poorly documented system. I did get it to work after migrating a very old Foundation 4.2 system by making the virtual Win 2K system's drive serial number match the system the license keys were originally created for. I had to do that because Xilinx couldn't generate keys for 3rd party software anymore. I really HATE to have all these separate VMs running. I have one VM for Windows CAD software, but have moved everything I can to native Linux. Anyway, after some more digging, it seems Ise WebPack 12.2 explicitly works on 64-bit systems and supports the CPLDs and Spartan 3A. So, I think I'm going to go with that, assuming I can get it to install. Many of the older products have documentation/release notes links that don't work, so it was pretty difficult to tell what was and wasn't supported by various older versions. But, the link for 12.2 did work. Thanks, JonArticle: 156034
Am 11.11.2013 23:40, schrieb Jon Elson: > I've been using Ise WebPack 10.1 for some time, as it is the last version > that supported the Spartan 2E chips. I don't do a lot on the > 2E anymore, but there are a number of units in the field with > those chips. Anyway, I'm still using Spartan 3A and 3AN, as > well as 9500XL and Coolrunner II CPLDs. I recently realized > my main desktop computer has been running 12 years straight, > and is probably living on borrowed time. So, I'm trying to > set up a new system. Xilinx doesn't allow WebPack 10.1 to > run on X86_64 systems, but some people report workarounds. I run 10.1 on a virtual XP machine and it works, including the USB download cable. Also my old Modelsim 6, Sigasi, and the current Altium designer. Vivado Webpack works, too, but I installed it only for curiousity, not for real work. One nice thing is that I can move the virtual machine from the workstation to my Dell Precision laptop and I have everything I need. I even exported the virtual machine from Virtual Box and then imported it into VMware Workstation, and it simply ran ( 2 weeks ago). Access to shared folders seems to be slow in my case on VMware, some friends say it's not for their systems. It looks like the XP network interface runs into timeouts when searching hosts, I'll sort that out when I have some time. USB and graphics integration is better on VMware, at least for my taste. My machines run Xubuntu, maybe MINT soon. regards, GerhardArticle: 156035
On 11/11/2013 6:28 PM, Jon Elson wrote: > Rob Gaddi wrote: > > >> Xilinx's software, in my experience, does not play well with others. >> I've taken to running even my later versions in VirtualBox VMs. This >> way whatever nonsensical fights FlexLM wants to have with other >> programs can get trapped in individual sandboxes. >> >> So it seems by that logic, you should be able to set up a VM running a >> 32-bit OS (I've had excellent luck with CentOS, far better than >> anything Debian derived), and install 10.1 on it. >> > Yes, FlexLM, even on Windows, was a messy and very poorly documented > system. I did get it to work after migrating a very old Foundation > 4.2 system by making the virtual Win 2K system's drive serial number > match the system the license keys were originally created for. > I had to do that because Xilinx couldn't generate keys for 3rd party > software anymore. > > I really HATE to have all these separate VMs running. I have one VM for > Windows CAD software, but have moved everything I can to native Linux. > > Anyway, after some more digging, it seems Ise WebPack 12.2 explicitly > works on 64-bit systems and supports the CPLDs and Spartan 3A. So, I > think I'm going to go with that, assuming I can get it to install. > > Many of the older products have documentation/release notes links that > don't work, so it was pretty difficult to tell what was and wasn't > supported by various older versions. But, the link for 12.2 did work. > > Thanks, > > Jon > If you're willing to drop the Spartan 2, 2e, Virtex 2 and older parts, you can go right up to the latest ISE (not Vivado) which is 14.7 IIRC. However if you're not interested in the 7-series, I think 13.4 is a very stable and usable platform. It also has some very usable improvements to ISIM, if you don't have another simulator at hand. Basically the part support changed going from 10.1.03 to 11.x and nothing was dropped from ISE since then. Vivado, on the other hand does not support anything older than 7-series and never will. I still have a very old system running 32-bit XP, so I can't comment on the virtual machine. I also run Foundation 4.1i on the same machine, so altogether there are quite a few versions of ISE installed. Lately I've been using 13.4 for all of my Virtex 5 and Spartan 6 work, and just getting into some 7-series projects with 14.6 From what I can tell, Vivado is not ready for prime time and I don't have the will to beta test it. If I do use it, it will only be because they stop adding new support for 7-series to the ISE product. -- GaborArticle: 156036
@Tim Wescott: Yes they have to be generated on core. Actually I need these clocks to implement 3/4 punctured coding with output data rate as 150MHz. 150 and 112.5 are not of very high precision when generated from one core. @Richard Damon: Yeah I agree to that. But atleast closer. I am going to try your method but you said "internal frequencey of 450.016 MHz (14.063*32) and then divide that by 3 and 4 for the two high speed clocks, which puts them less than 36 ppm high." I don't understand the last part. Why is it required to put them less than 36ppm high? Is there any document you can recommend for clock generation which discusses the PLL clock cores in detail? I get confused with multiple clock generation. I was wondering if I cascade two cores? The user guide says it allows to generate 6 clocks that means 2 cores. I tried that using one to generate 150MHz and then generate 112.5 and 14.063 from 150 but the last 2 clocks did not generate.Article: 156037
On 11/12/2013 5:28 AM, eyecatcherdear@gmail.com wrote: > @Tim Wescott: Yes they have to be generated on core. Actually I need these clocks to implement 3/4 punctured coding with output data rate as 150MHz. 150 and 112.5 are not of very high precision when generated from one core. > > @Richard Damon: Yeah I agree to that. But atleast closer. I am going to try your method but you said "internal frequencey of 450.016 MHz (14.063*32) and > then divide that by 3 and 4 for the two high speed clocks, which puts > them less than 36 ppm high." I don't understand the last part. Why is it required to put them less than 36ppm high? > > Is there any document you can recommend for clock generation which discusses the PLL clock cores in detail? I get confused with multiple clock generation. > > I was wondering if I cascade two cores? The user guide says it allows to generate 6 clocks that means 2 cores. > I tried that using one to generate 150MHz and then generate 112.5 and 14.063 from 150 but the last 2 clocks did not generate. A PLL generates clocks by running a voltage controlled oscillator (VCO) at a rate typically higher than a reference input clock, dividing this clock rate down and then using a phase comparator to compare to the input clock. The action of the phase comparator output brings the frequency of the divided VCO clock to the same rate as the reference and the output of the PLL to a multiple of the reference clock. Once you have this output clock you can divide the rate down by any amount you wish. It would make sense to have a reference clock equal to one of the input clock rates, but 25 MHz is a nicer rate, not so high as to be hard to distribute and high enough for most PLLs. Many FPGAs have a minimum input frequency spec of 25 MHz or so. Or you could use 50 MHz. Set your PLL to generate 450 MHz. Then you can simply divide this clock down to generate the three internal clocks of 150, 112.5 and 14.063 MHz (divide by 3, 4 and 32). You say the FPGA PLL can generate up to 3 clock outputs. If they have programmable dividers for each of the three outputs you should be able to generate all three frequencies from one reference input. The only problem I see is that the 150 MHz requires a divider of 3 from 450 MHz. It is common to use a programmable divider followed by a divide by 2 to give a symmetrical clock waveform (50/50 duty cycle). So you might not be able to generate 150 MHz from 450 MHz using the build in dividers. You can fix this by ramping up the PLL output rate to 900 MHz, using a divider external to the PLL (if it will let you bring the 450 MHz out) or you can just use a second PLL with the same input reference to generate say, 300 MHz internally and divide by 4. Is that clear? PLLs have limitations and you need to work with those. -- RickArticle: 156038
Gabor wrote: > > If you're willing to drop the Spartan 2, 2e, Virtex 2 and older > parts, you can go right up to the latest ISE (not Vivado) which > is 14.7 IIRC. However if you're not interested in the 7-series, > I think 13.4 is a very stable and usable platform. How about XC9500XL and CoolRunner II CPLD's? The Xilinx download page doesn't have working release notes for most of the older Ise versions. > It also has > some very usable improvements to ISIM, if you don't have another > simulator at hand. Basically the part support changed going from > 10.1.03 to 11.x and nothing was dropped from ISE since then. OK, sounds good! Well, I tried 12.2, and it installed just fine, but got an error message while trying to read the license file. All the things on the main page that seem like they connect to your browser (Firefox in my case) get the same message about GLIBCXX(specific version) not found. But, it seemed to run anyway (maybe 30-day trial license) so I tried synthesizing a simple vhdl file, and it crashed with a 2-page traceback. UGH! Then, I copied over my 10.1 Webpack install using sftp, and it almost works! I did a complete compile of that same VHDL, worked fine (and was quite a bit faster than my old computer). But, Impact wouldn't even start from the GUI, complained about "Cable operation is not supported" on the 64-bit platform. I'll have to tinker with this a bit and see if I can come up with a version of Impact that works. I don't need it to be integrated with the GUI either. I also didn't try isim, and that may need me to generate a new license. Thanks, JonArticle: 156039
I'd love if someone could tell me if what I've found is as stupid as I think it is, or far cleverer than I am. So I'm putting together a design using Qsys on Quartus 13.0. I used the Avalon-MM Clock Crossing bridge out of the Altera library, and have been having some wacky issues on reset. So I go spelunking. The Avalon-MM Clock Crossing bridge wraps two of the Avalon-ST Dual Clock FIFO. Okay, I suppose that makes sense. Both these cores have two reset inputs, one for the master/write side clock and one for the slave/read side. Fine, sure, good. In the ST FIFO that's at the core of all this, however, those two resets never meet up. So the write side reset asynchronously clears the write_ptr, and the read side reset async clears the read_ptr. Well, now I know why I'm getting old junk transactions stuck in my clock crossing bridge after resetting one side. Does anyone have a reason why one might want to reset only one side or the other of the FIFO, or is this (undocumented, of course) behavior just silly? -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 156040
Jon Elson wrote: [snip] >> I think 13.4 is a very stable and usable platform. > How about XC9500XL and CoolRunner II CPLD's? > The Xilinx download page doesn't have working release notes for > most of the older Ise versions. > The CPLD's are also in the latest versions of ISE, however there have not been any improvements other than simulation that would warrant upgrading. >> It also has >> some very usable improvements to ISIM, if you don't have another >> simulator at hand. Basically the part support changed going from >> 10.1.03 to 11.x and nothing was dropped from ISE since then. > OK, sounds good! > > Well, I tried 12.2, and it installed just fine, but got an error > message while trying to read the license file. All the things on > the main page that seem like they connect to your browser > (Firefox in my case) get the same message about GLIBCXX(specific version) > not found. But, it seemed to run anyway (maybe 30-day trial license) > so I tried synthesizing a simple vhdl file, and it crashed with a > 2-page traceback. UGH! > There is a license manager you can access from the GUI under Help. That would tell you if you're using an eval license. Also I would double check whether 12.2 actually supports your OS. I was under the impression that OS support was enhanced in much more recent releases like 14.x On the other hand, that may only affect the newer Windows versions (Vista, and 7). I don't think Windows 8 is supported yet. > Then, I copied over my 10.1 Webpack install using sftp, and it almost > works! I did a complete compile of that same VHDL, worked fine > (and was quite a bit faster than my old computer). But, Impact > wouldn't even start from the GUI, complained about "Cable operation is > not supported" on the 64-bit platform. I'll have to tinker with this > a bit and see if I can come up with a version of Impact that works. > I don't need it to be integrated with the GUI either. > Impact was never very good with 64 bits. On the other hand, you don't really need old versions of Impact. The newest Impact should still support the old devices, as well as old bit files. > I also didn't try isim, and that may need me to generate a new license. > As I said, ISIM got a lot better in the 13.x releases. For one thing they added the Re-Launch button to work around the issue that you can't recompile and restart from within ISIM. -- GaborArticle: 156041
GaborSzakacs wrote: > > There is a license manager you can access from the GUI under Help. Right, but none of these buttons do anything. There is a "License manager" button, and an "obtain license" button, these do nothing. I think it is because it uses your default browser, and there is a library mismatch that prevents the interface to the browser from running. > That would tell you if you're using an eval license. Also I would > double check whether 12.2 actually supports your OS. I was under the > impression that OS support was enhanced in much more recent releases > like 14.x On the other hand, that may only affect the newer Windows > versions (Vista, and 7). I don't think Windows 8 is supported yet. > LINUX! It seems other than some library problems, none of the Linux versions actually care about the OS version. >> Then, I copied over my 10.1 Webpack install using sftp, and it almost >> works! I did a complete compile of that same VHDL, worked fine >> (and was quite a bit faster than my old computer). But, Impact >> wouldn't even start from the GUI, complained about "Cable operation is >> not supported" on the 64-bit platform. I'll have to tinker with this >> a bit and see if I can come up with a version of Impact that works. >> I don't need it to be integrated with the GUI either. >> > > Impact was never very good with 64 bits. On the other hand, you don't > really need old versions of Impact. The newest Impact should still > support the old devices, as well as old bit files. > Yes, that's what I'm thinking, but I'd have to get a new version of Impact installed. I see some "lab" versions of ise that probably have impact and a few other things in them that ought to do it. >> I also didn't try isim, and that may need me to generate a new license. >> > > As I said, ISIM got a lot better in the 13.x releases. For one thing > they added the Re-Launch button to work around the issue that you can't > recompile and restart from within ISIM. > OK, I couldn't get the release notes for 13.x to work from the download web page. But, maybe I should try to download 13! Thanks, JonArticle: 156042
Jon Elson wrote: > GaborSzakacs wrote: > >> There is a license manager you can access from the GUI under Help. > Right, but none of these buttons do anything. There is a "License > manager" button, and an "obtain license" button, these do nothing. > I think it is because it uses your default browser, and there is > a library mismatch that prevents the interface to the browser > from running. > The license manager should be standalone. Try starting it from the command line with: xlcm or xlcm -manage If you can't find the executable, that could explain the fact that the buttons don't work. On my WinXP system, the executable is in ISE_DS/common/bin/nt under the installation. -- GaborArticle: 156043
On Tue, 12 Nov 2013 12:43:39 -0800 Rob Gaddi <rgaddi@technologyhighland.invalid> wrote: > I'd love if someone could tell me if what I've found is as stupid as I > think it is, or far cleverer than I am. > > So I'm putting together a design using Qsys on Quartus 13.0. I used > the Avalon-MM Clock Crossing bridge out of the Altera library, and have > been having some wacky issues on reset. So I go spelunking. > > The Avalon-MM Clock Crossing bridge wraps two of the Avalon-ST Dual > Clock FIFO. Okay, I suppose that makes sense. Both these cores have > two reset inputs, one for the master/write side clock and one for the > slave/read side. Fine, sure, good. > > In the ST FIFO that's at the core of all this, however, those > two resets never meet up. So the write side reset asynchronously > clears the write_ptr, and the read side reset async clears the read_ptr. > > Well, now I know why I'm getting old junk transactions stuck in my > clock crossing bridge after resetting one side. Does anyone have a > reason why one might want to reset only one side or the other of the > FIFO, or is this (undocumented, of course) behavior just silly? > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. Additional note on this. Because the Avalon-ST Dual Clock FIFO (a.k.a. altera_avalon_dc_fifo) is also what is automatically inserted into the Qsys design for a clock-domain crossing when you simply let Qsys "take care of it" and have the design set for FIFO crossings rather than Handshake, the same problem occurs. If you only reset one clock domain, then the read and write pointers get out of whack and the FIFO gets hosed. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 156044
In article <l5u8k9$jll$1@dont-email.me>, GaborSzakacs <gabor@alacron.com> wrote: >Jon Elson wrote: >> GaborSzakacs wrote: >> >>> There is a license manager you can access from the GUI under Help. >> Right, but none of these buttons do anything. There is a "License >> manager" button, and an "obtain license" button, these do nothing. >> I think it is because it uses your default browser, and there is >> a library mismatch that prevents the interface to the browser >> from running. >> > >The license manager should be standalone. Try starting it from >the command line with: > >xlcm > >or > >xlcm -manage > >If you can't find the executable, that could explain the fact that >the buttons don't work. On my WinXP system, the executable is in >ISE_DS/common/bin/nt under the installation. For what it's worth - we've NEVER had any luck with any of the flex-lm wizards like xlcm. Cadence/Modelsim/Xilinx they just don't work. Xilinx xlcm, just crashes. The others all report an invalid license, when in fact they're valid and work just fine. Now, on the other hand setting up the license server on a linux box, and just controlling the licensing by hand isn't any trouble at all. Took a few hours of reading the flex-lm docs 6 or 7 years ago. Now, just copy any *.lic into appropriate directory (minor edits to fix the daemon pathname), and run "lmutil lmreread". Done. Hasn't failed us in all that time. All the end users need to do is make sure that env variable: LM_LICENSE_FILE = 1717@license_server And tell them NOT to run the license manager gui. That one variable (and single lmgrd) dishes out all licenses (Xilinx/Modelsim/Cadence/ others...) Regards, MarkArticle: 156045
In article <20131112124339.7deb9d9a@rg.highlandtechnology.com>, Rob Gaddi <rgaddi@technologyhighland.invalid> wrote: >I'd love if someone could tell me if what I've found is as stupid as I >think it is, or far cleverer than I am. > >So I'm putting together a design using Qsys on Quartus 13.0. I used >the Avalon-MM Clock Crossing bridge out of the Altera library, and have >been having some wacky issues on reset. So I go spelunking. > >The Avalon-MM Clock Crossing bridge wraps two of the Avalon-ST Dual >Clock FIFO. Okay, I suppose that makes sense. Both these cores have >two reset inputs, one for the master/write side clock and one for the >slave/read side. Fine, sure, good. > >In the ST FIFO that's at the core of all this, however, those >two resets never meet up. So the write side reset asynchronously >clears the write_ptr, and the read side reset async clears the read_ptr. > >Well, now I know why I'm getting old junk transactions stuck in my >clock crossing bridge after resetting one side. Does anyone have a >reason why one might want to reset only one side or the other of the >FIFO, or is this (undocumented, of course) behavior just silly? I'm with you Rob - sounds silly to me. I know nothing of that product, so can't offer much, but common fifo bugs are around initialization. You often need a bit of logic in your design to make sure that both sides of the fifo come out of reset into the proper states. Resetting just one side seems like asking for trouble. --MarkArticle: 156046
Rob Gaddi <rgaddi@technologyhighland.invalid> wrote: > Well, now I know why I'm getting old junk transactions stuck in my > clock crossing bridge after resetting one side. Does anyone have a > reason why one might want to reset only one side or the other of the > FIFO, or is this (undocumented, of course) behavior just silly? I'm not completely clear on why that happens. You need two inputs because each reset needs to be in the right clock domain, otherwise Excitement (TM) happens if you try and clock domain cross with the resets. Perhaps the model is that the resets only reset the parts in the domain that belongs to it, and propagating the resets is your problem. How are you generating the clocks for the two parts? I think the standard Qsys clock input block will also synchronise a reset to a given clock - perhaps you need one of those? TheoArticle: 156047
Hi Svenn, > Shit, I need a native USB 2.0 host in VHDL. Any poor sucker who would do > a 4 week job at USD30/week? Cash on Delivery!!!! (though paypal) >=20 > Is this how we want globalization to work? It is not in my best interest to let globalization work this way:) My hourl= y and not weekly rate is typically around USD 30. Greek clients would be ha= ppy having me work for USD 10 per hour, but I ditch them (like four times s= ince September for some major projects -- like OEMs for license plate recog= nition -- since there is no margin for any benefit!) So clients are helples= s and are typically middle-men who want to go into production (yeah right, = thanks for the entertainment Greek IT people!) For these kind of tasks a reasonable hourly rate e.g. in Germany is around = 70-100 USD; this is what the client expects to pay for high-quality work.= =20 I'm afraid that rates of a couple of dollars exist; don't ask me where, you= know. But in some aspect or another you will get what you pay for. Best regards Nikolaos Kavvadias http://www.nkavvadias.com http://www.ajaxcompilers.com http://www.perfeda.grArticle: 156048
Hi Rick, On 08/11/2013 15:47, rickman wrote: [] >> According to the FAE it is possible to configure the internal weak >> pull-up resistor on the PIN configuration and profit of the same >> mechanism described in the AN I was referring to >> (http://www.actel.com/documents/LPF_AC380_AN.pdf), therefore >> *without* the need of an additional external pull up resistor. > > The app note goes into great detail about the timing of VCC and VCCI. > In this discussion I believe they are talking about the input from > the IBUF (RST_p) when they say, "The I/Os are tristated and the core > logic detects '1' on the inputs from the boundary scan register > (BSR)." It is not clear what sets the value in the BSR. It is also > not clear how this determines the value of the RST_p signal. Between the I/O Bank and the FPGA core there's the BSR mandated by the IEEE-1149.1 standard (JTAG) that you can control during programming. I'm trying to look for 'default' values, but that is not essential since when both VCC and VCCI will be above the functional voltage level the I/O will first drive the input and 200ns later the output, resulting in the transition '1'->'0' on RST_p which, in turns, generates a transition '0'->'1' on RST_n, to be used internally as an active low reset. > This entire circuit seems to depend on VCC reaching "its functional > voltage level" before VCCI. Do you know that this is true for your > board? Actually you do not need to have VCC functional *before* VCCI. I paste here an excerpt from the app note: (pag.2) > Before the start of power-up, all the I/Os are tristated. The I/Os > remain tristated during the power-up until the last supply (being > either VCCIBx or VCC) is powered to its functional activation voltage > level. After the last supply reaches the functional voltage level, > the outputs of the active I/O bank exits the tristate mode and drive > the logic at the input of the output buffer. Similarly, the input > buffers of the active I/O bank passes the external logic into the > FPGA fabric once the last supply reaches its functional voltage > level. The behavior of user I/Os is independent of the VCC and VCCIBx > power-up sequence HTH, AlArticle: 156049
GaborSzakacs wrote: > > The license manager should be standalone. Try starting it from > the command line with: > > xlcm No, it didn't work, either, as it seems it also uses your browser as a front end. But, I just copied my text license file over, and it worked. So, a BIG thanks, Gabor, for the suggestion to try 13.4! It seems to work fine except for Impact. So, I brought in a VHDL file and did both the implementation steps as well as ran an isim simulation on my test bench, and these all worked. Isim has changed enough that I had to search for the familiar buttons, but I got it to work after a couple of minutes. Hmm, default time units are now ps! Leads to insanely large numbers on the screen. The install complained that drivers could not be installed, probably you need to compile them separately. I seem to recall having to do this on 10.1, also. I did find it had built a kernel module install_windrver6, but I could not get modprobe to install it. I suspect I can take this up with Xilinx, as 13.4 must still be supported. Thanks again, Jon
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z