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We'd like to announce the release of a 'super small' soft processor
core. The goal of our project/core is to make the smallest possible
FPGA area footprint processor (for now, on Altera FPGAs) that is
compatible with MIPS binaries. It is a bit-serial processor in
implementation, although the interface is completely 32-bit, and so very
slow. It comes in a two flavours, one with exceptions, and one without.
How small? It requires 236 Stratix III ALUTs/336 registers/207 ALMs with
exceptions enabled, and 142 ALUTs/168 registers/115 ALMs without them.
This compares well with the completely stripped down Nios II/e's scores,
which we measured at 517 ALUTs/311 registers/347 ALMs, making it between
1.7x and 3.0x smaller than the smallest available Nios II.
How slow? When run against the eclectic collection of test benchmarks
included with the processor, it was found to be 8-10x slower on average
than a Nios II/e compiled with the same settings. Its clock speed
ranges from 130 MHz for the smallest version to 171 MHz for the largest.
You can find the release at:
http://www.eecg.toronto.edu/~jayar/software/SuperSmallProcessor/
The processor is 2-clause BSD-licensed, so feel free to download it,
play with it, and use it wherever you want. It works great as an Avalon
master, and includes everything you need to use it with SOPC builder.
Also available on the website is a compiler consisting of a vanilla GNU
toolchain (binutils, gcc, newlib) targeted to MIPS and slightly modified
to avoid multiplies, divides, and unaligned access instructions.
Unfortunately, the design is currently very Altera-specific: the design
work has only been done on a Stratix III, and it uses Altera's lpm
modules for on-chip ram. As far as we know though, none of these issues
are anything integral to the architecture, so theoretically someone
could port it to Xilinx if they wanted to.
James Robinson & Jonathan Rose
The Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto
Article: 143201I'd like to set up automated unit test scripts. (I'm using Riviera Pro 2009.06.) Does anyone know a good way of doing this? For example, I've written assertion-based unit tests for most of my modules. I'd like something to run each test and summarize the results. I know I could probably do so with a csh/bash script. However, I was looking for something more canned if it exists.Article: 143202
Thanks a lot for the help. I found the problem after reading your post. I don't have a C:\lsc_env directory. The ini files are in lsc_env under ispTOOLS7_2. I tried looking at lsc_7_2.ini and the differences were limited to directories and three lines at the end which seem to have to do with reading error messages about a compile. I removed the three error messages and ispLever still didn't start. Since there were seven errors about reading the .ini file, I figured the directory must be wrong. Sure enough when I checked the environment variables, LSC_INI_PATH was pointing to c:\lsc_env which I don't have. Changing that to the correct path seems to have fixed the problem. I have ***NO*** idea how that was altered in the middle of using the tool. Thanks again. Rick On Sep 25, 6:46=A0am, Charles Gardiner <inva...@invalid.invalid> wrote: > Normally ispLever installs the *.ini files to c:\lsc_env. You can change > this by setting the variable LSC_INI_PATH to something like > %USERPROFILE%\lsc_env > > If yours has become screwed up somehow, you can write your own based on > the one below (from German windows Server 2003): > Store it under lsc_7_2.ini in whichever lsc_env directory you decide to > use original or one pointed to by LSC_INI_PATH). > > Sorry, but I can't restrain myself on my favorite rant here. The big > problem is the cluelessness of so many windows SW developers who still > have not realised that computers in the 21th century are largely > multi-user or at least that the SW should support that model. Putting > one config file for everbody in a privately invented directory should > have died out around 1990. It would be a great help to the user if these > developers took the time to look at the windows API and read the section > Win32 and Com Development -> Administration and Management > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -> Policies and Profi= les > (Now, I'm feeling better) > > [paths] > Bin=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\bin > Config=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\config > Examples=3DC:\Programme\Lattice\ispTOOLS7_2\examples > FPGAPath=3DC:\Programme\Lattice\ispTOOLS7_2\ispfpga > FPGABinPath=3DC:\Programme\Lattice\ispTOOLS7_2\ispfpga\bin\nt > INI=3DC:\lsc_env > License=3DC:\Programme\Lattice\ispTOOLS7_2\license > Root=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld > ispVM=3DC:\Programme\Lattice\ispTOOLS7_2\ispvmsystem > SpectrumPath=3D"C:\isptools\spectrum" > PrecisionPath=3D"" > ModelsimPath=3D"" > SynplifyPath=3DC:\Programme\Lattice\ispTOOLS7_2\synpbase > MachPath=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\bin > AppNotes=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\bin > PDSPath=3DC:\Programme\Lattice\ispTOOLS7_2\ispcomp > Tutorial=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\tutorial > Manuals=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\manuals > DSPPATH=3DC:\Programme\Lattice\ispTOOLS7_2\ispLeverDSP > TclPath=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\tcltk\bin > ActiveHDLPath=3DC:\Programme\Lattice\ispTOOLS7_2\active-hdl\bin > > [Strings] > ProductName=3DispLEVER > ProductPrefix=3DSYN > ProductTitle=3DispLEVER > ProductVersion=3D7.2.00.07 > ProductType=3D7.2.00.41.49.08_LS_HDL_BASE_PC_N > ProgramFolder=3DLattice Semiconductor 7.2 > > [CPLD] > > [FPGA] > LSCC_DEV_PATH=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\data > LSCC_RDD_PATH=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\data > LSCC_LIB_PATH=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\data > LSCC_LCI_PATH=3DC:\Programme\Lattice\ispTOOLS7_2\ispcpld\config > LSDB_COMPRESSED =3D "1" > > [Packages] > LatticeGNUCompiler=3DC:\Programme\Lattice\ispTOOLS7_2\micosystem > LatticeMico32System=3DC:\Programme\Lattice\ispTOOLS7_2\micosystem > Synplify=3DC:\Programme\Lattice\ispTOOLS7_2\synpbase > Spectrum=3D"C:\isptools\spectrum" > Precision=3D"" > ModelSim=3D"" > ispVMSystem=3DC:\Programme\Lattice\ispTOOLS7_2\ispvmsystem > HDLExplorer=3DC:\Programme\Lattice\ispTOOLS7_2\hdle\win32 > EPICPATH=3DC:\Programme\Lattice\ispTOOLS7_2\ispfpga\bin\nt > LM32PATH=3D"C:\isptools\micosystem" > ActiveHDL=3DC:\Programme\Lattice\ispTOOLS7_2\active-hdl\bin > [Symbols] > DeviceFamily=3DORCALDB5_JED_T_VHD > ProjectType=3DDevice > ToolMenu=3DORCATLM32REVEAL > CurrentProject=3DC:\Dokumente und Einstellungen\Administrator\Eigene > Dateien\Lattice\pcie_easi.syn > EntryType=3DPure VHDL > FlowType=3DNORMAL > Simulator=3DActiveHDL > RevealInsert=3Dfalse > UseDefinedSymbols=3Dc:\dokumente und einstellungen\administrator\eigene > dateien\lattice\pcie_easi.iniArticle: 143203
On Sep 25, 9:49=A0am, George <bishop...@gmail.com> wrote: > On Sep 25, 9:39=A0am, George <bishop...@gmail.com> wrote: > > > I'm using the mpmc controller. =A0I thought the burst size of the ddr > > was 4 words, and I don't see any way to change this in the mpmc > > interface. > > > Thanks, > > George > > Sorry, I retract that previous statement. =A0I see in the datasheet that > the burst length can be programmed to 2,4,or 8. Just be careful to set the chip burst size for the appropriate number of 32-bit "words" so your 64-bit interface has the burst size you want. Generally the internal buses run at single data rate and twice the device data width, so a burst of 8 as defined by the chip's mode register means 4 double-wide words internal to the FPGA.Article: 143204
Great news, We have been waiting for something like this for years (the gcc hack is particularly welcome). Steven James Robinson a écrit : > We'd like to announce the release of a 'super small' soft processor > core. The goal of our project/core is to make the smallest possible > FPGA area footprint processor (for now, on Altera FPGAs) that is > compatible with MIPS binaries. It is a bit-serial processor in > implementation, although the interface is completely 32-bit, and so very > slow. It comes in a two flavours, one with exceptions, and one without. > > How small? It requires 236 Stratix III ALUTs/336 registers/207 ALMs with > exceptions enabled, and 142 ALUTs/168 registers/115 ALMs without them. > This compares well with the completely stripped down Nios II/e's scores, > which we measured at 517 ALUTs/311 registers/347 ALMs, making it between > 1.7x and 3.0x smaller than the smallest available Nios II. > > How slow? When run against the eclectic collection of test benchmarks > included with the processor, it was found to be 8-10x slower on average > than a Nios II/e compiled with the same settings. Its clock speed > ranges from 130 MHz for the smallest version to 171 MHz for the largest. > > You can find the release at: > http://www.eecg.toronto.edu/~jayar/software/SuperSmallProcessor/ > > The processor is 2-clause BSD-licensed, so feel free to download it, > play with it, and use it wherever you want. It works great as an Avalon > master, and includes everything you need to use it with SOPC builder. > > Also available on the website is a compiler consisting of a vanilla GNU > toolchain (binutils, gcc, newlib) targeted to MIPS and slightly modified > to avoid multiplies, divides, and unaligned access instructions. > > Unfortunately, the design is currently very Altera-specific: the design > work has only been done on a Stratix III, and it uses Altera's lpm > modules for on-chip ram. As far as we know though, none of these issues > are anything integral to the architecture, so theoretically someone > could port it to Xilinx if they wanted to. > > James Robinson & Jonathan Rose > The Edward S. Rogers Sr. Department of Electrical and Computer Engineering > University of TorontoArticle: 143205
Antti, Well, Thank You. It is unexpected such help but needed. The web sight is elec-real.com, but only a generic business page from Network Solutions is available. I am working on getting someone or myself to get something put together. cyArticle: 143206
bugfinder skrev: > I would like to read the status register and the CRC register using > HWICAP for Virtex 5 using microblaze. > > > #include "hwicap.h" > with > XHwIcap_Type1Read(Register) should work. > > But it gives compilation error saying: "hwicap.h" is not found, and > XHwIcap_Type1Read() not defined. > I am using xilinx ISE 10.1 for development. > > How can I get the updates for these library/include files? > Any help is appreciated. > > Thanks, > buggie Hello bugfinder, Just a side-note to you and all others using the HWICAP core. Since the ICAP is run by the PLB bus clock, the PLB BUS must not run faster than 100 MHz, as 100 MHz is the limit for the ICAP. Run it above 100 MHz and it won't work. There is no warning or anything about this in the datasheet for the core. So beware out there folks ! ;-) FinnArticle: 143207
On Sep 25, 6:54=A0pm, Steven Derrien <sderrienREM...@irisa.fr> wrote: > Great news, > > We have been waiting for something like this for years (the gcc hack is > particularly welcome). > > Steven > > James Robinson a =E9crit : > > > We'd like to announce the release of a 'super small' soft processor > > core. =A0The goal of our project/core is to make the smallest possible > > FPGA area footprint processor (for now, on Altera FPGAs) that is > > compatible with MIPS binaries. =A0It is a bit-serial processor in > > implementation, although the interface is completely 32-bit, and so ver= y > > slow. =A0It comes in a two flavours, one with exceptions, and one witho= ut. > > > How small? It requires 236 Stratix III ALUTs/336 registers/207 ALMs wit= h > > exceptions enabled, and 142 ALUTs/168 registers/115 ALMs without them. > > This compares well with the completely stripped down Nios II/e's scores= , > > which we measured at 517 ALUTs/311 registers/347 ALMs, making it betwee= n > > 1.7x and 3.0x smaller than the smallest available Nios II. > > > How slow? =A0When run against the eclectic collection of test benchmark= s > > included with the processor, it was found to be 8-10x slower on average > > than a Nios II/e compiled with the same settings. =A0Its clock speed > > ranges from 130 MHz for the smallest version to 171 MHz for the largest= . > > > You can find the release at: > > =A0 =A0http://www.eecg.toronto.edu/~jayar/software/SuperSmallProcessor/ > > > The processor is 2-clause BSD-licensed, so feel free to download it, > > play with it, and use it wherever you want. =A0It works great as an Ava= lon > > master, and includes everything you need to use it with SOPC builder. > > > Also available on the website is a compiler consisting of a vanilla GNU > > toolchain (binutils, gcc, newlib) targeted to MIPS and slightly modifie= d > > to avoid multiplies, divides, and unaligned access instructions. > > > Unfortunately, the design is currently very Altera-specific: the design > > work has only been done on a Stratix III, and it uses Altera's lpm > > modules for on-chip ram. =A0As far as we know though, none of these iss= ues > > are anything integral to the architecture, so theoretically someone > > could port it to Xilinx if they wanted to. > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 James Robinson & Jonathan Rose > > The Edward S. Rogers Sr. Department of Electrical and Computer Engineer= ing > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 University of Toronto u are not the only one I am glad i was lazy enough to wait long enough! AnttiArticle: 143208
Where is the burst size set? I see the parameter C_MPMC_CTRL_SUPPORT_BURSTS in the datasheet for the mpmd (which it looks like defaults to 0 in the mpd).Article: 143209
On Sep 24, 7:30=A0am, nobody <cydrollin...@gmail.com> wrote: > Rick, > > You were right, I can not refute you at this time it is $6.10 per > board so it stands no one can do it for $6 a board. Yes, they do a > minimum of $50.00. Still that seems good, no that seems great! > > Cy Care to share who these people are? I've never seen 4-layer pricing this low, for such small quantities. Cy, while your broad-brush concept is commendable, the execution leaves a little to be desired. The Arduino is successful because it's a 80MB download with a free software toolchain, with a great deal of abstraction that removes the need to go through the uC setting registers. If the Arduino had been just a hardware design, it would not have been successful. For your board one needs to download Xilinx's immense webpack and learn the vagaries of HDL. And you're relying on Xilinx's software for synthesis and so on, so while the hardware design may be open, the software toolchain sure ain't. That makes it a good deal less "Free". - MikeArticle: 143210
rickman wrote: > You snipped my quote of > these functions, but they are very different. This is the package declaration. The code is in the package body.Article: 143211
James Robinson <jpr.robinson@utoronto.ca> writes: > We'd like to announce the release of a 'super small' soft processor Nice! Does it have tcl files to integrate it into SOPC builder? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 143212
Thanks for the positive responses. :) You'll find supersmall_hw.tcl, supersmall_noexc_hw.tcl, and supersmall_debug_hw.tcl in the sopcquartus directory, as well as a quartus project file that should have it all already set up. James Robinson On Fri, 2009-09-25 at 20:30 +0200, Petter Gustad wrote: > James Robinson <jpr.robinson@utoronto.ca> writes: > > > We'd like to announce the release of a 'super small' soft processor > > Nice! Does it have tcl files to integrate it into SOPC builder? > > Petter >Article: 143213
On Thu, 24 Sep 2009 16:11:13 -0700 (PDT), Andy wrote: >The VHDL numeric_std package does not force bit 0 = LSB. 'Left is >always MSB. Just like Verilog, yes. >Not sure about the new fixed point types... You can declare them any way you like, but as soon as one of the overloaded operators gets its hands on a fixed-point operand it will throw an assertion error if the subscript range is ascending. So the package effectively enforces the rather reasonable convention that bit number N has place-value 2**N. Verilog can't do that. One up to VHDL, and one of several reasons why (as discussed elsewhere) I regard VHDL as a superior language to Verilog for RTL design (personal opinion only, of course). -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 143214
On Sep 26, 2:02=A0am, James Robinson <jpr.robin...@utoronto.ca> wrote: > It is a bit-serial processor in implementation, Cool. Can it execute from SPI FLASH memory 1/2/4 bits wide ? Can it use the new SPI SRAM ? > How slow? =A0When run against the eclectic collection of test benchmarks > included with the processor, it was found to be 8-10x slower on average > than a Nios II/e compiled with the same settings. =A0Its clock speed > ranges from 130 MHz for the smallest version to 171 MHz for the largest. Nice datapoint. So you are saying this is in the 10-20mips region ? How does the power consumption compare, with a NIOS clock-reduced/ gated to give the same appx MIPs ? -jgArticle: 143215
On Sep 25, 1:51=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > rickman wrote: > > You snipped my quote of > > these functions, but they are very different. > > This is the package declaration. > The code is in the package body. Yes, but they are the documentation. I looked at the bodies, and in the copy I have, dated 1995, the bodies agree with the declaration comments. So it would seem that the functionality of shift_left for signed values changed at some point. I don't know when this package was adopted, so 1995 may be before it was official. But I suspect not. RickArticle: 143216
On Sep 24, 10:30=A0am, nobody <cydrollin...@gmail.com> wrote: > Rick, > > You were right, I can not refute you at this time it is $6.10 per > board so it stands no one can do it for $6 a board. Yes, they do a > minimum of $50.00. Still that seems good, no that seems great! > > Cy But I am afraid that your math is very poor. If they have a minimum order amount of $50, then the price is $50 per board for qty 1. Qty 2 is $25 per board and so on until you reach the floor price of $6.10 at qty 9. However, if they are anything like other PCB houses, the price will continue to drop as the volume goes up and may well drop below $6.10 per board, I can't say for sure though. In reality, I would bet the $6.10 figure is for qty 100 or something similar. It is just too much labor to set up a PCB run to do *any* number of boards for $50, but they may be combining your boards with some others to achieve a lower unit cost. RickArticle: 143217
On Sep 23, 12:57=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 23, 7:38=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Sep 23, 11:58=A0am, nobody <cydrollin...@gmail.com> wrote: > > > > Antti, > > > > I enjoy your responses they are to the bone, but valid. The right > > > people are engineers who wish to pick this project up for their > > > benefit, yes antti as well as mine. The engineer would be some one > > > willing to pay a bit extra for one of four boards available with all > > > the design file associated with the boards. These files are the meat > > > of the work and would allow an engineer to make changes from the > > > current form to one more suitable to their needs, if necessary. Open > > > Source license also allows anyone willing to manufacture this product > > > for sale and profit of their own, royalty free. Development and > > > testing is a huge cost and has been paid for in this project. Yes, > > > antti schematics are available for many of the development boards but > > > firmware and how things are implemented are not. Digilent for example > > > produced a project that only required a usb to miniB connection to th= e > > > board to program utilizing Xilinx's impact program, how did they do > > > that? They will not tell me, I understand, but it was worth asking. > > > Yes, there are vendors who do not make all of their design files > > available for FPGA development boards. =A0But for the most part, the > > FPGA makers provide development boards and make all of their design > > files available. =A0I think they do this to reduce the amount of suppor= t > > required. =A0If you have all of the design files, you don't need to ask > > so many questions, you can just look it up yourself. =A0So in that > > sense, there are a number of open source FPGA development boards. > > Just not with the freedom to make your own copies although I can't > > imagine an FPGA vendor would object since you would be putting their > > parts on it! > > > > If the 4 layer printed circuit board was manufactured for $6 is that > > > to expensive? > > > No one can have a board manufactured for $6. =A0You might be able to ge= t > > 100 for $600 or possibly even 10 for $60, but not 1 for $6. =A0That is > > one of the problems with open source hardware. =A0It is "hard" and ofte= n > > difficult to make on your own. =A0But that does not need to be a > > problem. =A0The most successful open source hardware (OSH) project I > > have seen is the Beagle Board which can only be made in pretty > > advanced factories. =A0It uses a Package on Package mounting technique > > for the processor memory as the OMAP CPU used is intended for use in > > PDAs and cell phone like applications. =A0So clearly, the fact that you > > might have to sell some part or even all of the board would not doom > > the project as Antti might think. =A0(Not trying to put words in your > > mouth Antti, just making a point). > > > In fact, I am thinking about an open source GPS receiver project which > > would require not only the electronic hardware, but also a mechanical > > design be done. =A0Now *that* can be a problem for open source I > > think. > > > > My point: is placing all of this projects work in an open source > > > license to be easily duplicated at a reasonable cost one board under > > > $50.00 for someone in need of well behaved electronic signals, maybe > > > an engineer, a student, a hobbyist, and the like. Antti, you are so > > > preceptive, Yes, I would like to be able to accept notes of > > > appreciation for this body of work, because someone finds it helpful. > > > Being able to discuss this body of work and let it go out to those wh= o > > > would find it useful makes me smile. Open Source Hardware licensing > > > just prevents anyone from strangling the work and making it theirs, > > > plagiarism. This body of work is not quite original but is not a rip > > > off, or a copy of another work. Yes, their are similar projects out > > > there and I have asked for help on this project from those similar > > > project, but understandably I got go away, I did. > > > I have spent my resource on this project and I need more to continue > > > on or even try something different. > > > Have you defined your goals for this project? =A0If you are going to > > succeed, you need to know what you are trying to do, *clearly*. > > Others can give feedback on the goals and you can modify them to > > include as many others as possible. =A0Then you will get as much suppor= t > > as possible. > > > Rick > > Rick, > > beagle is: > 1) backed up by TI > 2) uses (used) newest components > > Cy's design: > 1) uses OBSOLETED and NFND components > > see the difference? > > Cy: doing something different is an option > > And as before i am failing to see what you expect to find? > > I can only sayd that no "open source" developer will be > ordering and assembling those boards for personal use > and no company is interested to produce them either > > so if somebody makes the boards its only you, and then > you have boards with 2 generation too old FPGA that > nobody is interested in, and that you can not sell even > for break even > > Antti I'm not sure what your point is. I am sure there are any number of differences between nobody's project and the beagleboard. So? Why do you think the XC3S250E is an obsolete chip? Heck, every chip will be off the cutting edge in six months. Personally, I prefer to use parts that are not brand new designs, especially with Xilinx. They have a reputation for making their products widely available only a long time after initial shipments to favored customers. Do you have any of the new parts? As to the beagleboard being "backed up" by TI, that really doesn't make much of a difference. I have not seen any indication that the people making them are financially supported by TI. The fact that the board can only be made by rather advanced technology assemblers means you pretty much *have* to buy these boards rather than making your own. I will say that at $150 there is not much incentive to build your own, even if you want 100's. A much smaller board that I am building and selling in qty 100's, with cheaper parts costs me $100 to build. I expect the beagleboard costs close to the selling price, so maybe TI *is* supporting the project in some way. My only problem with the beagleboard is that the power consumption is too high, and that it has no FPGA ;^) I would like something along these lines with an ARM9 processor and memory capable of running Linux, all designed for lowest power so it can run from batteries. Like a PDA I guess, but more than 6 hours of run time, more like 20 hours with a PDA sized display. I wish this was not the FPGA forum. I don't feel I should carry on with this discussion here. There are some display technologies I would like to discuss. Maybe I'll go over to c.a.e and post there... RickArticle: 143218
Hi all, I'm new to this group and I'd like to ask you some help with my design. Actually I'm testing a double median filter implemented in a Virtex5 FPGA. To chek it in different situation I tought to use an ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) and use them as stimuli for my device, finally storing the output (32 x 1 x 1024bit) in another ILA core. The data I'd like to use for this test are stored in .txt files. The point is: 1) Is it possible to pass data from a .txt file to a ILA core? 2) If so, can you suggest me how to do that? Thanks all DekArticle: 143219
On 23 Set, 13:20, "sreedevi1988" <sreedevi1...@gmail.com> wrote: > Hello, > > I am trying to implement a fir filter in vhdl.. i want to put the output > sequence into a text file, so that I can use the same text file in MATLAB > and check the frequency response.. The problem I am facing is;;when I try > to simulate thro Modelsim, it gives the following errors... > > # ** Warning: fir_low.vhd(57): (vcom-1194) FILE declaration was written > using VHDL 1987 syntax. > # ** Error: fir_low.vhd(89): No feasible entries for subprogram "write". > # ** Error: fir_low.vhd(90): No feasible entries for subprogram > "writeline". > # ** Error: fir_low.vhd(94): VHDL Compiler exiting > # ** Error: C:/Modeltech_xe_starter/win32xoem/vcom failed. > > Pls help me out in this regard. > > Thank you, > Sreedevi If you didn't solve the problem yet, try to post the post the piece of code Bye DekArticle: 143220
On Sep 26, 4:59=A0pm, Dek <daniele.deq...@gmail.com> wrote: > Hi all, > > I'm new to this group and I'd like to ask you some help with my > design. Actually I'm testing a double median filter implemented in a > Virtex5 FPGA. To chek it in different situation I tought to use an > ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) and > use them as stimuli for my device, finally storing the output (32 x 1 > x 1024bit) in another ILA core. The data I'd like to use for this test > are stored in .txt files. The point is: > > 1) Is it possible to pass data from a .txt file to a ILA core? > 2) If so, can you suggest me how to do that? > > Thanks all > > Dek You can't pass data to an ILA core. However, you can export the data already stored in ILA core to a text file. Cheers, Jim http://myfpgablog.blogspot.com/Article: 143221
On 27 Set, 01:32, Jim <jimw...@gmail.com> wrote: > On Sep 26, 4:59=A0pm, Dek <daniele.deq...@gmail.com> wrote: > > > > > > > Hi all, > > > I'm new to this group and I'd like to ask you some help with my > > design. Actually I'm testing a double median filter implemented in a > > Virtex5 FPGA. To chek it in different situation I tought to use an > > ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) and > > use them as stimuli for my device, finally storing the output (32 x 1 > > x 1024bit) in another ILA core. The data I'd like to use for this test > > are stored in .txt files. The point is: > > > 1) Is it possible to pass data from a .txt file to a ILA core? > > 2) If so, can you suggest me how to do that? > > > Thanks all > > > Dek > > You can't pass data to an ILA core. However, you can export the data > already stored in ILA core to a text file. > > Cheers, > Jimhttp://myfpgablog.blogspot.com/- Nascondi testo citato > > - Mostra testo citato - Thanks for you reply before my hopes finally vanish I ask you if you know another way to do what I meant. Anyway, the idea of storing data to be used as stimuli inside the FPGA block-RAM came to me listening to several tutorials, in which I heard that using ChipScope you can place stimuli inside the FPGA, and store the output. Now I can't figure how I can do that whithout storing those stimuli in block-RAM. Thanks DekArticle: 143222
Dek wrote: > I'm new to this group and I'd like to ask you some help with my > design. Actually I'm testing a double median filter implemented in a > Virtex5 FPGA. To chek it in different situation I tought to use an > ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) and > use them as stimuli for my device, finally storing the output (32 x 1 > x 1024bit) in another ILA core. The data I'd like to use for this test > are stored in .txt files. The point is: > > 1) Is it possible to pass data from a .txt file to a ILA core? > 2) If so, can you suggest me how to do that? I would write a VHDL testbench and run it in the ISE ISim Simulator. If you really want to test it in real hardware, you could write a simple entity with ROM data for testing your entity. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 143223
On Sep 27, 3:44=A0am, Dek <daniele.deq...@gmail.com> wrote: > On 27 Set, 01:32, Jim <jimw...@gmail.com> wrote: > > > > > On Sep 26, 4:59=A0pm, Dek <daniele.deq...@gmail.com> wrote: > > > > Hi all, > > > > I'm new to this group and I'd like to ask you some help with my > > > design. Actually I'm testing a double median filter implemented in a > > > Virtex5 FPGA. To chek it in different situation I tought to use an > > > ChipScope Pro ILA core to store a set of data (32 x 10 x 1024 bit) an= d > > > use them as stimuli for my device, finally storing the output (32 x 1 > > > x 1024bit) in another ILA core. The data I'd like to use for this tes= t > > > are stored in .txt files. The point is: > > > > 1) Is it possible to pass data from a .txt file to a ILA core? > > > 2) If so, can you suggest me how to do that? > > > > Thanks all > > > > Dek > > > You can't pass data to an ILA core. However, you can export the data > > already stored in ILA core to a text file. > > > Cheers, > > Jimhttp://myfpgablog.blogspot.com/-Nascondi testo citato > > > - Mostra testo citato - > > Thanks for you reply > > before my hopes finally vanish I ask you if you know another way to do > what I meant. Anyway, the idea of storing data to be used as stimuli > inside the FPGA block-RAM came to me listening to several tutorials, > in which I heard that using ChipScope you can place stimuli inside the > FPGA, and store the output. Now I can't figure how I can do that > whithout storing those stimuli in block-RAM. > > Thanks > > Dek Chipscope has a VIO core that you can use to drive signals inside FPGA. The stimulus for the VIO are not stored in BRAMs. They are directly controlled by the user via Chipscope (GUI or script). There are several options for what you want to do: * If your stimulus is static, you can use CoreGen to generate a ROM with an initialization data file. You then instantiate this ROM is your design to generate the bitstream. * If your stimulus is not static (i.e. you want to change the data in the ROM after the bitstream is generated), you can use data2mem program (http://www.xilinx.com/support/documentation/sw_manuals/ xilinx11/data2mem.pdf) * Based on what you're doing, I highly recommend you use Matlab Simulink and System Generator (SysGen). You can run hardware cosimulation with SysGen, which you can send data directly to the hardware from Simulink environment. Cheers, Jim http://myfpgablog.blogspot.com/Article: 143224
"Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:
>On Sep 23, 10:47=A0pm, "Antti.Luk...@googlemail.com"
><antti.luk...@googlemail.com> wrote:
>> On Sep 23, 10:41=A0pm, nobody <cydrollin...@gmail.com> wrote:
>>
>>
>>
>> > Antti,
>>
>> > You have it all figured dont ya, Nobody, nothing, no company, no
>> > interest. Well, seems as if two others have joined in to express some
>> > interest.
>>
>> > =A0I agree the mating components, 4 connectors, used on the board for
>> > stacking the boards are expensive and therefore need to rethink
>> Antti
>> PS I am not as negative just trying to help you,
>> and yes i have pretty much figured out
>
>i must correct myself
>
>s3e: no failsafe multiboot in SPI flash without external circuitry
Whats the problem with that? The only limitation of this board is that
you need an external JTAG interface to program it. It would be nicer
to have JTAG thru the FTDI chip. That way you'll always have a
fallback.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
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