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On Sep 3, 2:43=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > > So you would never recommend VHDL to an Ada programmer would you? I would still recommend VHDL, but I couldn't very well use that argument. AndyArticle: 142851
On Sep 3, 5:22=A0pm, Johnson <gpsab...@yahoo.com> wrote: > Mark McDougall wrote: > > Johnson wrote: > > >> Could anybody please show me a list of popular FPGA development > >> IDE/toolchains and their approximate costs? > > > Your choice of silicon more-or-less dictates the development tools you'= ll > > be using. Yes, there are 3rd party synthesis tools but for "entry level > > development" you're most likely looking at standard silicon vendor pack= ages. > > > As for choosing silicon, unless you have an application that can take > > advantage of a specific feature, the decision is to some degree a > > "religious" one. Sometimes the choice is even based on the development > > tools rather than the actual silicon. > > > So your questions are, to a large degree, "not applicable". For > > entry-level, mainstream development you choose your silicon and you're > > stuck with the vendor tools as supplied. > > > Regards, > > Good and thanks. So what is the most "religious" FPGA silicon for now? I > guess Zarlink, right? And what is the most popular development tools of > Zarlink products to entry-level developers? You mean Xilinx? The top two are pretty close in design wins and tend to leap-frog eachother on each process node. The other is of course Altera. The pack running behind those two includes Lattice, Actel, and a lot of smaller players. Go to the websites of the manufacturers to find the free software options, usually called a "web-pack" or something similar. Regards, GaborArticle: 142852
On Sep 3, 6:11=A0am, "august22nd" <emily.mo...@gmail.com> wrote: > >Hello FPGA Gurus! > >I have just bought Xilinx ML507 board in order to learn Xilinx FPGAs and > ISE > >tools. Latest experience with XC3130 FPGAs was 13 years ago, but those > chips > >and tools were very easy to use. > >I was able to run all demos, I have downloaded all possible docs and > >refernce designs from Xilinx site for ML505 and ML507 boards. However, > all > >these demos include precompiled .ACE and .BIT (some of them) files > already, > >and there is no source where I can start and learn from, otherwise the > board > >is of no use for me. > >Can you help me and advise where I can get a source for a least HELLO > WORLD > >demo &!!! > > >Many thanks, > >Regards, > >Pavel > > Did you ever find any?- Hide quoted text - > > - Show quoted text - http://www.xilinx.com/ml507 -> Reference Designs or directly at http://www.xilinx.com/products/boards/ml507/reference_designs.htm Ed McGettigan -- Xilinx Inc.Article: 142853
On Sep 3, 1:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > http://shop.trenz-electronic.de/catalog/product_info.php?products_id=3D..= . > > first S6 boards arrived today, so its finally there(here)! > > well well well the DIP modules from OHO are also orderable now! > I had them reviewed in the brain a few month ago, nice to see > them released and online > > http://shop.trenz-electronic.de/catalog/default.php > > Antti > brain issue August is out too :)http://groups.google.com/group/antti-brai= n/files?hl=3Den The SP601 started shipping in volume last week. I've been waiting for an Antti post saying that you had yours as I thought that I saw a post that you had ordered one. :-) I know that there were ordering/delivery problems in the past with Spartan-3 boards, but you won't see any of those issues this time around. Ed McGettigan -- Xilinx Inc.Article: 142854
On Sep 3, 3:12=A0pm, gabor <ga...@alacron.com> wrote: > On Sep 3, 5:22=A0pm, Johnson <gpsab...@yahoo.com> wrote: > > > > > > > Mark McDougall wrote: > > > Johnson wrote: > > > >> Could anybody please show me a list of popular FPGA development > > >> IDE/toolchains and their approximate costs? > > > > Your choice of silicon more-or-less dictates the development tools yo= u'll > > > be using. Yes, there are 3rd party synthesis tools but for "entry lev= el > > > development" you're most likely looking at standard silicon vendor pa= ckages. > > > > As for choosing silicon, unless you have an application that can take > > > advantage of a specific feature, the decision is to some degree a > > > "religious" one. Sometimes the choice is even based on the developmen= t > > > tools rather than the actual silicon. > > > > So your questions are, to a large degree, "not applicable". For > > > entry-level, mainstream development you choose your silicon and you'r= e > > > stuck with the vendor tools as supplied. > > > > Regards, > > > Good and thanks. So what is the most "religious" FPGA silicon for now? = I > > guess Zarlink, right? And what is the most popular development tools of > > Zarlink products to entry-level developers? > > You mean Xilinx? > > The top two are pretty close in design wins and tend to leap-frog > eachother on each process node. =A0The other is of course Altera. > > The pack running behind those two includes Lattice, Actel, and > a lot of smaller players. > > Go to the websites of the manufacturers to find the free software > options, usually called a "web-pack" or something similar. > > Regards, > Gabor- Hide quoted text - > > - Show quoted text - A few links for the latest from Xilinx. FPGAs Virtex-6 http://www.xilinx.com/products/virtex6/index.htm Spartan-6 http://www.xilinx.com/products/spartan6/index.htm Design Software ISE 11.1 http://www.xilinx.com/tools/designtools.htm Free Eval http://www.xilinx.com/ise_eval/index.htm Boards Spartan-6 SP601 http://www.xilinx.com/products/devkits/EK-S6-SP601-G.htm Virtex-6 ML605 http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm Ed McGettigan -- Xilinx Inc.Article: 142855
gabor wrote: > On Sep 3, 5:22 pm, Johnson <gpsab...@yahoo.com> wrote: >> Mark McDougall wrote: >>> Johnson wrote: >>>> Could anybody please show me a list of popular FPGA development >>>> IDE/toolchains and their approximate costs? >>> Your choice of silicon more-or-less dictates the development tools you'll >>> be using. Yes, there are 3rd party synthesis tools but for "entry level >>> development" you're most likely looking at standard silicon vendor packages. >>> As for choosing silicon, unless you have an application that can take >>> advantage of a specific feature, the decision is to some degree a >>> "religious" one. Sometimes the choice is even based on the development >>> tools rather than the actual silicon. >>> So your questions are, to a large degree, "not applicable". For >>> entry-level, mainstream development you choose your silicon and you're >>> stuck with the vendor tools as supplied. >>> Regards, >> Good and thanks. So what is the most "religious" FPGA silicon for now? I >> guess Zarlink, right? And what is the most popular development tools of >> Zarlink products to entry-level developers? > > You mean Xilinx? > > The top two are pretty close in design wins and tend to leap-frog > eachother on each process node. The other is of course Altera. > > The pack running behind those two includes Lattice, Actel, and > a lot of smaller players. > > Go to the websites of the manufacturers to find the free software > options, usually called a "web-pack" or something similar. > > Regards, > Gabor Yes, Xilinx. Thanks for correcting me.Article: 142856
On Sep 3, 11:42=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Sep 3, 8:47=A0am, 2G <soar2mor...@yahoo.com> wrote: > > > > > > > On Sep 2, 6:55=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Sep 2, 11:49=A0am, 2G <soar2mor...@yahoo.com> wrote: > > > > > On Sep 2, 11:10=A0am, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.co= m> > > > > > wrote: > > > > > > >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. = The V5 > > > > > >is loading the recovered clock signal with an apparent impedance= of 50 > > > > > >ohms (measured by the voltage drop across a series resistor). Th= is is > > > > > >dropping the voltage swing of the signal in half. We have tried = a > > > > > >different input pin with no change. We then added a buffer with = no > > > > > >change. The ucf for that input is: > > > > > > >NET "RX_CLK" LOC =3D "G15" | IOSTANDARD =3D LVCMOS25; > > > > > > >This is not happening to any of the other inputs from the SERDES= . > > > > > > >Any ideas as to what is going on? > > > > > > Did you check the board schematics? This signal seems to be conne= cted > > > > > to the CPLD also which might be causing the issue you see. > > > > > > -- > > > > > Muzaffer Kal > > > > > > DSPIA INC. > > > > > ASIC/FPGA Design Services > > > > > >http://www.dspia.com > > > > > Yes, we are aware of that. We previously used AJ32 and had the same > > > > problem. We used it because it was the only global clock input > > > > available (ISE kept complaining about using that input for a clock > > > > source). If need be, we can isolate the CPLD and LED from that line > > > > (we removed the LED and got no change). > > > > > We just tried rerouting that signal to the USER_CLK after removing = the > > > > oscillator (X1). This greatly improved the signal quality, but > > > > requires a flying wire off of our mezzanine board to make the > > > > connection.- Hide quoted text - > > > > > - Show quoted text - > > > > How are you physically connecting the TLK2501 to the ML507? > > > > Ed McGettigan > > > -- > > > Xilinx Inc.- Hide quoted text - > > > > - Show quoted text - > > > The TLK2501 is on a mezzanine board that interconnects thru the > > expansion headers (J4-7).- Hide quoted text - > > > - Show quoted text - > > Looking back at your posts you started out using AJ32, HDR1_46, and > then switched to G15, GPIO_LED_2, and both of these have an issue with > "dropping the voltage in half" for the RX_CLK output from the TLK2501. > > AJ32 is in Bank 13 and is connected to the VCCO_EXP supply and is not > GC or CC clock input pin. =A0Did you set the VCCO_EXP supply to 2.5V > using the J20 jumpers? =A0Is AK32, HDR1_48, used on the TLK2501 board? > > G15 is in Bank =A01 is connected to VCC2V5 this is a GC clock input, but > it is also connected to the input of the CPLD and the signal integrity > will be reduced. Is G16, GPIO_LED_3 used on the TLK2501 board? > > Have you verified that the problem isn't on the TLK2501 board?- Hide quot= ed text - > > - Show quoted text - Thanks for the reply. I checked and it was set to 3.3V, so we changed it to 2.5V and got the same SI problems, but the bit error went away (due no doubt to the change in threshold levels). The clock signal itself looks terrible: its low level is raised to 1.32 V (the high level is 2.5 V), with a 0.15 V glitch on the rising edge at the mid point. AK32 is used for RXD<8>. We have isolated the clock signal on the TLK2501 board and it looks fine. We tried using a different input entirely (HDR1_2, H33) and got the same results. I generated the IBIS file for this design and noted that the same IO standard, LVCMOS25_S_2, is used for all inputs from the TLK2501, yet the SI problem is exclusive to RX_CLK. The buffer used, an SL74LVC8T245, is capable of sinking 8 mA with a 2.5 V supply while keeping Vol to 0.3 V max. Doing the math, this implies there is an equivalent pull-up of about 33 ohms on that line! TomArticle: 142857
Ed McGettigan wrote: > A few links for the latest from Xilinx. Thanks Father Ed from the Church of Xilinx! ;) The other major player is Altera... <http://www.altera.com/> Devices: <http://www.altera.com/products/devices/dev-index.jsp> Design Software (Quartus, Web (a.k.a. free) Edition) <http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html> Dev Boards: <http://www.altera.com/products/devkits/kit-dev_platforms.jsp> <http://www.altera.com/products/devkits/kit-dev_platforms_partner.jsp> Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 142858
Mike Harrison wrote: > ..although as writing HDL is so different from programming, perhaps a > _more_ different language would help reinforce the differences.... Actually, that's a _very_ good point. And to weigh in with my $0.02 worth on the Verilog vs VHDL debate... My "preference" is VHDL, but I suspect that has a lot to do with the fact that the requirements for our first major FPGA project stipulated that the design be coded in VHDL as far as possible. So I find most of my synthesizable code is done in VDHL to this day. Interestingly, said project included some 3rd party cores, one of which was written in Verilog with a very large and complex testbench. We ended up expanding on that testbench to encompass the whole design. And so I found my preference for writing testbench code was in Verilog, rather than VHDL. And I would maintain that IMHO it's _definitely_ quicker and easier to write testbenches in Verilog. Subsequently, I found myself continuing this pattern on later projects - VHDL for synthesizable modules with a Verilog testbench for simulation. However, more recently I've forced myself to write testbench code in VHDL as well - mainly to simplify development requirements and ease the burden on my poor brain cells. But it's definitely an advantage to be conversant in both - and I do still find it necessary to modify the odd Verilog core. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 142859
"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:h7p82b$mgn$1@naig.caltech.edu... > Andy <jonesandy@comcast.net> wrote: > (snip on verilog and VHDL) > > < (Other than my personal bias) : Given the differences between coding > < for SW and coding for HW, VHDL is better at keeping a new user from > < making some ignorant mistakes. A new designer with a SW background is > < more likely to make typical "SW" mistakes in a language that looks > < more like the SW he is used to. Sometimes keeping the syntax apart > < helps in this regard. On the other hand, if one's SW background is in > < ada, you could make exactly the same argument in favor of verilog ;^) > > I don't agree, but I believe it could be personal preference. > For one, I did some logic design with TTL gates before learning > verilog, so I know how to think in terms of logic. > > Verilog isn't really that much like C. There are people using > C as an HDL, and I completely agree that is a bad idea. Don't be too quick to dismiss C for HDL, there are lots of companies that develop algorithms in Matlab/C/C++/SC and then pass it on to a poor engineer to "quickly" translate into VHDL/Verilog. Then a month later they require the same algorithm but 5 times faster or with a "subtle change" which normally results (requires) a costly redesign. For those applications you really want to use an untimed language like C/C++ and use a tool (CatapultC/BlueSpec/ Forte/Synfora/etc...) to do all the design exploration (resource mapping/adding pipelines/concurrency/etc) for you. Given the progress these tools are making (most can now also handle control path as well) and the amount of money companies like Intel/AMD are pouring into sequential to concurrent research I wouldn't be surprise if the future of RTL is neither VHDL nor Verilog..... Hans www.ht-lab.comArticle: 142860
On Fri, 04 Sep 2009 10:24:26 +1000, Mark McDougall wrote: >VHDL for synthesizable modules with a Verilog >testbench for simulation. Couldn't agree more. Even after the SystemVerilog enhancements, VHDL is a demonstrably superior language for RTL design - I can go into *much* more detail if you want, but I strongly suspect you don't want :-) But Verilog, and especially SystemVerilog, makes testbenches very, very much easier than VHDL. >it's definitely an advantage to be conversant in both Again, I agree strongly. However, many folks don't have the luxury of tools that support mixed-language simulation, and most folks don't have the luxury of tools that support SystemVerilog simulation. Back to the real world :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 142861
On Sep 3, 1:27=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Antti <antti.luk...@googlemail.com> wrote: > > Hi > > Uwe, (and others) what should i do (how high to jump, etc) to get USB > > Blaster officially supported by XC3sprog? > > urjtat already supports it, and xc3sprog supports partially drivers > > from urjag, so i think my plea isnt so complicated to fulfill? > > and yes i can donate some usb gadgets to the xc3sprog developers, (or > > to any one who adds the support) > > hm, basically the offer is valid to any developers adding usb blaster > > support to some open or closed software..:) > > OpenOCD lacks usb blaster support as well, and i think some more jtag > > software also... > > (sorry for the delay, I was on vacation) > > There are at several possibilities: > - write the low level support driver yourself. No too hard if you look ho= w > the xc3sprog xpc-driver was ripped of the urjtag xpc-driver > - lend me a USB Blaster and hope that I find time to write the driver > - hope that I find time and that I write the the driver without the > hardware. Feedback on some probably non-working intermediate step will be > welcome. > > Bye > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Hi Uwe, ok so: the gagdet: U2TOOL mini spec 1) FT245RQ + FPGA module (can be different, first will use A3P060 modules) 2) FPGA: hard wired USB blaster emulation mode 3) full PIN-SWAP soft controlled MUX 4) free running clock can be output on any selected pin 5) soft controlled pullup OR pulldown resistors (4.7K) 6) AP32 soft core (AVR compatible) that can "take over" and implement custom protocols locally in the gadget 7) some small extras for frequency counter function and maybe PLL I know that USB blasters are selling for $39, so I have real hard competition if i want to sell this tool, but well so far i only dreamed of having a USB blaster and now i have one, one that is a litte bit more then just the blaster xc3sprog: I offered "donation of gadgets" that is I would send the gadget with free shipping for you to KEEP. it is REALLY boring to work with hardware you dont have on your desk. its doable, but boring. I would suggest to add support in "generic mode" that is using FTDI defautl VID/PID and all stock drivers of course reprogramming the eeprom to altera mode makes the gadget to be recognized by all tools that support usb blaster natively I have written linux soft and low level drivers, so i could do it all myself, but i prefer that give this task out to those who can do it better (also better integration and coding style), so I will be happy to donate those gadgets (specially if it is all that is needed from me). Much money up front is not available, the all project may not pay back for me at all. AnttiArticle: 142862
ganeshstha wrote:
> Hi,
> I am new to the FPGA world. I am using chipcon CC2400 board and has the
> Xilinx's XC2S200E FPGA. Is it possible to program it program the FPGA in
> C?
> I donot have any experience in VHDL and verilog.
http://www.myhdl.org/doku.php/why
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Article: 142863Ed McGettigan <ed.mcgettigan@xilinx.com> wrote: > On Sep 3, 1:45 am, Antti <antti.luk...@googlemail.com> wrote: > > http://shop.trenz-electronic.de/catalog/product_info.php?products_id=... > > > > first S6 boards arrived today, so its finally there(here)! > > > > well well well the DIP modules from OHO are also orderable now! > > I had them reviewed in the brain a few month ago, nice to see > > them released and online > > > > http://shop.trenz-electronic.de/catalog/default.php > > > > Antti > > brain issue August is out too :)http://groups.google.com/group/antti-brain/files?hl=en > The SP601 started shipping in volume last week. I've been waiting for > an Antti post saying that you had yours as I thought that I saw a post > that you had ordered one. :-) > I know that there were ordering/delivery problems in the past with > Spartan-3 boards, but you won't see any of those issues this time > around. With Digikey, the SP601 is is on status "Call"... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 142864
On Sep 4, 12:57=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > On Sep 3, 1:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > > >http://shop.trenz-electronic.de/catalog/product_info.php?products_id= =3D... > > > > first S6 boards arrived today, so its finally there(here)! > > > > well well well the DIP modules from OHO are also orderable now! > > > I had them reviewed in the brain a few month ago, nice to see > > > them released and online > > > >http://shop.trenz-electronic.de/catalog/default.php > > > > Antti > > > brain issue August is out too :)http://groups.google.com/group/antti-= brain/files?hl=3Den > > The SP601 started shipping in volume last week. =A0I've been waiting fo= r > > an Antti post saying that you had yours as I thought that I saw a post > > that you had ordered one. :-) > > I know that there were ordering/delivery problems in the past with > > Spartan-3 boards, but you won't see any of those issues this time > > around. > > With Digikey, the SP601 is is on status "Call"... > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- try: 1-CALLDIGIKEY use spock-communicator! EU stock is currently empty ASFAIK, I suppose US stock also by now, at time of posting it wasnt. but as Ed also confirmed the mockup with S3x delivery isnt gonna repeat this time. meaning the boards should be shipping now without major delays..(?) (we all hope) Antti PS I reported as soon as I had confirmation of first SP601 been seen in EU/Germany. and Ed, NO the board isnt yet on my desk. I do have patience this time :)Article: 142865
"hussnain721" <hussnain721@hotmail.com> writes: > Hi all ! > I need your help and assistance for the configuration of Multiple > Microblaze on FSL link. Does anyone has any document regarding this > problem? Or can anyone guide me using example how multiple microblaze are > communicated on FSL link? On a single FSL, they can't - FSL is a one-to-one link. You will need one FSL per processor that you want to link to. Then just wire them all up. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 142866
On Sep 4, 2:56=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Fri, 04 Sep 2009 10:24:26 +1000, Mark McDougall wrote: > >VHDL for synthesizable modules with a Verilog > >testbench for simulation. > > Couldn't agree more. =A0Even after the SystemVerilog > enhancements, VHDL is a demonstrably superior language > for RTL design - I can go into *much* more detail > if you want, but I strongly suspect you don't want :-) > > But Verilog, and especially SystemVerilog, makes > testbenches very, very much easier than VHDL. Hi, Jonathan. Actually, I would benefit from an elucidation on why VHDL is superior to SystemVerilog for RTL design. I shifted into Verilog, because I came from an analog background and I was familiar with Verilog-A. I've recently hired a seasoned VHDL designer, and we're trying to determine which language to code in as a general rule (leaving room for warranted exceptions, of course). Based on this: http://www.systemverilog.org/techpapers/date04_systemverilog= .pdf I was under the impression that SystemVerilog is now up to speed with VHDL on all the usage scenarios that Verilog lacked. I realize a lot of these decisions come from personal experience and preference. However, I want to be open to all points of view given that I can't predict what my future experience will be.Article: 142867
On Sep 4, 6:14=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 4, 12:57=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > > darmstadt.de> wrote: > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > On Sep 3, 1:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > >http://shop.trenz-electronic.de/catalog/product_info.php?products_id= =3D... > > > > > first S6 boards arrived today, so its finally there(here)! > > > > > well well well the DIP modules from OHO are also orderable now! > > > > I had them reviewed in the brain a few month ago, nice to see > > > > them released and online > > > > >http://shop.trenz-electronic.de/catalog/default.php > > > > > Antti > > > > brain issue August is out too :)http://groups.google.com/group/antt= i-brain/files?hl=3Den > > > The SP601 started shipping in volume last week. =A0I've been waiting = for > > > an Antti post saying that you had yours as I thought that I saw a pos= t > > > that you had ordered one. :-) > > > I know that there were ordering/delivery problems in the past with > > > Spartan-3 boards, but you won't see any of those issues this time > > > around. > > > With Digikey, the SP601 is is on status "Call"... > > -- > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-d= armstadt.de > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > try: > > 1-CALLDIGIKEY > > use spock-communicator! > > EU stock is currently empty ASFAIK, > I suppose US stock also by now, at time of posting it wasnt. > > but as Ed also confirmed the mockup with S3x delivery isnt gonna > repeat this time. > meaning the boards should be shipping now without major delays..(?) > (we all hope) > > Antti > > PS I reported as soon as I had confirmation of first SP601 been seen > in EU/Germany. > and Ed, NO the board isnt yet on my desk. I do have patience this > time :) I received my SP601 from Nu Horizons earlier in the week. I have not had time to play with it yet but it has enough bells and whistles to keep me amused once I free up some time. George.Article: 142868
On Sep 4, 3:54=A0am, Poojan Wagh <poojanw...@gmail.com> wrote: > On Sep 4, 2:56=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > > On Fri, 04 Sep 2009 10:24:26 +1000, Mark McDougall wrote: > > >VHDL for synthesizable modules with a Verilog > > >testbench for simulation. > > > Couldn't agree more. =A0Even after the SystemVerilog > > enhancements, VHDL is a demonstrably superior language > > for RTL design - I can go into *much* more detail > > if you want, but I strongly suspect you don't want :-) > > > But Verilog, and especially SystemVerilog, makes > > testbenches very, very much easier than VHDL. > > Hi, Jonathan. > > Actually, I would benefit from an elucidation on why VHDL is superior > to SystemVerilog for RTL design. I shifted into Verilog, because I > came from an analog background and I was familiar with Verilog-A. I've > recently hired a seasoned VHDL designer, and we're trying to determine > which language to code in as a general rule (leaving room for > warranted exceptions, of course). > > Based on this:http://www.systemverilog.org/techpapers/date04_systemverilo= g.pdf > I was under the impression that SystemVerilog is now up to speed with > VHDL on all the usage scenarios that Verilog lacked. I realize a lot > of these decisions come from personal experience and preference. > However, I want to be open to all points of view given that I can't > predict what my future experience will be. I think we can agree on one thing - Verilog and VHDL are like toothpaste. You'll have a favorite, but you'll tolerate the other if you have to. The real problem I see is that no matter what the language, at some point you have to deal with clock domain crossing, meta-stability, setup/hold issues, logic depth, etc. Neither language can eliminate these traps. A newbie who comes into h/ w design from a s/w background probably doesn't appreciate how tricky these problems can be. They focus on the language to use and not what the subtle design problems are. John ProvidenzaArticle: 142869
On Sep 4, 2:57=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > On Sep 3, 1:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > > >http://shop.trenz-electronic.de/catalog/product_info.php?products_id= =3D... > > > > first S6 boards arrived today, so its finally there(here)! > > > > well well well the DIP modules from OHO are also orderable now! > > > I had them reviewed in the brain a few month ago, nice to see > > > them released and online > > > >http://shop.trenz-electronic.de/catalog/default.php > > > > Antti > > > brain issue August is out too :)http://groups.google.com/group/antti-= brain/files?hl=3Den > > The SP601 started shipping in volume last week. =A0I've been waiting fo= r > > an Antti post saying that you had yours as I thought that I saw a post > > that you had ordered one. :-) > > I know that there were ordering/delivery problems in the past with > > Spartan-3 boards, but you won't see any of those issues this time > > around. > > With Digikey, the SP601 is is on status "Call"... > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------- Hide q= uoted text - > > - Show quoted text - I was actually a bit surprised to see non-Xilinx distributors selling the SP601. The first deliveries should be to customers that had pre- ordered with our major distributors, Avnet/Insight/Memec/Silica, NuHorizons and TED. Independent resellers are likely lower on the priority ladder for shipments. Ed McGettigan -- Xilinx Inc.Article: 142870
On Sep 4, 5:45=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Sep 4, 2:57=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > > darmstadt.de> wrote: > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > On Sep 3, 1:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > >http://shop.trenz-electronic.de/catalog/product_info.php?products_id= =3D... > > > > > first S6 boards arrived today, so its finally there(here)! > > > > > well well well the DIP modules from OHO are also orderable now! > > > > I had them reviewed in the brain a few month ago, nice to see > > > > them released and online > > > > >http://shop.trenz-electronic.de/catalog/default.php > > > > > Antti > > > > brain issue August is out too :)http://groups.google.com/group/antt= i-brain/files?hl=3Den > > > The SP601 started shipping in volume last week. =A0I've been waiting = for > > > an Antti post saying that you had yours as I thought that I saw a pos= t > > > that you had ordered one. :-) > > > I know that there were ordering/delivery problems in the past with > > > Spartan-3 boards, but you won't see any of those issues this time > > > around. > > > With Digikey, the SP601 is is on status "Call"... > > -- > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-d= armstadt.de > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------- Hide= quoted text - > > > - Show quoted text - > > I was actually a bit surprised to see non-Xilinx distributors selling > the SP601. =A0The first deliveries should be to customers that had pre- > ordered with our major distributors, Avnet/Insight/Memec/Silica, > NuHorizons and TED. Independent resellers are likely lower on the > priority ladder for shipments. > > Ed McGettigan > -- > Xilinx Inc. Trenz ist Xilinx Alliance Partner und ich dachte die durfen die Xilinx produkte offiziel auch verkaufen? opla :) sprachbarriere... Trenz Electronic GmbH is Xilinx Alliance Partner, and has been selling Xilinx AND Digilent boards for a long time, so I assumed they are authorized to resell Xilinx board products? AnttiArticle: 142871
On Sep 4, 7:54=A0am, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > On Sep 4, 5:45=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Sep 4, 2:57=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > darmstadt.de> wrote: > > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Sep 3, 1:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > >http://shop.trenz-electronic.de/catalog/product_info.php?products_= id=3D... > > > > > > first S6 boards arrived today, so its finally there(here)! > > > > > > well well well the DIP modules from OHO are also orderable now! > > > > > I had them reviewed in the brain a few month ago, nice to see > > > > > them released and online > > > > > >http://shop.trenz-electronic.de/catalog/default.php > > > > > > Antti > > > > > brain issue August is out too :)http://groups.google.com/group/an= tti-brain/files?hl=3Den > > > > The SP601 started shipping in volume last week. =A0I've been waitin= g for > > > > an Antti post saying that you had yours as I thought that I saw a p= ost > > > > that you had ordered one. :-) > > > > I know that there were ordering/delivery problems in the past with > > > > Spartan-3 boards, but you won't see any of those issues this time > > > > around. > > > > With Digikey, the SP601 is is on status "Call"... > > > -- > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu= -darmstadt.de > > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------- Hi= de quoted text - > > > > - Show quoted text - > > > I was actually a bit surprised to see non-Xilinx distributors selling > > the SP601. =A0The first deliveries should be to customers that had pre- > > ordered with our major distributors, Avnet/Insight/Memec/Silica, > > NuHorizons and TED. Independent resellers are likely lower on the > > priority ladder for shipments. > > > Ed McGettigan > > -- > > Xilinx Inc. > > Trenz ist Xilinx Alliance Partner und ich dachte die durfen die Xilinx > produkte offiziel auch verkaufen? > opla :) sprachbarriere... > > Trenz Electronic GmbH is Xilinx Alliance Partner, and has been selling > Xilinx AND Digilent boards > for a long time, so I assumed they are authorized to resell Xilinx > board products? > > Antti- Hide quoted text - > > - Show quoted text - Hi Antti, How much is a piece of the board? And where can I find the board schematical and specification? WengArticle: 142872
On Sep 4, 6:53=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > On Sep 4, 7:54=A0am, "Antti.Luk...@googlemail.com" > > > > <antti.luk...@googlemail.com> wrote: > > On Sep 4, 5:45=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Sep 4, 2:57=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > > darmstadt.de> wrote: > > > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Sep 3, 1:45=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > > >http://shop.trenz-electronic.de/catalog/product_info.php?product= s_id=3D... > > > > > > > first S6 boards arrived today, so its finally there(here)! > > > > > > > well well well the DIP modules from OHO are also orderable now! > > > > > > I had them reviewed in the brain a few month ago, nice to see > > > > > > them released and online > > > > > > >http://shop.trenz-electronic.de/catalog/default.php > > > > > > > Antti > > > > > > brain issue August is out too :)http://groups.google.com/group/= antti-brain/files?hl=3Den > > > > > The SP601 started shipping in volume last week. =A0I've been wait= ing for > > > > > an Antti post saying that you had yours as I thought that I saw a= post > > > > > that you had ordered one. :-) > > > > > I know that there were ordering/delivery problems in the past wit= h > > > > > Spartan-3 boards, but you won't see any of those issues this time > > > > > around. > > > > > With Digikey, the SP601 is is on status "Call"... > > > > -- > > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.= tu-darmstadt.de > > > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmsta= dt > > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------- = Hide quoted text - > > > > > - Show quoted text - > > > > I was actually a bit surprised to see non-Xilinx distributors selling > > > the SP601. =A0The first deliveries should be to customers that had pr= e- > > > ordered with our major distributors, Avnet/Insight/Memec/Silica, > > > NuHorizons and TED. Independent resellers are likely lower on the > > > priority ladder for shipments. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > Trenz ist Xilinx Alliance Partner und ich dachte die durfen die Xilinx > > produkte offiziel auch verkaufen? > > opla :) sprachbarriere... > > > Trenz Electronic GmbH is Xilinx Alliance Partner, and has been selling > > Xilinx AND Digilent boards > > for a long time, so I assumed they are authorized to resell Xilinx > > board products? > > > Antti- Hide quoted text - > > > - Show quoted text - > > Hi Antti, > How much is a piece of the board? And where can I find the board > schematical and specification? > > Weng sp601? here http://www.xilinx.com/products/boards/sp601/reference_designs.htm just order from your preferred disti should not be big diff in price AnttiArticle: 142873
James Harris <james.harris.1@googlemail.com> wrote:
>On 2 Sep, 15:34, Andy <jonesa...@comcast.net> wrote:
>
>...
>
>> But for starters, I would strongly recommend using an HDL like verilog
>> or vhdl, and of those two, I recommend vhdl. Both are supported by the
>> FPGA vendors' free design tools.
>
>Verilog is closer to C and may thus be a little easier for the OP to
>learn.
I strongly disagree. Verilog always looks like a netlist to me. No
beginning - no end. VHDL is much more structured. Agreed Verilog can
leeds to results faster, but VHDL is definitely more powerful.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 142874
Andy <jonesandy@comcast.net> wrote:
>FPGA's are not processors, so FPGA's are not "programmed" by a
>language per se. They are designed, and the design is specified using
>a schematic or a language, usually verilog or vhdl. "Programming" an
>fpga usually refers to downloading the design configuration data into
>the FPGA (i.e. via the JTAG port you mentioned. The FPGA and/or board
>vendor will provide utilities to "program" the FPGA with your design
>configuration data.
I still see no difference between the development flow for a cpu and
an FPGA. Its all about idea -> specification -> implementation ->
verification / testing. The only real difference is that a CPU
executes a program sequentially and an FPGA executes its program in
parallel.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
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