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Messages from 142750

Article: 142750
Subject: Re: program spartan3 under linux
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Sun, 30 Aug 2009 07:44:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 4:47=A0pm, Thorsten Kiefer <tok...@gmx.net> wrote:
> Antti.Luk...@googlemail.com wrote:
> > On Aug 28, 12:51 am, Thorsten Kiefer <tok...@gmx.net> wrote:
> >> Hi,
> >> I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the
> >> Digilent USB/JTAG cable.
> >> I find ISE 11.1 too slow under Windows, so I want to use it with Linux=
.
> >> My question is : is it possible to program the FPGA under Linux ?
> >> Xilprg is too old. Export from digilent is discontinued and not availa=
ble
> >> for Linux.
> >> Are there any alternatives ?
>
> >> Best Regards
> >> Thorsten
>
> > alternative:
> > do not use Digilent [ ]
> > Antti
>
> > I have some products with digilent on board usb and that doesnt work
> > on windows either
> > so i made a firm promise to me not to use the digilent cable whenever
> > possible
> > this doesnt include the XUP cable what is cloned xilinx platform
> > cable, that one work
> > as it is not designed by digilent
>
> Hi,
> thanks for the hint !
> What FPGA vendor and development board would you suggest for
> development on Linux ?
>
> Best wishes
> Thorsten- Hide quoted text -
>
> - Show quoted text -

some additions previous reply

1) in me previous post: "Xilinx USB Cable" means Xilinx USB Platform
Cable or any direct clones of it (made in china or by digilent)

2) soon to be announced U2TOOL uses FT245 and FPGA, and it has altera
usb blaster compatibility mode, this tool would work under linux (also
as Xilinx downloader), but my plans to support linux are also not so
immediate, it just costs too much money (time=3Dmoney!) to develop for
linux, much more then providing tools that work in win boxes

usb blaster is like jtag eingine over usb-uart so the support for
linux should be simple (as long as FTDI drivers can be installed of
course)

Antti





Article: 142751
Subject: Re: program spartan3 under linux
From: Frank Buss <fb@frank-buss.de>
Date: Sun, 30 Aug 2009 17:09:59 +0200
Links: << >>  << T >>  << A >>
Antti.Lukats@googlemail.com wrote:

> Option 1:
> Get a PC with preinstalled WinXP/Vista and forget the attempts to use
> FPGA tools under linux
> This option saves lots of frustration and is worth the money spent

I use Windows, too, but maybe a VMWare, or with another virtualization
software, you don't need at least an extra PC (I'm using this on my desktop
PC to run Debian Linux in VMWare, which works fine). Or install Linux and
Windows on one PC with a bootmanager like Grub (this is my Laptop setup),
but Murphy's Law says, that you just need some program for Linux fast (e.g.
phone call from a customer and you have to check something) when Windows is
booted and vice versa :-)

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 142752
Subject: Re: Does ModelSim or any simulator software have a function similar
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sun, 30 Aug 2009 08:29:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 12:48=A0am, "HT-Lab" <han...@ht-lab.com> wrote:
> "Weng Tianxiang" <wtx...@gmail.com> wrote in message
>
> news:59730a19-3192-4625-97dc-491f71a5cfb9@p10g2000prm.googlegroups.com...
> On Aug 29, 1:07 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
> ..
>
> >Hi Jonathan,
> >I have a project continuously running more than 20 days to get an
> >error.
>
> 20 days in my book sounds totally unworkable, are you using an OEM versio=
n of
> Modelsim? In that case you might have hit the OEM limit and Modelsim will=
 simply
> grind to a halt (1% of PE). If you explain what you are trying to do than=
 you
> might get some useful suggestions on how to improve your simulation time.
>
> >In my project I have many assert statements to make sure the
> >design is going well. If there is an error, the design stops.
>
> >But I couldn't open the waveform window under ModelSim when starting
> >the simulation, the reason is very simple: any size of hard disk would
> >be filled up within one day simulation.
>
> You can also turn logging off (-nolog) for say the first 19 days and turn=
 it
> back on again on day 20. You can also use the WLFSizeLimit =A0variable to=
 limit
> the wlf file size (see manual/modelsim.ini).
>
> >I would like the ModelSim or other simulation software to have the
> >following function:
> >It has two windows to accept two numbers to specify how many clocks
> >before and after the point where assert statement fails to generate
> >waveform window data.
>
> That is a good option, log an Enhancement Request with Mentor. However, t=
he
> WLFTimeLimit variable might be able to help you (not tried myself)
>
> ; Limit WLF file by time, as closely as possible,
> ; to the specified amount of simulation time. When the limit is exceeded
> ; the earliest times get truncated from the file.
> WLFTimeLimit =3D {100 ms}
>
> Hanswww.ht-lab.com

Hi Hans,
"; Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is
exceeded
; the earliest times get truncated from the file.
WLFTimeLimit =3D {100 ms} "

It seems that is what I want: to limit waveform file limit and it may
overwrite oldest one and continue writing new one.

I will try the option. I will tell you back if the option is purposely
designed for that purpose.

Thank you.

Weng






Article: 142753
Subject: Re: Does ModelSim or any simulator software have a function similar to the standard function any logic analizer has?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sun, 30 Aug 2009 16:39:54 +0100
Links: << >>  << T >>  << A >>
On Sun, 30 Aug 2009 06:57:19 -0700 (PDT), gabor wrote:

[Hans:]
>> You can also use the WLFSizeLimit variable to limit
>> the wlf file size (see manual/modelsim.ini).

Thanks Hans, I'd completely forgotten about that.

[Gabor:]
>The problem with that is that it's not obvious that the wlf will
>contain the most recent portion of the trace.

But that's precisely what Hans said: it's the OLDEST part
of the log that's deleted.  It works like a charm.  You
can limit the log file by time or by file size.  Just look
at modelsim.ini for details - see WLFTimeLimit or WLFSizeLimit.

>What you need, and what the logic analyzer has, is a ring buffer that
>has a fixed size (up to your disk space limit) and starts
>overwriting the oldest data when it hits that size.  I don't
>think ModelSim has that now.

See above: it does.  Combine that with "when" scriptable 
breakpoints and surely you have everything you need.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 142754
Subject: Re: program spartan3 under linux
From: Thorsten Kiefer <toki78@gmx.net>
Date: Sun, 30 Aug 2009 19:27:56 +0200
Links: << >>  << T >>  << A >>
Frank Buss wrote:

> Antti.Lukats@googlemail.com wrote:
> 
>> Option 1:
>> Get a PC with preinstalled WinXP/Vista and forget the attempts to use
>> FPGA tools under linux
>> This option saves lots of frustration and is worth the money spent
> 
> I use Windows, too, but maybe a VMWare, or with another virtualization
> software, you don't need at least an extra PC (I'm using this on my
> desktop PC to run Debian Linux in VMWare, which works fine). Or install
> Linux and Windows on one PC with a bootmanager like Grub (this is my
> Laptop setup), but Murphy's Law says, that you just need some program for
> Linux fast (e.g. phone call from a customer and you have to check
> something) when Windows is booted and vice versa :-)
> 

Xilinx ISE is very slow on Windows and much faster on Linux.
So once I used a Linux box to code and a win box for uploading
the mcs file. According to your advise I will try running
the Digilent ExPort tool on Win in VirtualBox.




Article: 142755
Subject: Virtex 5 HDMI
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Sun, 30 Aug 2009 13:15:31 -0500
Links: << >>  << T >>  << A >>
I would like to implement a HDMI transmitter with a Virtex 5. Does anyone
know if there is a chip that converts LVDS to TMDS?

Thanks

Jon 

Article: 142756
Subject: Re: program spartan3 under linux
From: nico@puntnl.niks (Nico Coesel)
Date: Sun, 30 Aug 2009 20:16:31 GMT
Links: << >>  << T >>  << A >>
"Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com> wrote:

>On Aug 30, 4:47=A0pm, Thorsten Kiefer <tok...@gmx.net> wrote:
>> Antti.Luk...@googlemail.com wrote:
>> > On Aug 28, 12:51 am, Thorsten Kiefer <tok...@gmx.net> wrote:
>> >> Hi,
>> >> I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the
>> >> Digilent USB/JTAG cable.
>> >> I find ISE 11.1 too slow under Windows, so I want to use it with Linux=
>.
>I know.
>
>But if you want the ALL BUNDLE, meaning development
>tools and utilities for 5 different FPGA vendors, + special
>tools for 3rd parties, then you just have to have one win
>box no matter how hard you may hate that solution.

Any experience using OpenOCD combined with a generic JTAG dongle (can
be as simple as a parallel port wiggler) to program xsv (or whatever
these pre-cooked jtag files are called) into the FPGA?

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

Article: 142757
Subject: Re: program spartan3 under linux
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Sun, 30 Aug 2009 14:23:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 11:16=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
> "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote:
> >On Aug 30, 4:47=3DA0pm, Thorsten Kiefer <tok...@gmx.net> wrote:
> >> Antti.Luk...@googlemail.com wrote:
> >> > On Aug 28, 12:51 am, Thorsten Kiefer <tok...@gmx.net> wrote:
> >> >> Hi,
> >> >> I'm using the Xilinx Webpack 11.1, the Spartan3 StarterKit, and the
> >> >> Digilent USB/JTAG cable.
> >> >> I find ISE 11.1 too slow under Windows, so I want to use it with Li=
nux=3D
> >.
> >I know.
>
> >But if you want the ALL BUNDLE, meaning development
> >tools and utilities for 5 different FPGA vendors, + special
> >tools for 3rd parties, then you just have to have one win
> >box no matter how hard you may hate that solution.
>
> Any experience using OpenOCD combined with a generic JTAG dongle (can
> be as simple as a parallel port wiggler) to program xsv (or whatever
> these pre-cooked jtag files are called) into the FPGA?
>
> --
> Failure does not prove something is impossible, failure simply
> indicates you are not using the right tools...
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg=
er hammer!"
> --------------------------------------------------------------

you dont rean the brain, i think i have written that using svf files
with jtag player is not a problem at all, i used amontec jtagkey
but any supported hw would do.hm i guess i used openocd
as player, think i did
--

Thorsten: i said win box (real PC), not VM virtual windows
under linux - different things, it is safe to run linux in win VM,
but not the otherway around as long as it goes the usb drivers
(well maybe linux usb want work in win VM either, but there
is no need for it also).

its worth a try of course as last hope, but it is not guaranteed
for success, sorry the linux way is die hard way, if you want
it it all yours..

I go the hard way too, when the task calls for it, but messing
around with linux/jtag/usb isnt for me, it doesnt pay

well it may one day develop some linux stuff that works,
but for my everyday work i use things that are known to work

Antti

Article: 142758
Subject: Re: program spartan3 under linux
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Sun, 30 Aug 2009 14:25:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 8:27=A0pm, Thorsten Kiefer <tok...@gmx.net> wrote:
> Frank Buss wrote:
> > Antti.Luk...@googlemail.com wrote:
>
> >> Option 1:
> >> Get a PC with preinstalled WinXP/Vista and forget the attempts to use
> >> FPGA tools under linux
> >> This option saves lots of frustration and is worth the money spent
>
> > I use Windows, too, but maybe a VMWare, or with another virtualization
> > software, you don't need at least an extra PC (I'm using this on my
> > desktop PC to run Debian Linux in VMWare, which works fine). Or install
> > Linux and Windows on one PC with a bootmanager like Grub (this is my
> > Laptop setup), but Murphy's Law says, that you just need some program f=
or
> > Linux fast (e.g. phone call from a customer and you have to check
> > something) when Windows is booted and vice versa :-)
>
> Xilinx ISE is very slow on Windows and much faster on Linux.
> So once I used a Linux box to code and a win box for uploading
> the mcs file. According to your advise I will try running
> the Digilent ExPort tool on Win in VirtualBox.- Hide quoted text -
>
> - Show quoted text -

I did NOT advise using win in virtual box, I meant REAL PC
think i did even say need buy PC with pre installed winXP
this mean real machine not win in VM

there is no gurantee digilent export will work in virual win box

Antti





Article: 142759
Subject: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
From: "murlary@gmail.com" <water9580@yahoo.com>
Date: Sun, 30 Aug 2009 17:55:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@googlemail.c=
om"
<antti.luk...@googlemail.com> wrote:
> On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> wrote:
>
> > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@googlema=
il.com"
>
> > <antti.luk...@googlemail.com> wrote:
> > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote:
>
> > > > who have the available  wrapper?
>
> > > wau do you think its only the wrapper you need?
> > > ask PLDA what their USB 3.0 IP cores costs
> > > then think how likely is to get a free IP
>
> > > Antti
> > > asics.ws also has usb 3.0 solutions i think
>
> > i only need this wrapper.
>
> 1) contact PLDA
> 2) contact asics.ws
> 3) write yourself
>
> Antti
> PS look at your rating:
> you have been rated 20 times, and the rating score is 1 out 5,
> means that.. [insert here....]
>
> there is no need for wrapper if you dont have the USB 3.0 IP
> but if you have the IP, you would also have the wrapper..

I have designed usb3.0 host controller sucessfully. but i need verify
it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device.

Article: 142760
Subject: Selection of external clocks for FPGA system and bus interfacing
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Sun, 30 Aug 2009 22:46:57 -0600
Links: << >>  << T >>  << A >>
Hello--

As discussed in previous posts, I'm in the process of designing a system 
which interfaces 6 serial-bus ADCs and 1 serial-bus DAC to a FPGA.  Data 
from each ADC is offloaded to asynchronous SRAM memory.  Also on the PCB 
is an embedded processor, the AP7001 from Atmel, which communicates with 
the FPGA over the SPI and SSC buses.

I've finally selected the FPGA, which is a Cyclone II EP2C8Q208I8N from 
Altera.  The core is powered at a nominal 1.2V, whereas all I/O banks 
are powered at 3.3V voltage levels.

Here is a list of the devices attached to the FPGA, along with the 
speeds of each bus:

(1) DAC8580 from Texas Instruments, DAC serial bus speed 30 MHz
(2) AD7690 from Analog Devices, ADC serial bus clock period minimum 15ns 
(~66 MHz bus speed)
(3) SPI bus to AP7001 master, 50MHz nominal speed
(4) IS61WV102416BLL 1M x 16 CMOS Asynchronous SRAM from ISSI, max 10ns 
update (100MHz) speed.  Three of these chips are interfaced to the FPGA 
to give 6MBytes of volatile memory.
(5) Serial RS-232 RX/TX port at nominal 115200 baud attached to FPGA
(6) SSC bus connection to AP7001 processor for reading data stored in 
the SRAM

To take a sample from all ADCs at the same time, the FPGA is used to 
bring high a TRIGGER pin on each of the 6 ADCs.  Each ADC samples at a 
rate of 400kHz.  All of the ADCs are read at the same time using 
separate SPI serial buses interfaced to the FPGA.

I am wondering:

(a) How many external clock inputs I should provide to the FPGA (8 
external clock inputs are supported for this particular Cyclone II 
FPGA).  Two PLLs are available.

(b) What should be the speed of each clock?

(c) What should be the speed of the system clock?

(d) Should I interface the DAC and ADCs to the same I/O bank, the SRAM 
to another I/O bank, and the SSC and RS-232 buses to another I/O bank? 
I would like to arrange the SRAM all on one side of the FPGA to allow 
for easy layout of the parallel bus connections.  Is there (or should 
there be) any preference for selecting the bank for the SRAM connections?

(e) If the voltages on all I/O banks are at the same 3.3V levels, could 
I span the ADC serial buses across two banks?

Article: 142761
Subject: Re: Selection of external clocks for FPGA system and bus interfacing
From: John Adair <g1@enterpoint.co.uk>
Date: Sun, 30 Aug 2009 22:57:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
Nicholas

Minimising the number of clocks is a good thing to minimise issues in
clock boundary crossings (lots of posts on this). If you want multiple
clocks a good half house is to have clock that that are exact
multiples of the same base and phase locked together. I would suggest
getting a single frequency version going fist just to see that all the
logic works correctly and then update to add more performance by
changing clocks.

The main restrictions on bank sharing and splitting over are that they
are the same voltage. There are some other restrictions for
differential signalling and the numbers of I/O switching together but
I doubt these apply to your design from the description.

John Adair
Enterpoint Ltd. - Home of Merrick1. The HPC Solution.

On 31 Aug, 05:46, Nicholas Kinar <n.ki...@usask.ca> wrote:
> Hello--
>
> As discussed in previous posts, I'm in the process of designing a system
> which interfaces 6 serial-bus ADCs and 1 serial-bus DAC to a FPGA. =A0Dat=
a
> from each ADC is offloaded to asynchronous SRAM memory. =A0Also on the PC=
B
> is an embedded processor, the AP7001 from Atmel, which communicates with
> the FPGA over the SPI and SSC buses.
>
> I've finally selected the FPGA, which is a Cyclone II EP2C8Q208I8N from
> Altera. =A0The core is powered at a nominal 1.2V, whereas all I/O banks
> are powered at 3.3V voltage levels.
>
> Here is a list of the devices attached to the FPGA, along with the
> speeds of each bus:
>
> (1) DAC8580 from Texas Instruments, DAC serial bus speed 30 MHz
> (2) AD7690 from Analog Devices, ADC serial bus clock period minimum 15ns
> (~66 MHz bus speed)
> (3) SPI bus to AP7001 master, 50MHz nominal speed
> (4) IS61WV102416BLL 1M x 16 CMOS Asynchronous SRAM from ISSI, max 10ns
> update (100MHz) speed. =A0Three of these chips are interfaced to the FPGA
> to give 6MBytes of volatile memory.
> (5) Serial RS-232 RX/TX port at nominal 115200 baud attached to FPGA
> (6) SSC bus connection to AP7001 processor for reading data stored in
> the SRAM
>
> To take a sample from all ADCs at the same time, the FPGA is used to
> bring high a TRIGGER pin on each of the 6 ADCs. =A0Each ADC samples at a
> rate of 400kHz. =A0All of the ADCs are read at the same time using
> separate SPI serial buses interfaced to the FPGA.
>
> I am wondering:
>
> (a) How many external clock inputs I should provide to the FPGA (8
> external clock inputs are supported for this particular Cyclone II
> FPGA). =A0Two PLLs are available.
>
> (b) What should be the speed of each clock?
>
> (c) What should be the speed of the system clock?
>
> (d) Should I interface the DAC and ADCs to the same I/O bank, the SRAM
> to another I/O bank, and the SSC and RS-232 buses to another I/O bank?
> I would like to arrange the SRAM all on one side of the FPGA to allow
> for easy layout of the parallel bus connections. =A0Is there (or should
> there be) any preference for selecting the bank for the SRAM connections?
>
> (e) If the voltages on all I/O banks are at the same 3.3V levels, could
> I span the ADC serial buses across two banks?


Article: 142762
Subject: Re: Selection of external clocks for FPGA system and bus interfacing
From: John Adair <g1@enterpoint.co.uk>
Date: Sun, 30 Aug 2009 23:06:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
Forgot this - I would suggest a system clock in the area of 20-30MHz
to start with. You can probably build a base system, with no PLLs, to
get going with.

John Adair
Enterpoit Ltd.

On 31 Aug, 06:57, John Adair <g...@enterpoint.co.uk> wrote:
> Nicholas
>
> Minimising the number of clocks is a good thing to minimise issues in
> clock boundary crossings (lots of posts on this). If you want multiple
> clocks a good half house is to have clock that that are exact
> multiples of the same base and phase locked together. I would suggest
> getting a single frequency version going fist just to see that all the
> logic works correctly and then update to add more performance by
> changing clocks.
>
> The main restrictions on bank sharing and splitting over are that they
> are the same voltage. There are some other restrictions for
> differential signalling and the numbers of I/O switching together but
> I doubt these apply to your design from the description.
>
> John Adair
> Enterpoint Ltd. - Home of Merrick1. The HPC Solution.
>
> On 31 Aug, 05:46, Nicholas Kinar <n.ki...@usask.ca> wrote:
>
> > Hello--
>
> > As discussed in previous posts, I'm in the process of designing a syste=
m
> > which interfaces 6 serial-bus ADCs and 1 serial-bus DAC to a FPGA. =A0D=
ata
> > from each ADC is offloaded to asynchronous SRAM memory. =A0Also on the =
PCB
> > is an embedded processor, the AP7001 from Atmel, which communicates wit=
h
> > the FPGA over the SPI and SSC buses.
>
> > I've finally selected the FPGA, which is a Cyclone II EP2C8Q208I8N from
> > Altera. =A0The core is powered at a nominal 1.2V, whereas all I/O banks
> > are powered at 3.3V voltage levels.
>
> > Here is a list of the devices attached to the FPGA, along with the
> > speeds of each bus:
>
> > (1) DAC8580 from Texas Instruments, DAC serial bus speed 30 MHz
> > (2) AD7690 from Analog Devices, ADC serial bus clock period minimum 15n=
s
> > (~66 MHz bus speed)
> > (3) SPI bus to AP7001 master, 50MHz nominal speed
> > (4) IS61WV102416BLL 1M x 16 CMOS Asynchronous SRAM from ISSI, max 10ns
> > update (100MHz) speed. =A0Three of these chips are interfaced to the FP=
GA
> > to give 6MBytes of volatile memory.
> > (5) Serial RS-232 RX/TX port at nominal 115200 baud attached to FPGA
> > (6) SSC bus connection to AP7001 processor for reading data stored in
> > the SRAM
>
> > To take a sample from all ADCs at the same time, the FPGA is used to
> > bring high a TRIGGER pin on each of the 6 ADCs. =A0Each ADC samples at =
a
> > rate of 400kHz. =A0All of the ADCs are read at the same time using
> > separate SPI serial buses interfaced to the FPGA.
>
> > I am wondering:
>
> > (a) How many external clock inputs I should provide to the FPGA (8
> > external clock inputs are supported for this particular Cyclone II
> > FPGA). =A0Two PLLs are available.
>
> > (b) What should be the speed of each clock?
>
> > (c) What should be the speed of the system clock?
>
> > (d) Should I interface the DAC and ADCs to the same I/O bank, the SRAM
> > to another I/O bank, and the SSC and RS-232 buses to another I/O bank?
> > I would like to arrange the SRAM all on one side of the FPGA to allow
> > for easy layout of the parallel bus connections. =A0Is there (or should
> > there be) any preference for selecting the bank for the SRAM connection=
s?
>
> > (e) If the voltages on all I/O banks are at the same 3.3V levels, could
> > I span the ADC serial buses across two banks?


Article: 142763
Subject: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Mon, 31 Aug 2009 00:22:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 31, 3:55 am, "murl...@gmail.com" <water9...@yahoo.com> wrote:
> On 8=D4=C230=C8=D5, =CF=C2=CE=E72=CA=B102=B7=D6, "Antti.Luk...@googlemail=
.com"
>
>
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Aug 30, 8:32 am, "murl...@gmail.com" <water9...@yahoo.com> wrote:
>
> > > On 8=D4=C228=C8=D5, =CF=C2=CE=E76=CA=B127=B7=D6, "Antti.Luk...@google=
mail.com"
>
> > > <antti.luk...@googlemail.com> wrote:
> > > > On Aug 28, 11:01 am, water <water9...@yahoo.com> wrote:
>
> > > > > who have the available  wrapper?
>
> > > > wau do you think its only the wrapper you need?
> > > > ask PLDA what their USB 3.0 IP cores costs
> > > > then think how likely is to get a free IP
>
> > > > Antti
> > > > asics.ws also has usb 3.0 solutions i think
>
> > > i only need this wrapper.
>
> > 1) contact PLDA
> > 2) contact asics.ws
> > 3) write yourself
>
> > Antti
> > PS look at your rating:
> > you have been rated 20 times, and the rating score is 1 out 5,
> > means that.. [insert here....]
>
> > there is no need for wrapper if you dont have the USB 3.0 IP
> > but if you have the IP, you would also have the wrapper..
>
> I have designed usb3.0 host controller sucessfully. but i need verify
> it at V5/V6 device.I need the usb3.0 PHY wrapper for V5/V6 device.- Hide =
quoted text -
>
> - Show quoted text -

try using 1GbE setting for MGT wrapper, if you test with your own test
IP it should work already

Antti


Article: 142764
Subject: Re: Virtex 5 HDMI
From: "Antti.Lukats@googlemail.com" <antti.lukats@googlemail.com>
Date: Mon, 31 Aug 2009 00:46:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 9:15=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> I would like to implement a HDMI transmitter with a Virtex 5. Does anyone
> know if there is a chip that converts LVDS to TMDS?
>
> Thanks
>
> Jon

TMDS uses DC coupled CML

Antti

Article: 142765
Subject: Re: Virtex 5 HDMI
From: Sandro <sdroamt@netscape.net>
Date: Mon, 31 Aug 2009 03:52:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 30, 8:15=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> I would like to implement a HDMI transmitter with a Virtex 5. Does anyone
> know if there is a chip that converts LVDS to TMDS?


let see 6.5 of:
   http://pdfserv.maxim-ic.com/en/an/AN291.pdf
Sandro

Article: 142766
Subject: Re: Virtex 5 HDMI
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Mon, 31 Aug 2009 06:56:02 -0500
Links: << >>  << T >>  << A >>
Yes I understand what it is but I want some method to use HDMI with a
Virtex 5.

Jon

Article: 142767
Subject: Re: Virtex 5 HDMI
From: "Phil Jessop" <phil@noname.org>
Date: Mon, 31 Aug 2009 13:26:47 +0100
Links: << >>  << T >>  << A >>

"maxascent" <maxascent@yahoo.co.uk> wrote in message 
news:HpqdnQS28-7PJwbXnZ2dnUVZ_umdnZ2d@giganews.com...
> Yes I understand what it is but I want some method to use HDMI with a
> Virtex 5.
>


You could use VHDL or Verilog, or if you know what you are doing schematic 
capture.



Article: 142768
Subject: Re: can't write to a bram module (verilog)
From: "nskri" <ansgarus@gmail.com>
Date: Mon, 31 Aug 2009 08:29:45 -0500
Links: << >>  << T >>  << A >>
Hi again, 

You were right, I thought the second part represented the address.

Now it works nicely.

Thanks a lot

Article: 142769
Subject: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
From: Dennis Yurichev <dennis.yurichev@gmail.com>
Date: Mon, 31 Aug 2009 07:16:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi.

Does anybody had any real success on running OpenSPARC core on Altera
Stratix II?

Article: 142770
Subject: Re: Selection of external clocks for FPGA system and bus interfacing
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Mon, 31 Aug 2009 08:54:12 -0600
Links: << >>  << T >>  << A >>

> 
> The main restrictions on bank sharing and splitting over are that they
> are the same voltage. There are some other restrictions for
> differential signalling and the numbers of I/O switching together but
> I doubt these apply to your design from the description.
> 

Thanks, John. It's good to know that I can share banks in this fashion. 
Thank you for your help.

Article: 142771
Subject: Re: Selection of external clocks for FPGA system and bus interfacing
From: Nicholas Kinar <n.kinar@usask.ca>
Date: Mon, 31 Aug 2009 08:58:22 -0600
Links: << >>  << T >>  << A >>
> Forgot this - I would suggest a system clock in the area of 20-30MHz
> to start with. You can probably build a base system, with no PLLs, to
> get going with.
> 

Sounds good, John.  What I will do is select a 30MHz oscillator to start 
off with, and I'll also leave space on my PCB to add other clocks to 
clock input pins.  This will provide for situations when I think that 
more clocks are required.

Thanks, John.

Article: 142772
Subject: Re: Where is Altera On-Demand Webinars show on radar signal
From: andi <andreapalomo@gmail.com>
Date: Mon, 31 Aug 2009 09:34:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 27, 12:37=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I recently received aOn-Demand Webinars email to watch Altera radar
> signal processing webcast. I did watched the show two times and found
> the webcast is valuable and impressive with input data rate 2.8GBS and
> output with 8 channels with each 350MSS. It asked me to do some
> further reading to understand its full processing.
>
> Today I searchedOn-Demand Webinars with keyword "Altera" and found
> there is no Altera radar signal processing webcast at all for
> 2009-2007.
>
> Anyone knows there it is, please post its website address.
>
> Thank you.
>
> Weng

Here is the link to the webcast you're looking for:
Rapid Military Sensor DSP Design with FPGAs:
http://www.altera.com/education/webcasts/all/wc-2009-sensor-design-dsp-buil=
der.html

Article: 142773
Subject: Re: program spartan3 under linux
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Mon, 31 Aug 2009 20:54:16 +0200
Links: << >>  << T >>  << A >>
Thorsten Kiefer <toki78@gmx.net> writes:

> What FPGA vendor and development board would you suggest for
> development on Linux ?

Altera has pretty good Linux support. I've been using Quartus under
Linux¹ for a couple years including JTAG programming, signaltap
debugging and NIOS II IDE debugging without any problems. I've also
used head-less Linux boxes as JTAG servers with the Altera programming
software.

As for both Altera and Xilinx I've also used my own custom programmer
which is Ethernet attached. I simply send my programming file to the
programmer using tftp which is available for most OSes. Unfortunately,
I don't have any documentation on the signaltap and chipscope
protocols in order to support those :-(


Petter

¹) Mostly Gentoo Linux even though it's not a supported distribution.
I've experienced some problems with the c-shell based Altera scripts
on unsupported Linux platforms.

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 142774
Subject: Re: Where is Altera On-Demand Webinars show on radar signal
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 31 Aug 2009 16:27:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 31, 9:34=A0am, andi <andreapal...@gmail.com> wrote:
> On Aug 27, 12:37=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > Hi,
> > I recently received aOn-Demand Webinars email to watch Altera radar
> > signal processing webcast. I did watched the show two times and found
> > the webcast is valuable and impressive with input data rate 2.8GBS and
> > output with 8 channels with each 350MSS. It asked me to do some
> > further reading to understand its full processing.
>
> > Today I searchedOn-Demand Webinars with keyword "Altera" and found
> > there is no Altera radar signal processing webcast at all for
> > 2009-2007.
>
> > Anyone knows there it is, please post its website address.
>
> > Thank you.
>
> > Weng
>
> Here is the link to the webcast you're looking for:
> Rapid Military Sensor DSP Design with FPGAs:http://www.altera.com/educati=
on/webcasts/all/wc-2009-sensor-design-ds...- Hide quoted text -
>
> - Show quoted text -

Hi Andi,
Thank you very much. How did you find it?

Weng



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