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Mike Treseler wrote:
> Note that tested vhdl synthesis examples that
> that make use of vhdl's unfair adavantages
advantages
> as well as standard libraries, are rare.
I couldn't resist noting my own unintentional cleverness here.
Many of vhdl's advantages are stolen from the language ADA.
Therefore, some are indeed "ada-advantages" ;)
-- Mike Treseler
Article: 143001To whom it may concern, Regarding the use of 'entitlenow' to download from your web site: May I respectfully request that you gather together everyone at Xilinx that thought that this was a good idea, drag them out to the parking lot, and beat them with a cricket bat until they promise to never do anything this foolish ever again. I am running a modern OS, with the latest browser and a very current copy of Java. I do not recall ever having so many problems downloading updates. Crashes, hangs, bad file names, errant pop-ups, you name it. This alone is making me want to encourage my clients to change FPGA vendors. If you can't get "file transfer" right, how can I trust you to get "synthesize" right? Get those bats out, and do it sometime when the google-earth satellite is overhead; I need to know that it got done. Sincerely, ALArticle: 143002
I forgot one detail: There is *one* program in all of the tools that I use that can not tolerate spaces in file/directory names: ISE. Find the fools that put spaces in the file names for the updates, and drag them out to the parking lot also. Regards, AL.Article: 143003
Hi, I am using distributed ram generated from coregen in a 9.2i ISE. I find distribute ram does not hold the init content in the .coe and its corresponding .mif file, which is in the same directory path with the other vhdl files. Do you know how to introduce the .mif file to Modelsim? Thanks.Article: 143004
Hi All, I need to provide 8 clock outs shifted by 45 degree, clk_0 -> 0 degree phase shift clk_1 -> 45 degree phase shift clk_1 -> 90 degree phase shift clk_1 -> 135 degree phase shift clk_1 -> 180 degree phase shift clk_1 -> 225 degree phase shift clk_1 -> 270 degree phase shift clk_1 -> 315 degree phase shift clk_1 -> 360 degree phase shift Is it at all possible? Thanks in advance for your feed back. QamrulArticle: 143005
Hi All, I have to get all this done in a single clk cycle in verilog. Requirement for Synthesis: Y = (INT(A/(B*C))) * (B*C); Where, A is a fixed 32 bit value; B is 2**X, X is a 3 bit value, hence B varies from 2 pow 0 to 2 pow 7; C is len + 1, len is a 4 bit value, and valid len is : 2,4,8 and 16; Can anyone of you let me know how all this can be achieved in a single clk cycle in the code. Regards RaviArticle: 143006
ravisguptaji <rsgupta.gupta@gmail.com> wrote: < I have to get all this done in a single clk cycle in verilog. < Requirement for Synthesis: < Y = (INT(A/(B*C))) * (B*C); < Where, < A is a fixed 32 bit value; < B is 2**X, X is a 3 bit value, hence B varies from 2 pow 0 to 2 pow 7; < C is len + 1, len is a 4 bit value, and valid len is : 2,4,8 and 16; < Can anyone of you let me know how all this can be achieved < in a single clk cycle in the code. Doing almost anything in a single clock cycle isn't a problem. The usual problem is that one also wants a high clock rate, which may be too fast for what one wants done. You can write a full combinatorial divider, 32 bits by 32 bits (for example). It might be slow, though. Maybe only 3MHz, maybe a little more. -- glen -- glenArticle: 143007
On Mon, 14 Sep 2009 22:51:21 +0000 (UTC), glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >ravisguptaji <rsgupta.gupta@gmail.com> wrote: > >< I have to get all this done in a single clk cycle in verilog. >< Requirement for Synthesis: >< Y = (INT(A/(B*C))) * (B*C); > >< Where, >< A is a fixed 32 bit value; >< B is 2**X, X is a 3 bit value, hence B varies from 2 pow 0 to 2 pow 7; >< C is len + 1, len is a 4 bit value, and valid len is : 2,4,8 and 16; > >< Can anyone of you let me know how all this can be achieved >< in a single clk cycle in the code. > >Doing almost anything in a single clock cycle isn't a problem. >The usual problem is that one also wants a high clock rate, >which may be too fast for what one wants done. > >You can write a full combinatorial divider, 32 bits by 32 bits >(for example). It might be slow, though. Maybe only 3MHz, maybe >a little more. A divider is really not needed as the denominator is defined by only 7 bits total so calculating 1/(B*C) should be much easier than dividing. Then depending on how "fixed" A is above, one can come up with really fast calculations too. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 143008
Muzaffer Kal <kal@dspia.com> wrote: < On Mon, 14 Sep 2009 22:51:21 +0000 (UTC), glen herrmannsfeldt < <gah@ugcs.caltech.edu> wrote: <>ravisguptaji <rsgupta.gupta@gmail.com> wrote: <>< I have to get all this done in a single clk cycle in verilog. <>< Requirement for Synthesis: <>< Y = (INT(A/(B*C))) * (B*C); <>< Where, <>< A is a fixed 32 bit value; <>< B is 2**X, X is a 3 bit value, hence B varies from 2 pow 0 to 2 pow 7; <>< C is len + 1, len is a 4 bit value, and valid len is : 2,4,8 and 16; (snip, then I wrote) <>You can write a full combinatorial divider, 32 bits by 32 bits <>(for example). It might be slow, though. Maybe only 3MHz, maybe <>a little more. < A divider is really not needed as the denominator is defined by only 7 < bits total so calculating 1/(B*C) should be much easier than dividing. < Then depending on how "fixed" A is above, one can come up with really < fast calculations too. The OP gave no requirements for either speed or size. You are saying that a look up table would be easier than a full combinatorial divider, and I would agree. On the other hand, isn't the look up table a form of divider? Will any of the synthesis tools generate a full combinatorial 32 bit by 32 bit divider? (This needs less than 32 bits for divisor, though.) -- glenArticle: 143009
On Mon, 14 Sep 2009 12:05:22 -0700, Mike Treseler <mtreseler@gmail.com> wrote: >Mike Treseler wrote: > >> Note that tested vhdl synthesis examples that >> that make use of vhdl's unfair adavantages > advantages > >> as well as standard libraries, are rare. > >I couldn't resist noting my own unintentional cleverness here. >Many of vhdl's advantages are stolen from the language ADA. >Therefore, some are indeed "ada-advantages" ;) > I love those unintentional improvements (mutations? to the original word. My favourite (unnoticed by its authors) was on a slide, presented by Motorola, describing the features of a new chip - or rather, since they hadn't built it yet - describing what they wanted us to believe the chip would do. And the slide was titled... Specifiction - BrianArticle: 143010
Hi,
Till now i have come up will the following code..
/////*****Code Snippet*****/////
******Combinational Logic*******
always @(*) begin
case ({B,C}) // B*C
7'b000_0001 : size_len = 12'b0000_0000_0010; // 2
7'b000_0011 : size_len = 12'b0000_0000_0100; // 4
7'b000_0111 : size_len = 12'b0000_0000_1000; // 8
7'b000_1111 : size_len = 12'b0000_0001_0000; // 16
7'b001_0001 : size_len = 12'b0000_0000_0100; // 4
7'b001_0011 : size_len = 12'b0000_0000_1000; // 8
7'b001_0111 : size_len = 12'b0000_0001_0000; // 16
7'b001_1111 : size_len = 12'b0000_0010_0000; // 32
7'b010_0001 : size_len = 12'b0000_0000_1000; // 8
7'b010_0011 : size_len = 12'b0000_0001_0000; // 16
7'b010_0111 : size_len = 12'b0000_0010_0000; // 32
7'b010_1111 : size_len = 12'b0000_0100_0000; // 64
7'b011_0001 : size_len = 12'b0000_0001_0000; // 16
7'b011_0011 : size_len = 12'b0000_0010_0000; // 32
7'b011_0111 : size_len = 12'b0000_0100_0000; // 64
7'b011_1111 : size_len = 12'b0000_1000_0000; // 128
7'b100_0001 : size_len = 12'b0000_0010_0000; // 32
7'b100_0011 : size_len = 12'b0000_0100_0000; // 64
7'b100_0111 : size_len = 12'b0000_1000_0000; // 128
7'b100_1111 : size_len = 12'b0001_0000_0000; // 256
7'b101_0001 : size_len = 12'b0000_0100_0000; // 64
7'b101_0011 : size_len = 12'b0000_1000_0000; // 128
7'b101_0111 : size_len = 12'b0001_0000_0000; // 256
7'b101_1111 : size_len = 12'b0010_0000_0000; // 512
7'b110_0001 : size_len = 12'b0000_1000_0000; // 128
7'b110_0011 : size_len = 12'b0001_0000_0000; // 256
7'b110_0111 : size_len = 12'b0010_0000_0000; // 512
7'b110_1111 : size_len = 12'b0100_0000_0000; //1024
7'b111_0001 : size_len = 12'b0001_0000_0000; // 256
7'b111_0011 : size_len = 12'b0010_0000_0000; // 512
7'b111_0111 : size_len = 12'b0100_0000_0000; //1024
7'b111_1111 : size_len = 12'b1000_0000_0000; // 2048
default : $display("Violation of Protocol");
endcase
end
*******Sequential Logic********
Parameter AWIDTH = 32
case (size_len)
12'b0000_0000_0010 : Y <= {A[AWIDTH:1],1'b0};
12'b0000_0000_0100 : Y <= {A[AWIDTH:2],2'b0};
12'b0000_0000_1000 : Y <= {A[AWIDTH:3],3'b0};
12'b0000_0001_0000 : Y <= {A[AWIDTH:4],4'b0};
12'b0000_0010_0000 : Y <= {A[AWIDTH:5],5'b0};
12'b0000_0100_0000 : Y <= {A[AWIDTH:6],6'b0};
12'b0000_1000_0000 : Y <= {A[AWIDTH:7],7'b0};
12'b0001_0000_0000 : Y <= {A[AWIDTH:8],8'b0};
12'b0010_0000_0000 : Y <= {A[AWIDTH:9],9'b0};
12'b0100_0000_0000 : Y <= {A[AWIDTH:10],10'b0};
12'b1000_0000_0000 : Y <= {A[AWIDTH:11],11'b0};
default : $display("Violation of Protocol");
endcase
********** End Code Snippet ********
Is everthing Ok with the above code snippet....
Synthesis constraint is more on Speed...
>Muzaffer Kal <kal@dspia.com> wrote:
>< On Mon, 14 Sep 2009 22:51:21 +0000 (UTC), glen herrmannsfeldt
>< <gah@ugcs.caltech.edu> wrote:
>
><>ravisguptaji <rsgupta.gupta@gmail.com> wrote:
>
><>< I have to get all this done in a single clk cycle in verilog.
><>< Requirement for Synthesis:
><>< Y = (INT(A/(B*C))) * (B*C);
>
><>< Where,
><>< A is a fixed 32 bit value;
><>< B is 2**X, X is a 3 bit value, hence B varies from 2 pow 0 to 2 pow
7;
><>< C is len + 1, len is a 4 bit value, and valid len is : 2,4,8 and 16;
>
>(snip, then I wrote)
>
><>You can write a full combinatorial divider, 32 bits by 32 bits
><>(for example). It might be slow, though. Maybe only 3MHz, maybe
><>a little more.
>
>< A divider is really not needed as the denominator is defined by only 7
>< bits total so calculating 1/(B*C) should be much easier than dividing.
>< Then depending on how "fixed" A is above, one can come up with really
>< fast calculations too.
>
>The OP gave no requirements for either speed or size.
>
>You are saying that a look up table would be easier than a
>full combinatorial divider, and I would agree.
>
>On the other hand, isn't the look up table a form of divider?
>
>Will any of the synthesis tools generate a full combinatorial
>32 bit by 32 bit divider? (This needs less than 32 bits for
>divisor, though.)
>
>-- glen
>
---------------------------------------
This message was sent using the comp.arch.fpga web interface on
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Article: 143011On Mon, 14 Sep 2009 23:47:36 +0000 (UTC), glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >Muzaffer Kal <kal@dspia.com> wrote: >< On Mon, 14 Sep 2009 22:51:21 +0000 (UTC), glen herrmannsfeldt >< <gah@ugcs.caltech.edu> wrote: > ><>ravisguptaji <rsgupta.gupta@gmail.com> wrote: > ><>< I have to get all this done in a single clk cycle in verilog. ><>< Requirement for Synthesis: ><>< Y = (INT(A/(B*C))) * (B*C); > ><>< Where, ><>< A is a fixed 32 bit value; ><>< B is 2**X, X is a 3 bit value, hence B varies from 2 pow 0 to 2 pow 7; ><>< C is len + 1, len is a 4 bit value, and valid len is : 2,4,8 and 16; > >(snip, then I wrote) > ><>You can write a full combinatorial divider, 32 bits by 32 bits ><>(for example). It might be slow, though. Maybe only 3MHz, maybe ><>a little more. > >< A divider is really not needed as the denominator is defined by only 7 >< bits total so calculating 1/(B*C) should be much easier than dividing. >< Then depending on how "fixed" A is above, one can come up with really >< fast calculations too. > >The OP gave no requirements for either speed or size. > The fact that the client doesn't mention speed/size requirements is a strong suggestion that they're actually quite challenging ;-) >You are saying that a look up table would be easier than a >full combinatorial divider, and I would agree. > >On the other hand, isn't the look up table a form of divider? > It would be difficult for a divider implementation to take advantage of restricted input domain values (especially C). >Will any of the synthesis tools generate a full combinatorial >32 bit by 32 bit divider? (This needs less than 32 bits for >divisor, though.) Not that I know of. I think most synthesizers available today can only do fixed numerator division but I could be wrong because I have never tried. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 143012
On Sep 15, 1:27=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote: > Hi All, > > I need to provide 8 clock outs shifted by 45 degree, > > clk_0 -> 0 degree phase shift > clk_1 -> 45 degree phase shift > clk_1 -> 90 degree phase shift > clk_1 -> 135 degree phase shift > clk_1 -> 180 degree phase shift > clk_1 -> 225 degree phase shift > clk_1 -> 270 degree phase shift > clk_1 -> 315 degree phase shift > clk_1 -> 360 degree phase shift > > Is it at all possible? > > Thanks in advance for your feed back. > > Qamrul yesArticle: 143013
On Mon, 14 Sep 2009 17:27:55 -0500, "qamrul" <qamrul.hasan@spansion.com> wrote: >Hi All, > >I need to provide 8 clock outs shifted by 45 degree, > >clk_0 -> 0 degree phase shift >clk_1 -> 45 degree phase shift >clk_1 -> 90 degree phase shift >clk_1 -> 135 degree phase shift >clk_1 -> 180 degree phase shift >clk_1 -> 225 degree phase shift >clk_1 -> 270 degree phase shift >clk_1 -> 315 degree phase shift >clk_1 -> 360 degree phase shift > >Is it at all possible? (almost) Anything is possible but not everything can be engineered. Depending on what you're going to do with it (and assuming you're using an FPGA) a PLL/DCM with 4 1/8 cycle delayed outputs and their inverses might work. If you are on an ASIC, you might get a PLL which gives you access to output of its delay line which would be what you need if you chose the right PLL. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 143014
LittleAlex wrote: > I am running a modern OS, with the latest browser and a very current > copy of Java. I do not recall ever having so many problems > downloading updates. Crashes, hangs, bad file names, errant pop-ups, > you name it. I had never a problem with it. Just click on "Cancel", when the Java applet asks you for permission to execute and a normal download starts :-) Then unpack the tar-file with something like WinRar (I don't understand why Xilinx pack it with tar instead of something more native for Windows, like zip) and your are done. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 143015
Qamrul If you don't need super fast clock outputs, that is less than say 12-25 MHz, you can use an internal clock at X8, X16, and a clock enable structure to generate such outputs. If you take care such the outputs are "buffered" through an I/O register, running at the X8/16, then you won't get any significant skew on the phases due to routing. The clock enable can be a preloaded shift register, with wrap, that is loaded with X"0001" (X16) loaded at reset or other control condition. One thing that is ice about this way is that clocks can be "stopped" easily and restarted without any retraining or lock sequences. For higher frequencies using PLL or DLL techniques to achieve the required outputs is probably better. John Adair Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: > Hi All, > > I need to provide 8 clock outs shifted by 45 degree, > > clk_0 -> 0 degree phase shift > clk_1 -> 45 degree phase shift > clk_1 -> 90 degree phase shift > clk_1 -> 135 degree phase shift > clk_1 -> 180 degree phase shift > clk_1 -> 225 degree phase shift > clk_1 -> 270 degree phase shift > clk_1 -> 315 degree phase shift > clk_1 -> 360 degree phase shift > > Is it at all possible? > > Thanks in advance for your feed back. > > QamrulArticle: 143016
On Sep 15, 12:06=A0am, LittleAlex <alex.lo...@email.com> wrote: > To whom it may concern, > > Regarding the use of 'entitlenow' to download from your web site: =A0May > I respectfully request that you gather together everyone at Xilinx > that thought that this was a good idea, drag them out to the parking > lot, and beat them with a cricket bat until they promise to never do > anything this foolish ever again. > > I am running a modern OS, with the latest browser and a very current > copy of Java. =A0I do not recall ever having so many problems > downloading updates. =A0Crashes, hangs, bad file names, errant pop-ups, > you name it. > > This alone is making me want to encourage my clients to change FPGA > vendors. =A0If you can't get "file transfer" right, how can I trust you > to get "synthesize" right? > > Get those bats out, and do it sometime when the google-earth satellite > is overhead; I need to know that it got done. > > Sincerely, > AL you forgot to name the OS there are no problems with XP there are no problems with Vista I assume there are no problems with W7 what is your OS? Antti PS if you say win... isnt a OS but GUI, i almost agree but it is good enough os to launch multiply FAR's so i can use F4 key for text editing :)Article: 143017
On Sep 13, 3:59=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > > Could you give a more specific pointer? =A0The best I could > find on the new-look OpenCores was Jamil Khatib's models, > written quite a long time ago and lacking some of the > features that you need to work with RAMs in modern FPGAs. > I probably wasn't looking in the right place, though. > -- > Jonathan Bromley, Consultant Hmm, it has magically disappeared ! I can't find it anymore either. One the few reasons OpenCores is going downhill .... Regards, rudiArticle: 143018
On Sep 13, 6:08=A0pm, "Antti.Luk...@googlemail.com" <antti.luk...@googlemail.com> wrote: > > the place is right > > just that the models are of no good in many cases > > Antti I disagree with you Antti. I have used numerous times and it works just fine. For an open project (e.g. OpenCores) to succeed, it would be great if you would contribute to the project and fix whatever you think is broken. Actually, since it is gone all together now, why not create a universal memory model ? I know you are very knowledgeable with almost every vendors tools ... Cheers, rudiArticle: 143019
"fl" <rxjwg98@gmail.com> wrote in message news:bfd4d314-f3f0-4c74-b3cd-644a622578b2@v2g2000vbb.googlegroups.com... > Hi, > I am using distributed ram generated from coregen in a 9.2i ISE. I > find distribute ram does not hold the init content in the .coe and its > corresponding .mif file, which is in the same directory path with the > other vhdl files. Do you know how to introduce the .mif file to > Modelsim? Thanks. Not sure I fully understand your question but I normally either fix the path in the memory model or copy the mif file to my work directory. Do a search for c_init_file_name and see where it is pointing to. Hans www.ht-lab.comArticle: 143020
On Sep 15, 10:26=A0am, luudee <rudolf.usselm...@gmail.com> wrote: > On Sep 13, 6:08=A0pm, "Antti.Luk...@googlemail.com" > > <antti.luk...@googlemail.com> wrote: > > > the place is right > > > just that the models are of no good in many cases > > > Antti > > I disagree with you Antti. I have used numerous times and > it works just fine. > > For an open project (e.g. OpenCores) to succeed, it would > be great if you would contribute to the project and fix > whatever you think is broken. Actually, since it is gone > all together now, why not create a universal memory model ? > I know you are very knowledgeable with almost every vendors > tools ... > > Cheers, > rudi :) YES OF COURSE they have been used in many projects with success. it doesnt mean they can always be used for all vendors in all usage scenarious. yes, i work 5 vendors at the moment, but well it really to my knowledge is not possible to create models that use all different features of the block ram primitives for all 5 vendors of course i would be nice to have generic models that do it all for all vendors and all synthesis tools, but as of today it isnt possible AnttiArticle: 143021
I agree totally with the op. I have had so many problems downloading ISE 11.2 that I have just given up. Every time I try and resume after stopping I just get error and have to strt all over again. Why cant Xilinx just give us the option to download the file using our own download manger. After all if I have the capability to design with their FPGA then surely I can work out how to download a zip file. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143022
On Sep 15, 12:05=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I agree totally with the op. I have had so many problems downloading ISE > 11.2 that I have just given up. Every time I try and resume after stoppin= g > I just get error and have to strt all over again. Why cant Xilinx just gi= ve > us the option to download the file using our own download manger. After a= ll > if I have the capability to design with their FPGA then surely I can work > out how to download a zip file. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com what OS are u using? last time i donwnloaded ISE it was 0 problems, 1MBYTE/sec download. AnttiArticle: 143023
Hi guys, Well, finally success :) > It does seem that there is no explanation for it not working > at all on the original board. (Unless the output shorts go +5V.) > Or you have hooked it to a pin which is not an input. Or the enable is > not connected. Or the ground is not connected. Check the basics first. I did go back to basics, and re-checked board and connections, and all seemed fine. Then I just connected the crystal oscillator in the socket, and measured it with the Agilent (60 MHz) scope, x1 probe (since x10 tends to distort the values a bit too much on the Agilent). and lo and behold - the oscillation is there :) So what I think was wrong initially, was the fact that I was measuring the output with the Hameg (20 MHz) scope, with x1 probe. Basically, that results with output like this screenshot from the video: http://img225.imageshack.us/img225/5708/xotestx15vtext.png except the first time around, I did not have the second probe connected to measure the supply voltage in dual mode. Since the oscillations have such small peak-to-peak voltages, being unaware of the scope filtering effects - I basically misinterpreted them as being a pure DC voltage (and the supply voltage at that). So, it was probably working all along - except I had to learn to interpret that, not so thick, DC line (band actually) as oscillations.. :) Well, thanks to you, list, this has become a true crash course/tutorial for the topic of crystal oscillators for me :) Let me summarize what I have understood until now: If you suspect your high-frequency crystal oscillator (XO) device (say with a stated frequency of fs=50 MHz) to be malfunctioning, there is a way to check if it is "alive" on an off-the-shelf oscilloscope which is generally not adequate for high-res capture of the oscillator signal (by adequate, it is meant oscilloscopes that have bandwidth of more that 5*fs; so in this example, an adequate oscilloscope would have bandwidth of 250 MHz at least). The method would consist of hooking the XO device directly to a power supply, that allows manual change/sweep of supply voltage - and observing the output on the oscilloscope. As the supply voltage is slowly increased from zero volts to the stated Vcc supply of the device (slowly meaning, say, about 1V/second ), one should be able to observe the device abruptly change modes of functioning (that is, the device will "flip"). First, from 0 to some low power supply voltage, no oscillations will be observed. At some low voltage (say U1 ~= 2V) the device will start oscillating - however with a lower frequency (fb) that the stated fs. The explanation for this is that crystals have difficulties oscillating above 20 MHz in their fundamental mode, and hence, in order to achieve frequencies like fs=50 MHz, the crystal needs to oscillate in a third overtone mode. Thus the base frequency fb of this oscillation will most likely be about a third of the stated frequency fs (i.e. for fs=50MHz, fb ~= 17 MHz). Increasing the power supply voltage above U1, will result with the XO device "flipping" its mode of operation once again at some voltage threshold U2 > U1 - this time suddenly starting to oscillate with the stated frequency fs. The device should now be in its third overtone mode. However, how this flipping will be displayed on the oscilloscope depends on both the oscilloscope bandwidth and the settings of the oscilloscope probes. Say, * for a 20 MHz oscilloscope, which can pass fb=17 MHz (but not the stated fs=50MHz), the peak-to-peak amplitude for the fundamental mode (fb) oscillation, will be significantly larger, than the Vpp when the device starts its third overtone oscillation (fs) - and thus, changing the oscillation mode of the device will be observable on the scope, as a drastic change in peak-to-peak signal output. (*1) * For a 60 MHz oscilloscope, which can pass both fb=17 MHz, and fs=50 MHz, the change in the peak-to-peak amplitude of the output oscillation will not be as drastic - however, the change in frequency will be itself visible on the scope. ** So according to this, a 2 MHz oscilloscope will most likely display no oscillations :) Note that the probe settings have an effect on what the scope will display - there will be a difference in the displayed signal between a x1 and a x10 setting of a probe on the same oscilloscope. In any case, a XO device, observed behaving as described above, can most certainly be described as 'alive' and 'well' :D Thanks again, Cheers !! (*1) For a while, I thought that the drastic change of peak-to-peak output was also followed by a jump in the DC level. Now that I have re-watched that video multiple times, I am pretty sure there is no drastic jump in DC level - I guess that the peak-to-peak change was so unexpected for me, I also got fooled into perceiving the optical illusion of the DC level jumping as well :) --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143024
>what OS are u using? > >last time i donwnloaded ISE it was 0 problems, 1MBYTE/sec download. >Antti The problem seems to be, at least for me, is if you have a slow internet connection and you try and resume the download. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
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