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ElVale wrote: > If such organization ever takes place I would recommend strict > implementation of guidelines for coding (like STARC VHDL desing rules, > Aldec ALINT) and documentation (doxigen), so we could all understand > each other easily. Well, it's just an idea I had. It would have to be setup in a very specific manner so that it would function optimally. The goal would be a sort of "global" research center where not only similar scientists could work on projects but communicate with other scientists. So, for example, if one group of scientists are working on some project that requires solving some advanced mathematical problem they could request a group of mathematicians to help them work on it. A group of mathematicians could create a project for solving some unsolved math problem. Anyone in the world, that is a member, could join the project if they allow him. But it wouldn't simply be a "myspace" for scientists but a complete method for scientific research. One could have an offshoot for more practical things such as working on things such as software or whatever. It would be a one-stop-shop for like minded and intelligent people to work together.Article: 143676
On Oct 20, 11:16=A0pm, "hvo" <hai...@synrad.com> wrote: > Hi, > > I am trying to connect an IO signal from my microblaze to the external > top-level vhdl code without using xilinx GPIO IP. =A0My question is, coul= dn't > I make a port definition in the MHS file and connect to it? for example, > > PORT Test_IO =3D Test_IO, DIR =3D I =A0 =A0 // an external port not defin= ed by gpio > ip > > and then on my top-level VHDL I would connect to it in the port map by > > Test_IO =A0=3D> somesignal, > > My second question is how can I read the signal value in microblaze. =A0W= ith > xilinx's GPIO, I could read base address to get the value. =A0But now the= re's > no base address associated with Test_IO. > > Best Regards > > HV =A0 =A0 =A0 =A0 > and your port ist not connected to any microblaze busses, has no address space and can not be accessed by the software at all AnttiArticle: 143677
On 10=D4=C220=C8=D5, =CF=C2=CE=E76=CA=B129=B7=D6, Brian Drummond <brian_dru= mm...@btconnect.com> wrote: > On Mon, 19 Oct 2009 18:16:47 -0700 (PDT), vcar <hi...@163.com> wrote: > >Anybody help?? > > What happened when you tried the previous suggestion? > > - Brian I tried different seed in MAP/PAR, it is not working. And I think it is not a good practice on relying seed change in timing closure.Article: 143678
The ideal outcome is everyone get one or more FPGA boards, ( I'd like 4 or 5 ), with a fairly large FPGA + power supply + JTAG config + several IO connectors for $200-$250 per board. Daughter cards can be connected anyway you wish. My other possibility is to connect several cheap exisitng boards together to form a FPGA cluster for larger design implementation. Any design will have to be suitably partitioned between the FPGAs. "nobody" <cydrollinger@gmail.com> wrote in message news:55630cde-7e03-4483-a250-68d9583369fd@12g2000pri.googlegroups.com... > newbie, > > I would be interested. Having just completed a similar project, having > posted a similar topic, and found a lot of interest, what is your > ideal outcome of this project? On the topic of daughter boards what if > the they were connected to themselves board to board like, bga, no > cost? > > Cy Drollinger >Article: 143679
HELP!Article: 143680
On Oct 21, 8:11=A0am, Tier Logic <jeff.ka...@gmail.com> wrote: > HELP! we should start giving awards for this like posts! AnttiArticle: 143681
Howdy All,
I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with
custom XBD file, but I am having troubles using the DDR3 memory.
The I try to compile it I get:
ERROR:MDT - issued from TCL procedure "check_partno" line 21
DDR2_SDRAM (mpmc) -
The parameter C_MEM_PARTNO=EBE52UD6AJUA-6E-E is not found in the
memory
database.
ERROR:MDT - platgen failed with errors!
I don't know how to fix this problem and all faqa/ xilinx help
etc, has been fruitless.
Anybody know how to fix that problem ?
Thanks,
rudi
Article: 143682
Howdy All,
I have a HTG-V5-DDR3-PCIE-FX100 development board. It comes with
custom XBD file, but I am having troubles using the DDR2 memory.
(It has both ddr2 and ddr3 memory).
The I try to compile it I get:
ERROR:MDT - issued from TCL procedure "check_partno" line 21
DDR2_SDRAM (mpmc) -
The parameter C_MEM_PARTNO=EBE52UD6AJUA-6E-E is not found in the
memory
database.
ERROR:MDT - platgen failed with errors!
I don't know how to fix this problem and all faqa/ xilinx help
etc, has been fruitless.
Anybody know how to fix that problem ?
Thanks,
rudi
Article: 143683
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi NG,
thanks to all your help, the design is now working quite flawlessly. I
implemented a Reset counter _within_ the partial module an asynchronly reset
all relevant FSMs to the 'idle' state. When resetcounter reaches zero, the
FSMs start doing their job.
Thanks to all of you.
- - --
(`/\
`=\/\
`=\/\
`=\/
_\___ best regards
) ( -- Fabian Schuh
( INK )
\___/
Fabian Schuh <usenet@xeroc.org> schrieb:
> Hi NG,
>
> I have got a partial Design with different CAN-Modules to be partial
> reconfigured. Most of the time the reconfiguration works quit flawlessly.
> Anyway sometimes (unpredictable) the FSMs in my design stop.
>
> In more courious tests i found out, that some FSMs enter two states at the
> same
> time:
> (fsm_state = idle & fsm_state=error_frame) == true
>
> Can anyone tell me if there is an initial fsm state after partial
> reconfiguration? Any Xilinx-sources on this topic?
>
> using: virtex-2
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=kj4z
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Article: 143684
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Hash: SHA1
Woops,
thats, what happens if you edit an allready gpg-signed message.
Sorry for that.
- --
(`/\
`=\/\
`=\/\
`=\/
_\___ best regards
) ( -- Fabian Schuh
( INK )
\___/
Fabian Schuh <usenet@xeroc.org> schrieb:
>
> Hi NG,
>
> thanks to all your help, the design is now working quite flawlessly. I
> implemented a Reset counter _within_ the partial module an asynchronly reset
> all relevant FSMs to the 'idle' state. When resetcounter reaches zero, the
> FSMs start doing their job.
>
> Thanks to all of you.
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MawAoLmcY/HArtvCfeasJFYcD1vwiS05
=MpL8
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Article: 143685
This message is in MIME format. The first part should be readable text,
while the remaining parts are likely unreadable without MIME-aware tools.
--8323328-942325020-1256122224=:30892
Content-Type: TEXT/PLAIN; charset=ISO-8859-1
Content-Transfer-Encoding: QUOTED-PRINTABLE
On Tue, 20 Oct 2009, Rickman asked:
|-------------------------------------------------------------------------|
|"On Oct 20, 9:47=A0am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> =
|
|wrote: |
|> On Sun, 18 Oct 2009, Rickman wrote: |
|> |
|> |---------------------------------------------------------------------||
|> |"[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0||
|> |[..] =A0My copy of ispLever from Lattice will =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0||
|> |not run compile or simulate because neither of these tools will run =A0=
||
|> |due to the license expiring. =A0[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ||
|> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ||
|> |[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ||
|> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ||
|> |So now I am trying to use the Xilinx Webpack to allow me to continue ||
|> |working until I can get a new license file, but it won't run either."||
|> |---------------------------------------------------------------------||
|> |
|> Xilinx Webpack used to be licensed such that it was forbidden to use |
|> it for Lattice FPGAs. I do not recall that prohibition being removed. |
| |
|How is this about Lattice FPGAs? I'm trying to compile VHDL code and |
|simulate it. |
| |
|Rick" |
|-------------------------------------------------------------------------|
Hello again,
Perhaps you are not targeting Lattice silicon, but I thought you were. From
WWW.Xilinx.com/ise/license/license_agreement.htm
:
"[..]
4. Restrictions.
(a) Special Use Restrictions. No right is granted hereunder to
use the Software [..]
to [..] develop designs for non-Xilinx Devices; however,
Licensee may port ASIC designs to Xilinx Devices for the purpose
of prototyping and verification. [..]
[..]"
I do not know why an employee of Xilinx did not seem to bother to
mention this in this thread.
Yours sincerely,
Colin Paul
--8323328-942325020-1256122224=:30892--
Article: 143686glen herrmannsfeldt wrote: > rickman <gnuarm@gmail.com> wrote: >> On Oct 20, 3:21?pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > (snip) > >>> IBM consistently numbered the MSB 0 on S/360, S/370, XA/370, >>> ESA/370, ESA/390, and z/Architecture. > > (snip) >>> Even more, z/ can operate on code using 64, 31, or 24 bit addressing >>> as appropriate, and instructions change as the addressing mode changes. > >> How are the bits in the address bus numbered? I would find it >> extremely confusing to deal with an address where the lsb is numbered >> N where N varies depending on the size of the address range. > > If by 'address bus' you mean the physical hardware, that is a separate > question from the architecture. > > Otherwise, the numbering changed in z/, but is internally consistent. > > For S/360, 24 bit addresses are in bits 8 to 31 of general registers, > for example, and the address as stored in the PSW is bits 40 to 63. > > z/ extended to 64 bits, so 24 bit addresses are in bits 40 to 63, > 31 bit in 33 to 63, and 64 bit addresses in bits 0 to 63. > > That only comes up in reading the descriptions of the instructions. > This is "nice and consistent" ?? The bit numbering for the same address varies according to the size of the register, and the significance of a bit of a given number varies according to the register, the bit width, and the machine variant. I'll agree that much of this is hidden from the programmer, and that you can get used to it, but it's still inconsistent and it's still messy. I've dealt with this in the context of PPC microcontrollers - it is a big pain in the neck, and it's very easy to get wrong. Virtually everything else in the electronics world numbers bits consistently from 0 for the LSB - the PPC sticks out like a sore thumb and means that you need to invert the bus numbering when connecting it to external memory. Internally, when programming these things, you get the joys of figuring out which bits are which in the documentation, and how that corresponds to reality. The manual might tell you a hardware register is theoretically 64 bits, with the field you are interested in from bits 56 to 59. However, perhaps only the lower 32 bits of the register are implemented, so the actual bits are 24 to 27. You then have to translate this into sensible bit numbers, 4 to 7, so that you can use them in software. All in all, reverse bit numbering is a big waste of time and effort, and a big cause of mistakes. And for PPC devices (at least, those I have looked at) with 64-bit architectures, the external databus is numbered consistently with the 32-bit devices. Thus the LSB of the data and address buses stays at 31. So the upper half of the databus runs from D-1 to D-32 as the MSB. Internally, of course, the registers are numbered with bit 0 as the MSB and bit 63 as the LSB. Thus bit 0 in a data register corresponds to pin D-32 on the PPC, matching net D63 on any external memory bus. Yes, "nice and consistent" is just the phrase... > In actual coding, (software) one can write a loop in whichever > way one wants. The hardware will execute it independent of the > thought process of the programmer. > I was under the impression that programming was about getting the hardware to execute /dependent/ on the thoughts of the programmer! > It never confused me. > I've not use the Power architecture, only some PowerPC devices, but I have to admit it has confused me on occasion, and irritated and frustrated me more often than that. mvh., DavidArticle: 143687
Does anyone have any surplus on any of the Stratix II FPGA. Small or large quantities would help. Thanks, Jon E. Hansen (949)864-7745Article: 143688
On Oct 21, 6:50=A0am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > On Tue, 20 Oct 2009, Rickman asked: > > |------------------------------------------------------------------------= -| > |"On Oct 20, 9:47=A0am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> = =A0 =A0 | > |wrote: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | > |> On Sun, 18 Oct 2009, Rickman wrote: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| > |> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= | > |> |---------------------------------------------------------------------= || > |> |"[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|| > |> |[..] =A0My copy of ispLever from Lattice will =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0|| > |> |not run compile or simulate because neither of these tools will run = =A0|| > |> |due to the license expiring. =A0[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 || > |> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 || > |> |[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 || > |> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 || > |> |So now I am trying to use the Xilinx Webpack to allow me to continue = || > |> |working until I can get a new license file, but it won't run either."= || > |> |---------------------------------------------------------------------= || > |> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= | > |> Xilinx Webpack used to be licensed such that it was forbidden to use = =A0 | > |> it for Lattice FPGAs. I do not recall that prohibition being removed. = =A0| > | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | > |How is this about Lattice FPGAs? =A0I'm trying to compile VHDL code and = =A0 =A0| > |simulate it. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | > | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | > |Rick" =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| > |------------------------------------------------------------------------= -| > > Hello again, > > Perhaps you are not targeting Lattice silicon, but I thought you were. Fr= om > WWW.Xilinx.com/ise/license/license_agreement.htm > : > "[..] > > 4. =A0 =A0 =A0 =A0 =A0 =A0 Restrictions. > > =A0 =A0 (a) Special Use Restrictions. =A0No right is granted hereunder to > =A0 =A0 use the Software [..] > =A0 =A0 to [..] develop designs for non-Xilinx Devices; however, > =A0 =A0 Licensee may port ASIC designs to Xilinx Devices for the purpose > =A0 =A0 of prototyping and verification. [..] > > [..]" > > I do not know why an employee of Xilinx did not seem to bother to > mention this in this thread. > > Yours sincerely, > Colin Paul I guess their is a fine distinction to how you might interpret that. I always try to write my code to be portable between different manufacturers. Before I ship any product I run the code through all of the tools at my disposal since each one will find some different usage that is questionable even if it works. Also, I prefer to have code that is easily ported across manufacturer's product lines so that I can easily switch to different brands depending on circumstances. In this case, I wonder if they would consider compiling with their tools to be a violation of this part of the license. RickArticle: 143689
On Oct 20, 6:55=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: > I have ISE 11.1 and the DCM does exist in the coregen for this release. I= s > it not in your version of coregen or is it grayed out? Your image doesnt > seem to work. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Hi there, Not sure it will help but I had a similar problem in the past. In my case was cause by me, at the beginning of the project creation, choosing the right FPGA device but in version Automotive. Meaning "Automotive Spartan 3A" instead of "Spartan 3A" . Doind so all IP models in CORE gen were grayed out. Suggestion: make sure you chose the right FPGA device when you start you project in ISE. cheers fab.Article: 143690
The way I handle this sort of problem in my PPC designs is I have a very simple custom peripheral, which simply exposes a DCR bus to the top-level code. /Mikhail "hvo" <hai.vo@synrad.com> wrote in message news:fPWdncDZd9QIh0PXnZ2dnUVZ_sWdnZ2d@giganews.com... > Hi, > > I am trying to connect an IO signal from my microblaze to the external > top-level vhdl code without using xilinx GPIO IP. My question is, > couldn't > I make a port definition in the MHS file and connect to it? for example, > > PORT Test_IO = Test_IO, DIR = I // an external port not defined by > gpio > ip > > and then on my top-level VHDL I would connect to it in the port map by > > Test_IO => somesignal, > > My second question is how can I read the signal value in microblaze. With > xilinx's GPIO, I could read base address to get the value. But now > there's > no base address associated with Test_IO. > > Best Regards > > HV > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface on > http://www.FPGARelated.comArticle: 143691
Hi,
After last upgrade of my Debian/testing system which I use for FPGA
development the Xilinx USB programmer stopped to work.
After some research I've found, that the syntax of udev rules has changed,
and it is necessary to replace $TEMPNODE with $tempnode:
=== xusbdfwu.rules ====
SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0008", MODE="666"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0007", RUN+="/sbin/fxload -v -t fx2 -I /usr/local/firmware/xusbdfwu.hex -D $tempnode"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0009", RUN+="/sbin/fxload -v -t fx2 -I /usr/local/firmware/xusb_xup.hex -D $tempnode"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="000d", RUN+="/sbin/fxload -v -t fx2 -I /usr/local/firmware/xusb_emb.hex -D $tempnode"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="000f", RUN+="/sbin/fxload -v -t fx2 -I /usr/local/firmware/xusb_xlp.hex -D $tempnode"
BUS=="usb", ACTION=="add", SYSFS{idVendor}=="03fd", SYSFS{idProduct}=="0013", RUN+="/sbin/fxload -v -t fx2 -I /usr/local/firmware/xusb_xpr.hex -D $tempnode"
=== end of rules ===
I hope, that this info may be useful for others, experiencing the above problem.
--
HTH & Regards,
Wojtek
Article: 143692rickman <gnuarm@gmail.com> wrote: (snip on licensing for different vendors) > I guess their is a fine distinction to how you might interpret that. > I always try to write my code to be portable between different > manufacturers. Before I ship any product I run the code through all > of the tools at my disposal since each one will find some different > usage that is questionable even if it works. Also, I prefer to have > code that is easily ported across manufacturer's product lines so that > I can easily switch to different brands depending on circumstances. > In this case, I wonder if they would consider compiling with their > tools to be a violation of this part of the license. I agree. The one that comes up more often is specific IP generated for specific devices. If, for example, you used Xilinx FIFO generator, the result might be licensed only for Xilinx FPGAs. For portable code, you should be able to simulate on different simulators, while deciding which device you want to target. (Even if you already have PC boards made, you could still change your mind.) -- glenArticle: 143693
Whoa! let me reign this coach back! I am one man, educated in the Gallatin Valley with an MSEE. I am having trouble keeping my doors open in case a client who happens to have cash needs my ability to solve the problem. Talking about scientists of world caliber and mathematicians having advanced formulas needing to be calculated is not even in the stadium of where I was thinking about playing, period. There exists problems needing solutions to which I have the skill set, but pairing these items is not something I have had success. I exist and I realize their are others that are experiencing the same, with slightly or wildly different skill sets. Alone I can get things done and have for a small set of clients, but together, even world wide, with the internet we could do much more. Let me provide one scenario that might be a quick and easy idea. I have an account on GURU.com which tries to pair work to workers, but I look like every other individual on the sight, India, Canada, and Wherever, so why choose me? Now if a collection of individuals got together and developed an account it looks more like a firm many hands producing on the capital someone spends to get the job done. That is actually the way it works together we get the job done quick and capable. But that is one idea among one individual, now put several individuals together and see what we can get done.Article: 143694
wzab wrote:
> After last upgrade of my Debian/testing system which I use for FPGA
> development the Xilinx USB programmer stopped to work.
> After some research I've found, that the syntax of udev rules has changed,
> and it is necessary to replace $TEMPNODE with $tempnode:
I have run into similar problems with file name references
that work on the windows side, but not on linux because
of case mismatches.
For example,
aa.vhd on a file list or script may or may not match the file aA.vhd.
-- Mike Treseler
Article: 143695On Oct 20, 11:08=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Oct 21, 8:11=A0am, Tier Logic <jeff.ka...@gmail.com> wrote: > > > HELP! > > we should start giving awards for this like posts! > > Antti Hey, it was just a joke. I wanted to test this thing. My favorite posts on here are the "Can you do my homework for me?" posts. Those are the best! But it does remind me of the most famous ever Xilinx FAE conference question. "What the hell, I have to call another guy so he can come check if the done pin goes high". Something like that. That was hilarious! JeffArticle: 143696
I think I know the answer, but want to make sure I'm not missing something... Can I use a crystal as my clock source for the Xilinx Spartan 3A FPGA? If so, how? Not to insult your intelligence, but please realize the difference between a crystal oscillator and a crystal. I've always used a crystal oscillator which outputs the clock right into the FPGA. Any info is appreciated. Thanks, DaleArticle: 143697
On Oct 21, 12:12=A0pm, Dale <dale.prat...@gmail.com> wrote: > I think I know the answer, but want to make sure I'm not missing > something... > Can I use a crystal as my clock source for the Xilinx Spartan 3A > FPGA? =A0If so, how? =A0Not to insult your intelligence, but please > realize the difference between a crystal oscillator and a crystal. > I've always used a crystal oscillator which outputs the clock right > into the FPGA. =A0Any info is appreciated. > > Thanks, > Dale Dale, stick with the oscillator. Yes, you can drive a xtal with one output pin, and use a second pin as input, with some reistors and a capacitor in-between, and it might work, most of the time. But it is not worth the trouble. A xtal oscillator uses a dedicated analog chip, made for this special purpose. The FPGA is a digital device, and not good at such low-power analog functions. 20 years ago, the XC3000 series had 2 dedicated pins to interface to a xtal. That solution caused us no end of grief. Stay with the oscillator! Peter Alfke, formerly Xilinx Applications.Article: 143698
Tier Logic wrote: > My favorite posts on here are the "Can you do my homework for me?" > posts. or: "I have to do brain surgery using vhdl. Any ideas?" ;)Article: 143699
On Oct 22, 8:12=A0am, Dale <dale.prat...@gmail.com> wrote: > I think I know the answer, but want to make sure I'm not missing > something... > Can I use a crystal as my clock source for the Xilinx Spartan 3A > FPGA? =A0If so, how? =A0Not to insult your intelligence, but please > realize the difference between a crystal oscillator and a crystal. > I've always used a crystal oscillator which outputs the clock right > into the FPGA. =A0Any info is appreciated. Yes, you can, but ideally you need an oscillator gate - which can be SOT23 sized. That can be a 1GU04 series, or 2GU04 if you want to improve the slew rate into the FPGA Or, you can use ones designed to work with a Crystal 74LVC1GX04 74AUP1Z04 74AUP1Z125 (etc) -jg
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