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John Adair <g1@enterpoint.co.uk> wrote: (snip) > The other aspect that I ddn't see mention of is that the larger > devices are not usually covered by the "free" versions of tools so you > may want to qualify how big a device you want. I believe that isn't quite right. The high-end devices aren't covered by the free tools. Last time I checked the large Spartan's were, but not the large Virtex. Comparing the two families isn't so easy, though, but the OP did specify Spartan. -- glenArticle: 143626
On 14 Pa=C5=BA, 16:14, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > =C2=A0Please advise me in any sense. > > If you've any sense you'll pick a more realistic final year project! > > Sorry to be blunt but from the questions you're asking there's no > way you'll get this finished. > > Nial Why the promotor - lecturer has approved this kind of project? Where is the common sense? Kolopipo, change the project if you can. Kind Regards, Jerzy GburArticle: 143627
Yeah, I am fine with that. I'm just not happy with the license expiring and having to be renewed. That can happen at very inconvenient times (like this weekend). It's not like I use the software every day. I guess I'll have to add license expiration to my calendar and make sure I keep it up to date even when I'm not using the tool. Rick On Oct 18, 7:35=A0pm, Charles Gardiner <inva...@invalid.invalid> wrote: > Regarding Lattice ispLever, > > this is a statment I got from them a while back: > > "The Warranty maintenance expiration and Third party OEM License feature > expiration are separate functions. Contractually we license the third > party tools annually from the latest license generation. You own the > license and we renew the features at any time regardless of the Warranty > maintenance status, for the life of the product. The Warranty > maintenance allows for distribution of new versions of the tool suite as > they are released." > > I guess that means if you renew maintenance you always get the latest, > if you don't, they lock <ou into the last maintained version of the OEM > tools =A0(e.g. Synplify) > > rickman schrieb: > > > The dreaded License expiration has bitten me in the butt again. =A0I > > don't recall if I had this exact same problem before, but I am pretty > > sure I was told at one point that my tools would not expire when > > maintenance ran out, because that is what is stuck in my head. > > However, that is not the case. =A0My copy of ispLever from Lattice will > > not run compile or simulate because neither of these tools will run > > due to the license expiring. =A0Maybe the deal is that I have to update > > the license file periodically, but I just did that earlier this > > year. > > > The real problem is that I can't get anyone to talk straight with me > > about this. =A0I had an email exchange with licensing the last time I > > updated the license and they never answered my questions about this. > > > So now I am trying to use the Xilinx Webpack to allow me to continue > > working until I can get a new license file, but it won't run either. > > I think that it somehow is using networking to communicate between > > processes and it won't go through the firewall! =A0Talk about making > > simple things difficult! =A0This is the error message I get. > > > IPC connection failed port=3D58676 hostname=3Dlocalhost > > > I am using Sophos for AVS and firewall. =A0Anyone know what has to be > > turned on to allow ISE to talk to the simulator? > > > Rick > >Article: 143628
Thomas Stanka wrote: > On 15 Okt., 10:30, Fabian Schuh <use...@xeroc.org> wrote: >> In more courious tests i found out, that some FSMs enter two states at the same >> time: >> (fsm_state = idle & fsm_state=error_frame) == true > > This is only possible, if your statemachine uses one-hot encoding. In > that case I would use some logic that recovers from illegal (unused) > states. Yep, Xilinx does use One-hot per default. We checked this in the syntheses report > In a later post you ask, if a when-others statement in VHDL is > sufficient to obtain this function. > No that is unfortunately not the case for some synthesis tools. Some > tools inferring one-hot-fsm allow to select self recovering one-hot- > fsm. For other tools you need to figure out how to avoid this. Good to know. > For some fsm it will be best practice to start cycling trough all > unused states before entering the usual idle state. This will force > the synthesis tool to cover every state and includes a dedicated way > to recover from "unused" states. Ok. first we are trying to use the 'safe_implement' attribute offered by xilinx synthesis tool, first. thanks for the advice. > bye ThomasArticle: 143629
On Oct 19, 2:26=A0am, Fabian Schuh <use...@xeroc.org> wrote: > KJ <kkjenni...@sbcglobal.net> schrieb:> That's tool dependent. =A0Check f= or some > > The illegal state is just a symptom of the problem. =A0The problem is > > (most likely) not meeting timing requirements (the other possibility > > is inadequate power to the chip). =A0The correct solution fixes the > > problem, not the symptom. > > Yep. I know the timing issues. Unfortunatelly, there's atm no way to solv= e > them, as parts of the design must run at 200MHz. Anyway the FSMs are cloc= ked > 20MHz, and the timing checkes passed. > Timing checks don't default to checking clock domain crossings (async inputs being a particular form of that). You have to specifically check an option to get that analysis. In any case, you typically have to hand check those crossings anyway to insure you've got the synchronization flops. KJArticle: 143630
Bigger Spartan's are not covered by Webpack version either details http://www.xilinx.com/publications/matrix/Software_matrix.pdf. Altera also has something similar in a limit from my memory. John Adair Enterpoint Ltd. - Home of Merrick. The HPC Solution. On 19 Oct, 09:22, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > (snip) > > > The other aspect that I ddn't see mention of is that the larger > > devices are not usually covered by the "free" versions of tools so you > > may want to qualify how big a device you want. > > I believe that isn't quite right. =A0The high-end devices aren't > covered by the free tools. =A0Last time I checked the large Spartan's > were, but not the large Virtex. =A0Comparing the two families isn't > so easy, though, but the OP did specify Spartan. > > -- glenArticle: 143631
Hi,all
I am an DSP engineer and new to FPGA,
but hope to learn more about it. FPGAs are
more and more used in various applications.
In my mind, FPGAs are expensive and high
power consumption, but some FPGAs are
becoming cheaper.
Fist of all I hope to learn the performance/price.
Is available a price list for each FPGA device?
I find a selection guide on xilinx's websit, and
price information is not available. I search it
on the internet but no helpful information is
found.
Can anyone tell me where to find such information?
Thanks.
Best Regards
Jogging
Article: 143632There isn't a single list as such and it all depends on your application. Some devices have a bias towards DSP with more multipliers and ram e.g. Xilinx Spartan-3A DSP family but even the smallest, cheapest, devices have application capability. It may be worth giving the group some more detail of what type of system you might be trying to design to narrow down the responses. John Adair Enterpoint Ltd. On 19 Oct, 13:09, jogging <joggings...@gmail.com> wrote: > Hi,all > =A0 =A0 =A0 I am an DSP engineer and new to FPGA, > but hope to learn more about it. =A0FPGAs are > more and more used in various applications. > In my mind, FPGAs are expensive and high > power consumption, but some FPGAs are > becoming cheaper. > > Fist of all I hope to learn the performance/price. > Is available a price list for each FPGA device? > I find a selection guide on xilinx's websit, and > price information is not available. I search it > on the internet but no helpful information is > found. > > Can anyone tell me where to find such information? > Thanks. > > Best Regards > JoggingArticle: 143633
Hi, trying to debug a design and look for a way to inspect the actual data that are inside a FIFO which has been generated with the core generator. I have turned off all optimization in order to see process variables etc., but all I find is a lot of control signals and generics. I looked into the behavioural code and found that the fifo is implemented as a linked list. I wonder if anybody in the group has been successful in looking at the data stream passing through. I was hoping for a nice std_logic_vector, but obviously this is not the case. (At least from what I find) Modelsim 6.4 and VHDL with ISE 10.3 -- SvennArticle: 143634
jogging wrote: > Fist of all I hope to learn the performance/price. > Is available a price list for each FPGA device? > I find a selection guide on xilinx's websit, and > price information is not available. I search it > on the internet but no helpful information is > found. The is no such thing as FPGA price list. The prices are very dependant on the volumes, from where they are bought, the size of the company as a customer to the vendor etc. You can get first level approximations for the upper limit of price from the distributors The price difference between some small company and big volume buyer can be substantial, sometimes 5-10x. --KimArticle: 143635
Not sure about FIFOs but with Xilinx block ram you can just go to the Modelsim memory window and look at the contents. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143636
On Oct 19, 8:56=A0am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > Hi, > trying to debug a design and look for a way to inspect the actual data > that are inside a FIFO which has been generated with the core > generator. I have turned off all optimization in order to see process > variables etc., but all I find is a lot of control signals and > generics. I looked into the behavioural code and found that the fifo > is implemented as a linked list. I wonder if anybody in the group has > been successful in looking at the data stream passing through. I was > hoping for a nice std_logic_vector, but obviously this is not the > case. (At least from what I find) > > Modelsim 6.4 and VHDL with ISE 10.3 > > -- > Svenn It sounds like Core Generator has given you the "Behavioral" model which is not cycle accurate. In fact at time zero you should get a warning to this effect. If you want to dig into FIFO internals you'll need the structural model, which you can generate by setting your CoreGen project options. Even then it may be difficult to see what's in the FIFO. If you're willing to believe that the CoreGen FIFO just works, you can build a very simple FIFO model and hook it up in parallel to the CoreGen FIFO and inspect what is in your model. Just be sure to only write to your model when the CoreGen reports not full and only read when CoreGen reports not empty. This and a common reset should keep the models in sync and you can easily inspect the contents of your model. Regards, GaborArticle: 143637
On Oct 19, 9:03=A0am, Kim Enkovaara <kim.enkova...@iki.fi> wrote: > jogging wrote: > > Fist of all I hope to learn the performance/price. > > Is available a price list for each FPGA device? > > I find a selection guide on xilinx's websit, and > > price information is not available. I search it > > on the internet but no helpful information is > > found. > > The is no such thing as FPGA price list. The prices > are very dependant on the volumes, from where they are > bought, the size of the company as a customer to the > vendor etc. You can get first level approximations for the > upper limit of price from the distributors > > The price difference between some small company and big > volume buyer can be substantial, sometimes 5-10x. > > --Kim However if all you want is relative pricing, e.g. which Xilinx part costs more than which other Xilinx part, you can get the "web" price (something like a retail list price, most customers pay considerably less) from distributor sites like Avnet or NuHorizons. Unfortunately this won't give you an apples to apples comparison between vendors. At our company we often go to our preferred distributor with a big list of parts to price out in various volumes before choosing one for a new product. Regards, GaborArticle: 143638
jogging wrote: > Fist of all I hope to learn the performance/price. > Is available a price list for each FPGA device? > I find a selection guide on xilinx's websit, and > price information is not available. I search it > on the internet but no helpful information is > found. Try Digikey, it has prices for Xilinx parts. The Altera parts are nice, too, and the prices are in their online shop. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 143639
On Oct 16, 4:07=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Gabor <ga...@alacron.com> wrote: > > (snip) > > > Xilinx XST ALWAYS encodes state machines one-hot unless you force > > it to use your encoding (see synthesis options). =A0Are you sure > > that your dynamic portion has a reset term for starting up the > > FSM logic? =A0One of my favorite approaches is to add a post-reset > > state that just continues onto the idle state. =A0Then when reset > > is released all of the states other than idle cannot be reached > > until the post-reset state has become inactive, effectively a > > synchronous reset release. > > If you use the state register somewhere else, such as a module > output, then it shouldn't convert to one hot. =A0(or it should > properly decode the one hot value.) > > The bug was with Quartus many years ago, I believe fixed while > I was still working on that project. > > It was a simple four state FSM to accept data one byte at a > time and output to a 32 bit FIFO. =A0The state variable was two > bits, and Quartus gave me the low two bits of the one hot register. > > Do you mean XST will give you the wrong output in that case? > > It seems that what Quartus expected was a case statement > to select the next state and a separate case statement to do > whatever you wanted to do in that state. =A0I wrote mine as > a single case statement and, in addition, used the state variable > outside the module. > > -- glen Xilinx is very aggressive in replacing your state machine logic with one-hot. Even when you use the encoded state elsewhere it will implement the on-hot machine and use encoding logic to replicate the original state variable. This often leads to the zero-hot or multiple-hot states witnessed by the OP. Adding a default state does nothing to prevent this, since in one-hot the tool needs to infer logic for all states off in order to make a safe implementation. This is not the default for Xilinx synthesis. You need to turn on "safe" encoding. In any case it would be better to provide a local reset for the reconfigured logic than try to fix the problem with state encoding. Regards, GaborArticle: 143640
On Oct 16, 6:59=A0pm, rickman <gnu...@gmail.com> wrote: > On Oct 15, 1:10=A0pm, Andy Peters <goo...@latke.net> wrote: > > > > > On Oct 15, 8:14=A0am, rickman <gnu...@gmail.com> wrote: > > > > On Oct 15, 12:51=A0am, GrIsH <grishkun...@gmail.com> wrote: > > > > > On Oct 14, 11:35=A0am, rickman <gnu...@gmail.com> wrote: > > > > > > I have never worked with SLV in the 0 to N direction. =A0To be ho= nest, I > > > > > don't remember the details of how assignments are made between bu= ses > > > > > using different directions of indexes. =A0I wouldn't expect any > > > > > surprises, but then I have no experience with them. =A0Is there a= reason > > > > > that you are using 0 to N numbering instead of N downto 0 on your= SLV > > > > > arrays? =A0This may not be a problem, but if you are stuck, why u= se this > > > > > uncommon convention? > > > > > =A0 =A0 for IP2Bus_Data we are not allowed to make this convention = of N > > > > downto 0 that's why i didn't use this convention. > > > > Ok, it shouldn't matter really, as long as you use it correctly. =A0C= an > > > you explain what this bus is and why it is 0 to 31? =A0Is this a port= on > > > the uBlaze? =A0Where exactly does this restriction come from. =A0Why = do > > > you assign your counter result to bits 16 to 31? > > > MicroBlaze is big endian. Bits 16 to 31 are the two least significant > > bytes in a 32-bit word (bit 31 is the right-most bit). > > > -a > > I wonder why they do that. =A0I have only seen bit zero as the most > significant bit in a handful of designs and I expect the first was > done for fairly obscure reasons and the rest were done to be > compatible. =A0Did the uBlaze need to be compatible with something in > this regard? > > Rick The historical reason is that IBM's Power PC is big endian, so all of the V2 pro tools were big endian, and microBlaze came later. Sticking with big endian at that stage in the game was better than re-writing a bunch of supporting software. Regards, GaborArticle: 143641
On Oct 19, 9:58=A0am, Gabor <ga...@alacron.com> wrote: > On Oct 16, 6:59=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Oct 15, 1:10=A0pm, Andy Peters <goo...@latke.net> wrote: > > > > On Oct 15, 8:14=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Oct 15, 12:51=A0am, GrIsH <grishkun...@gmail.com> wrote: > > > > > > On Oct 14, 11:35=A0am, rickman <gnu...@gmail.com> wrote: > > > > > > > I have never worked with SLV in the 0 to N direction. =A0To be = honest, I > > > > > > don't remember the details of how assignments are made between = buses > > > > > > using different directions of indexes. =A0I wouldn't expect any > > > > > > surprises, but then I have no experience with them. =A0Is there= a reason > > > > > > that you are using 0 to N numbering instead of N downto 0 on yo= ur SLV > > > > > > arrays? =A0This may not be a problem, but if you are stuck, why= use this > > > > > > uncommon convention? > > > > > > =A0 =A0 for IP2Bus_Data we are not allowed to make this conventio= n of N > > > > > downto 0 that's why i didn't use this convention. > > > > > Ok, it shouldn't matter really, as long as you use it correctly. = =A0Can > > > > you explain what this bus is and why it is 0 to 31? =A0Is this a po= rt on > > > > the uBlaze? =A0Where exactly does this restriction come from. =A0Wh= y do > > > > you assign your counter result to bits 16 to 31? > > > > MicroBlaze is big endian. Bits 16 to 31 are the two least significant > > > bytes in a 32-bit word (bit 31 is the right-most bit). > > > > -a > > > I wonder why they do that. =A0I have only seen bit zero as the most > > significant bit in a handful of designs and I expect the first was > > done for fairly obscure reasons and the rest were done to be > > compatible. =A0Did the uBlaze need to be compatible with something in > > this regard? > > > Rick > > The historical reason is that IBM's Power PC is big endian, so > all of the V2 pro tools were big endian, and microBlaze came > later. =A0Sticking with big endian at that stage in the game > was better than re-writing a bunch of supporting software. > > Regards, > Gabor Are you saying that on the Power PC they number bits in the data bus with 0 as msb and 31 as lsb? How about address bits, is the lsb numbered 31 and the msb numbered 0? I would find that very confusing. I could care less if the byte addressing is big-endian or little- endian. I don't see that having much import when defining the bits in a bus. RickArticle: 143642
On Oct 18, 10:21=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Oct 18, 11:37=A0am, Ben Jones <benj...@gmail.com> wrote: > > > > Just because FPGAs have to cobble together logic to create a latch > > > (and cause potential timing issues in doing so) > > > This is not true - or at least, it's not true of all FPGAs. > > Correct, I should've said "may have to cobble..." > > > Spartan and Virtex lines, even in their latest incarnations (V6/S6), > > allow the memory elements in every slice to be configured either as D- > > type flip-flops or as transparent latches. > > Making use of 'hard' latches that may be available in a given target > is OK as long as one also verifies that the hard latches actually get > used in each and every instance. =A0A latch designed by the silicon guys > is not the same as one that has to be put together from logic arrays > (CPLDs) or lookup tables (FPGAs). =A0If one chooses the route of wanting > to make use of hard latches that are available, then one still has to > make sure that the synthesized output does indeed end up using the > hard latch and not implement the latch in logic because the tool > didn't quite spot it. =A0I don't know if the tools support reporting of > latches that have been implemented the two different ways...after all, > a 'latch' is really anything that has a combinatorial logic path that > loops back on itself, not just the canonical expression Q <=3D D when > (CE=3D'1'); > > Kevin Jennings Patent US6791387-"Feedback latch circuit and method therefor" is a good paper for Earle latch and other related latches. But it is not the latch Intel has used, neither is Actel 1010. Weng WengArticle: 143643
Hi,
I am trying to implement an interrupt handler which only interrupts on the
rising edge of a gpio signal. So far, it always interrupt regardless of
input signal, rising or falling. here is my MHS snippit
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER HW_VER = 7.10.d
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_AREA_OPTIMIZED = 1
PARAMETER C_INTERRUPT_IS_EDGE = 1
PARAMETER C_EDGE_IS_POSITIVE = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
PORT MB_RESET = mb_reset
PORT Interrupt = Interrupt
END
BEGIN xps_gpio
PARAMETER INSTANCE = DIPs_4Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_IS_DUAL = 1
PARAMETER C_ALL_INPUTS_2 = 1
PARAMETER C_IS_BIDIR_2 = 0
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_DIPs_4Bit_GPIO_in
PORT IP2INTC_Irpt = gpio_interrupt
PORT GPIO2_in = fpga_channel_2_in
END
BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_KIND_OF_INTR = 0xFFFFFFFF
PARAMETER C_KIND_OF_EDGE = 0xFFFFFFFF
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Irq = Interrupt
PORT Intr =
Ethernet_MAC_IP2INTC_Irpt&xps_timer_1_Interrupt&gpio_interrupt
END
----------------------------------------------------------------------------
here is my main code:
int main(void)
{
// init the gpio interrupt
XGpio_Initialize(&Gpio, XPAR_DIPS_4BIT_DEVICE_ID);
// enable global interrupt
XGpio_InterruptGlobalEnable(&Gpio);
// enable channels 1 and 2
XGpio_InterruptEnable(&Gpio, INTR_CHANNEL2_MASK);
XGpio_InterruptEnable(&Gpio, INTR_CHANNEL1_MASK);
}
// static main thread in xilkernel
int main_thread()
{
// registers the interrupt handler
register_int_handler(DIPSWITCH_ID, handler, &Gpio);
// enable the interrupt
enable_interrupt (DIPSWITCH_ID);
// create a thread below
}
// interrupt handler function
void handler(void)
{
// first disable interrupt
disable_interrupt(DIPSWITCH_ID);
// process interrupt......
// Clear interrupt
XGpio_InterruptClear(&Gpio, INTR_CHANNEL1_MASK);
XGpio_InterruptClear(&Gpio, INTR_CHANNEL2_MASK);
// re-enable the interrupt
enable_interrupt(DIPSWITCH_ID);
}
------------------------------------------------------------------------
in my MHS file, I've defined the kind of interrupt to edge for both the
microblaze and interrupt controller and yet I always get an interrupt
everytime the gpio signal changes level.
Is there something i've overlooked?
Please help
Regards
---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com
Article: 143644I believe... You have the option enabled that generates an interrupt any time a gpio bit changes state. If this is not what you wanted, then don't do that... http://www.xilinx.com/support/documentation/ip_documentation/opb_gpio.pdf page 9 This has nothing to do with rising edge, or level, for the interrupt controller as the system will ensure that every time a gpio bit changes state, it generates an interrupt. AustinArticle: 143645
>I believe... > >You have the option enabled that generates an interrupt any time a >gpio bit changes state. > >If this is not what you wanted, then don't do that... > >http://www.xilinx.com/support/documentation/ip_documentation/opb_gpio.pdf > >page 9 > >This has nothing to do with rising edge, or level, for the interrupt >controller as the system will ensure that every time a gpio bit >changes state, it generates an interrupt. > >Austin > Yes I see the limitation of GPIO interrupts. There are no parameters to set the gpio to only generate an interrupt on a rising or falling edge. How else can I connect an external interrupt without using GPIO? Best Regards --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143646
hi, i'm having the same issue, i'd downloaded the last adept version software but got the same "onboard usb" in enumarated devices, i'm sure that board is perfect because the issue only is in the laptop, i have to use it in my desktop pc, but i need to work in laptop, i hope somebody help me thanks :)Article: 143647
Anybody help??Article: 143648
Anybody help??Article: 143649
On Mon, 19 Oct 2009 18:16:47 -0700 (PDT), vcar <hitsx@163.com> wrote: >Anybody help?? What happened when you tried the previous suggestion? - Brian
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