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Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: (snip on generating and using FSM) < Somewhere around 30-100 states it gets simpler to think of it < as software/microcode rather than a traditional FSM. That is, if you actually have to think about them. I worked on a pattern matching project some time ago where finite state machines were generated from the input strings. I had ones with millions of states, where the current state depended on the previous input data and which strings it partially matched. < Then you have to write an assembler. We used to start with the one < leftover from the last project. Anybody got a handy sample? Easier to write macros for an existing macro assembler. -- glenArticle: 141826
Yes, sorry about the confusion. The starting post is the detailed explanation of the circuit, but have been implementing along the way. The starting post description did just as it has been explained. The VHDL posted has a one second on and a one second off flash on the green led. the switches on 6 and 7 have the same functionality as the starting post. Mom switch 0 or 1 turns on the corresponding led 6 or 7 but it does not go off after release. Thank you for your consideration with my problem and your posts. CyArticle: 141827
On Jul 10, 4:45=A0pm, nobody <cydrollin...@gmail.com> wrote: > Yes, sorry about the confusion. The starting post is the detailed > explanation of the circuit, but have been implementing along the way. > The starting post description did just as it has been explained. The > VHDL posted has a one second on and a one second off flash on the > green led. does the flashing led work? this would indicate whether the cpld can properly drive the led.Article: 141828
On Jul 10, 8:52=A0am, nobody <cydrollin...@gmail.com> wrote: > Thanks for the replies: Alan, and Gabor. Below is the VHDL I appended > much of it so not to long but the logic for the switch is available as > well as a couple of lines for the UCF. I was not aware of the global > on keeper and pullup. I have tried the keeper or pullup in the ucf but > both have the same result as nothing in the UCF. re-reading gabor's response, i believe he is right. you have to use all keepers or all pullups. since the default for coolrunner2 is keeper (also called bus-hold), pullups in ucf are ignored and a warning given (did you ignore the warnings?). in ise processes: right click fit, select properties and change unused i/o pad termination and input and tristate i/o termination to pullup. or use an external pullup on the switch. note that pullups on the led outputs aren't required and aren't doing anything.Article: 141829
alan@nishioka.com <alan@nishioka.com> wrote: (snip) > > re-reading gabor's response, i believe he is right. you have to use > all keepers or all pullups. since the default for coolrunner2 is > keeper (also called bus-hold), pullups in ucf are ignored and a > warning given (did you ignore the warnings?). If I understand the original post, the LED goes from the output to Vcc, not to ground. (Hopefully with a resistor.) In that case, a pullup would not turn the LED on. The keeper may or may not have enough pull to keep an LED on. -- glenArticle: 141830
On Jul 10, 12:45=A0pm, [LinuxF8-64]GaLaKtIkUs=99 <taileb.me...@gmail.com> wrote: > Hi, > You just have to feedback the CLK0 to CLKFB! otherwise the DLL will > not lock :) > > On Jul 10, 4:40=A0pm, "muse_ee" <brian.bubn...@jhuapl.edu> wrote: > > > > > Hi, I'm trying to learn how to use the DCM's frequency synthesis capabi= lity > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock= . I > > used Xilinx Architecture wizard to generate the code and the clock > > multiplication works correctly in timing simulation. When I get to the > > bench to test however, I don't get a multiplied clock output - the line= is > > 0. I have a couple debug signals that tell me the following: > > > -75MHz, post BUFG looks fine (I see output from the FPGA) > > -DCM Lock is 0 > > -Status(2 downto 0) are all 0. > > > I've tried the design on 2 different boards, ruling out defective > > hardware. I'm really scratching my head here so I'd greatly appreciate = some > > help from a Xilinx guru! > > > Here is my VHDL for the clock multiplier (well, more accurately Xilinx'= s > > VHDL): > > =A0 =A0GND_BIT <=3D '0'; > > =A0 =A0CLKIN_IBUFG_OUT <=3D CLKIN_IBUFG; > > =A0 =A0CLKFX_BUFG_INST : BUFG > > =A0 =A0 =A0 port map (I=3D>CLKFX_BUF, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKFX_OUT); > > > =A0 =A0CLKIN_IBUFG_INST : IBUFG > > =A0 =A0 =A0 port map (I=3D>CLKIN_IN, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKIN_IBUFG); > > > =A0 =A0DCM_INST : DCM > > =A0 =A0generic map( CLK_FEEDBACK =3D> "NONE", > > =A0 =A0 =A0 =A0 =A0 =A0 CLKDV_DIVIDE =3D> 2.0, > > =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_DIVIDE =3D> 4, > > =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_MULTIPLY =3D> 5, > > =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_DIVIDE_BY_2 =3D> FALSE, > > =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_PERIOD =3D> 12.500, > > =A0 =A0 =A0 =A0 =A0 =A0 CLKOUT_PHASE_SHIFT =3D> "NONE", > > =A0 =A0 =A0 =A0 =A0 =A0 DESKEW_ADJUST =3D> "SYSTEM_SYNCHRONOUS", > > =A0 =A0 =A0 =A0 =A0 =A0 DFS_FREQUENCY_MODE =3D> "LOW", > > =A0 =A0 =A0 =A0 =A0 =A0 DLL_FREQUENCY_MODE =3D> "LOW", > > =A0 =A0 =A0 =A0 =A0 =A0 DUTY_CYCLE_CORRECTION =3D> TRUE, > > =A0 =A0 =A0 =A0 =A0 =A0 FACTORY_JF =3D> x"8080", > > =A0 =A0 =A0 =A0 =A0 =A0 PHASE_SHIFT =3D> 0, > > =A0 =A0 =A0 =A0 =A0 =A0 STARTUP_WAIT =3D> FALSE) > > =A0 =A0 =A0 port map (CLKFB=3D>GND_BIT, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKIN=3D>CLKIN_IBUFG, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DSSEN=3D>GND_BIT, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSCLK=3D>GND_BIT, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSEN=3D>GND_BIT, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSINCDEC=3D>GND_BIT, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 RST=3D>RST_IN, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKDV=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX=3D>CLKFX_BUF, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX180=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK0=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X180=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK90=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK180=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK270=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOCKED=3D>LOCKED_OUT, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSDONE=3D>open, > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 STATUS(7 downto 0)=3D>STATUS_OUT(7 down= to 0)); Alright, I tried adding a feedback signal between CLK0 and CLKFB, and changed the CLK_FEEDBACK attribute from "None" to "1X". This didn't have any effect.Article: 141831
A flip-flop is a device that stores either a 0 or 1. The state of a flip-flop is the value that it currently stores. The stored value can be changed only at certain times determined by a =93clock=94 input, and the new value may further depend on the flip-flop=92s current state and its =93control=94 inputs. This is to start discussions from scratch. What is clock input above? I need a wide understanding of it and its connections with other concepts. Step by step, however.Article: 141832
"dsa fsag" <johnkarry@gmail.com> wrote in message news:cacf2b21-88c8-43fc-ad61-62f1f91ad503@y7g2000yqa.googlegroups.com... A flip-flop is a device that stores either a 0 or 1. The state of a flip-flop is the value that it currently stores. The stored value can be changed only at certain times determined by a “clock” input, and the new value may further depend on the flip-flop’s current state and its “control” inputs. This is to start discussions from scratch. What is clock input above? I need a wide understanding of it and its connections with other concepts. Step by step, however. ..... slow down - this is getting way too complex. First things first - do you know what a not gate is? PhilArticle: 141833
On Jul 10, 10:00=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > a...@nishioka.com <a...@nishioka.com> wrote: > > re-reading gabor's response, i believe he is right. =A0you have to use > > all keepers or all pullups. =A0since the default for coolrunner2 is > > keeper (also called bus-hold), pullups in ucf are ignored and a > > warning given (did you ignore the warnings?). > > If I understand the original post, the LED goes from the output > to Vcc, not to ground. =A0(Hopefully with a resistor.) =A0In that > case, a pullup would not turn the LED on. =A0The keeper may or may > not have enough pull to keep an LED on. =A0 the problem is on the input switch side not on the output led side. since coolrunner2 defaults to keeper, he isn't getting a pullup on the momentary switch, but a keeper instead. so it powers up high, then he switches it low and it stays low. and due to coolrunner2 hardware, in order to get any pullups at all, he needs to turn off *all* keepers. the keeper (or pullup) on the led side is doing nothing (it is too weak) and is actually disabled by the software (one of the warnings from ise).Article: 141834
Hi, I have a question about DSP's data width. Why do both Xilinx and Altera DPS use 18*18? Is it determined by hardware algorithms in order to save time or by meeting most DSP data real needs? or any other reasonning? WengArticle: 141835
On Jul 11, 6:26=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > I have a question about DSP's data width. > > Why do both Xilinx and Altera DPS use 18*18? > > Is it determined by hardware algorithms in order to save time or by > meeting most DSP data real needs? or any other reasonning? > > Weng well also Lattice uses 9 , 18, 36 multiplier widths :) see also the RAM block bit widths scale 9 18 36 so the multiplier line up nicely, they are often connected also the ram fifo so the i think in xilinx there is even direct connections mult-bram, at least they are colocated close by hm.. i would say it would have been stupid to have 9 bit rams and 8 bit multipliers i guess there are other more valid reasons as well AnttiArticle: 141836
Alan, Thank you for the heads up on the properties under the fit category. I thought that if I set the pullups in the UCF it would be handled. I on occasion look through the warnings when all else fails, I will try and be a bit more diligent in what ISE is warning. The leds now follow the switch on and off momentarily. Sincerely, Cy DrollingerArticle: 141837
On Jul 9, 3:28=A0am, "a...@nishioka.com" <a...@nishioka.com> wrote: > On Jul 8, 1:54=A0am, cow <cowsgomoosodo...@gmail.com> wrote: > > > Hi everyone. > > > I'm trying to learn more about how configuration of an FPGA works. I > > have been looking at data sheets of integrated boards such as Opal > > Kelly, but I wasn't able to get much information. My question is: In > > boards where a bitstream is sent every time after power-up, where is > > the configuration bitstream stored? > > where ever there is non-volatile storage. > > > Is PROM or Flash required for storing it? > > usually, yes. =A0some fpga's have built in flash. > > > Is a CPLD or something similar needed to manage the > > configuration of the FPGA? > > usually no. =A0you can buy eeproms that are designed to output > bitstreams to fpgas. =A0newer fpgas will work with some generic eeproms. > > > If the configuration is not done by JTAG > > but by sending the bitstream through USB or PCIe, how is the bitstream > > recognized as a bitstream? > > xilinx uses special codes to align and recognize bitstreams. =A0xilinx > also uses crc's to verify accuracy. > but anything you send on the configuration pins is assumed to be > bitstream. How is the eeprom programmed? Is something needed to manage the loading of the bitstream from the USB/PCIe to the eeprom? Do you know any fpga that supports generic eeproms? I read the article mentioned by nobody, the board PROM and a CLPD to coordinate the download between USB and FPGA, which looks like the old method.Article: 141838
On Jul 11, 9:08=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jul 11, 6:26=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > Hi, > > I have a question about DSP's data width. > > > Why do both Xilinx and Altera DPS use 18*18? > > > Is it determined by hardware algorithms in order to save time or by > > meeting most DSP data real needs? or any other reasonning? > > > Weng > > well also Lattice uses 9 , 18, 36 multiplier widths :) > > see also the RAM block bit widths scale 9 18 36 > > so the multiplier line up nicely, they are often connected also the > ram fifo so the > i think in xilinx there is even direct connections mult-bram, at least > they are colocated close by > > hm.. i would say it would have been stupid to have 9 bit rams and 8 > bit multipliers > i guess there are other more valid reasons as well > > Antti Hi Antti, 1. It had first have Block RAM before DPS takes its current data width. Why 8+1 width for RAM is 8-bit is a byte, and another bit is used for check bytes, 1 bit for 1 byte. It is for memory checking usage. 2. Block RAM size is one of many reasons why DPS takes 18*18 width. 3. But there is more fundamental reason I believe on which DPS bases its 18*18 width. WengArticle: 141839
On Jul 12, 5:59=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jul 11, 9:08=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Jul 11, 6:26=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > Hi, > > > I have a question about DSP's data width. > > > > Why do both Xilinx and Altera DPS use 18*18? > > > > Is it determined by hardware algorithms in order to save time or by > > > meeting most DSP data real needs? or any other reasonning? > > > > Weng > > > well also Lattice uses 9 , 18, 36 multiplier widths :) > > > see also the RAM block bit widths scale 9 18 36 > > > so the multiplier line up nicely, they are often connected also the > > ram fifo so the > > i think in xilinx there is even direct connections mult-bram, at least > > they are colocated close by > > > hm.. i would say it would have been stupid to have 9 bit rams and 8 > > bit multipliers > > i guess there are other more valid reasons as well > > > Antti > > Hi Antti, > 1. It had first have Block RAM before DPS takes its current data > width. Why 8+1 width for RAM is 8-bit is a byte, and another bit is > used for check bytes, 1 bit for 1 byte. > It is for memory checking usage. > 2. Block RAM size is one of many reasons why DPS takes 18*18 width. > 3. But there is more fundamental reason I believe on which DPS bases > its 18*18 width. > > Weng yes I think the reason is that they all (xilinx altera lattice..) wait and hope that i write some really cool soft processor that uses 9 bit data path well, hm maybe its too late already ERIC5 uses 110 Altera LEs and has full support of a C compiler and it has 9 bit data path AnttiArticle: 141840
On Jul 11, 10:30=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jul 12, 5:59=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Jul 11, 9:08=A0am, "Antti.Luk...@googlemail.com" > > > <Antti.Luk...@googlemail.com> wrote: > > > On Jul 11, 6:26=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > Hi, > > > > I have a question about DSP's data width. > > > > > Why do both Xilinx and Altera DPS use 18*18? > > > > > Is it determined by hardware algorithms in order to save time or by > > > > meeting most DSP data real needs? or any other reasonning? > > > > > Weng > > > > well also Lattice uses 9 , 18, 36 multiplier widths :) > > > > see also the RAM block bit widths scale 9 18 36 > > > > so the multiplier line up nicely, they are often connected also the > > > ram fifo so the > > > i think in xilinx there is even direct connections mult-bram, at leas= t > > > they are colocated close by > > > > hm.. i would say it would have been stupid to have 9 bit rams and 8 > > > bit multipliers > > > i guess there are other more valid reasons as well > > > > Antti > > > Hi Antti, > > 1. It had first have Block RAM before DPS takes its current data > > width. Why 8+1 width for RAM is 8-bit is a byte, and another bit is > > used for check bytes, 1 bit for 1 byte. > > It is for memory checking usage. > > 2. Block RAM size is one of many reasons why DPS takes 18*18 width. > > 3. But there is more fundamental reason I believe on which DPS bases > > its 18*18 width. > > > Weng > > yes > > I think the reason is that they all (xilinx altera lattice..) wait and > hope > that i write some really cool soft processor that uses 9 bit data path > > well, hm maybe its too late already ERIC5 uses 110 Altera LEs and > has full support of a C compiler and it has 9 bit data path > > Antti- Hide quoted text - > > - Show quoted text - Hi Antti, Maybe ADC, Analog to Digital Convertor, has the largest accuracy at 18- bits that is the decisive factor to let DSPs have 18*18 width. It means DSPs embedded in FPGAs are only designed for data flow converted from ADC. WengArticle: 141841
On 11 Jul., 14:14, dsa fsag <johnka...@gmail.com> wrote: > A =A0flip-flop is a device that stores either a 0 or 1. The =A0state of a [..] > This is to start discussions from scratch. What is clock input above? > I need a wide understanding of it and its connections with other > concepts. Step by step, however. Google about edge triggered vs level triggered (RS, JK, D, T) flip- flop.Article: 141842
Hi! thnx alot for your kind help and assistance. i'll try these and let u know if i find some problem. i'll try to use this and fix this, if i find problem then i'll discuss with you. Regards Symon wrote: > "Rai" <raifasih@gmail.com> wrote in message > news:8f8f48c1-e359-4096-a518-94aaa4b3bb29@m11g2000yqh.googlegroups.com... > > Ok i'll let you know my problem...I have two inputs with 8-bit width. > > These two inputs are the 8-bit image from camera. I need to correlate > > these two inputs by cross correlation and therefore i need to multiply > > these two inputs. my vector having 10,000 8-bit data. therefore i need > > 10,000 multiplication using 8-bit multiplier. My clock frequency is > > 66MHz. > > > > Hi Rai, > Have a read of this :- > http://andraka.com/distribu.htm > > You could use your FPGA's clock multipliers, i.e. DCMs or PLLs, to make a > faster clock, 4*66 = 264MHz for instance. Then use distributed arithmetic to > do your calculations. With a modern FPGA you can probably clock even faster, > but see how you go. > HTH., Syms. > > p.s. This may be of interest also. > http://andraka.com/cordic.htmArticle: 141843
"muse_ee" <brian.bubnash@jhuapl.edu> writes: > Hi, I'm trying to learn how to use the DCM's frequency synthesis capability > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock. I > used Xilinx Architecture wizard to generate the code and the clock > multiplication works correctly in timing simulation. When I get to the > bench to test however, I don't get a multiplied clock output - the line is > 0. I have a couple debug signals that tell me the following: > > -75MHz, post BUFG looks fine (I see output from the FPGA) > -DCM Lock is 0 > -Status(2 downto 0) are all 0. One thought - what does your reset to the DCM look like? It has a minimum pulse length documented in the datasheet for the part. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 141844
On Jul 12, 10:05=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jul 11, 10:30=A0pm, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Jul 12, 5:59=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > On Jul 11, 9:08=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > > > On Jul 11, 6:26=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > Hi, > > > > > I have a question about DSP's data width. > > > > > > Why do both Xilinx and Altera DPS use 18*18? > > > > > > Is it determined by hardware algorithms in order to save time or = by > > > > > meeting most DSP data real needs? or any other reasonning? > > > > > > Weng > > > > > well also Lattice uses 9 , 18, 36 multiplier widths :) > > > > > see also the RAM block bit widths scale 9 18 36 > > > > > so the multiplier line up nicely, they are often connected also the > > > > ram fifo so the > > > > i think in xilinx there is even direct connections mult-bram, at le= ast > > > > they are colocated close by > > > > > hm.. i would say it would have been stupid to have 9 bit rams and 8 > > > > bit multipliers > > > > i guess there are other more valid reasons as well > > > > > Antti > > > > Hi Antti, > > > 1. It had first have Block RAM before DPS takes its current data > > > width. Why 8+1 width for RAM is 8-bit is a byte, and another bit is > > > used for check bytes, 1 bit for 1 byte. > > > It is for memory checking usage. > > > 2. Block RAM size is one of many reasons why DPS takes 18*18 width. > > > 3. But there is more fundamental reason I believe on which DPS bases > > > its 18*18 width. > > > > Weng > > > yes > > > I think the reason is that they all (xilinx altera lattice..) wait and > > hope > > that i write some really cool soft processor that uses 9 bit data path > > > well, hm maybe its too late already ERIC5 uses 110 Altera LEs and > > has full support of a C compiler and it has 9 bit data path > > > Antti- Hide quoted text - > > > - Show quoted text - > > Hi Antti, > Maybe ADC, Analog to Digital Convertor, has the largest accuracy at 18- > bits that is the decisive factor to let DSPs have 18*18 width. > > It means DSPs embedded in FPGAs are only designed for data flow > converted from ADC. > > Weng Another possibility is that the 9x9 minimum width allows you to do 8x8 either signed or unsigned using a signed multiplier?Article: 141845
On Jul 13, 3:45=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > "muse_ee" <brian.bubn...@jhuapl.edu> writes: > > Hi, I'm trying to learn how to use the DCM's frequency synthesis capabi= lity > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock= . I > > used Xilinx Architecture wizard to generate the code and the clock > > multiplication works correctly in timing simulation. When I get to the > > bench to test however, I don't get a multiplied clock output - the line= is > > 0. I have a couple debug signals that tell me the following: > > > -75MHz, post BUFG looks fine (I see output from the FPGA) > > -DCM Lock is 0 > > -Status(2 downto 0) are all 0. > > One thought - what does your reset to the DCM look like? =A0It has a > minimum pulse length documented in the datasheet for the part. > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html Thanks for the reply - I saw the minimum pulse length requirements and so I put this reset pulse extender in. It ensures that any pulse coming from the reset button lasts for at least 256 clock cycles (overkill I know but this was put in well past the point of desperation). I have tried pressing the reset button several minutes after powering the FPGA to see if the clock was slow to stabilize for some reason, but nothing I do seems to make the output from the DCM vary from '0'. Below is my reset manager code: rst_manager : process(clk,rstn) variable cnt : std_logic_vector(7 downto 0); variable r : std_logic; constant ones : std_logic_vector(7 downto 0) :=3D (others =3D> '1'); begin r :=3D not rstn; if r =3D '1' then cnt :=3D (others =3D> '0'); rst <=3D '1'; elsif rising_edge(clk) then if cnt =3D ones then rst <=3D '0'; else rst <=3D '1'; cnt :=3D cnt + '1'; end if; end if; end process;Article: 141846
On Jul 13, 10:05=A0am, muse_ee <brian.bubn...@gmail.com> wrote: > On Jul 13, 3:45=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > > "muse_ee" <brian.bubn...@jhuapl.edu> writes: > > > Hi, I'm trying to learn how to use the DCM's frequency synthesis capa= bility > > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clo= ck. I > > > used Xilinx Architecture wizard to generate the code and the clock > > > multiplication works correctly in timing simulation. When I get to th= e > > > bench to test however, I don't get a multiplied clock output - the li= ne is > > > 0. I have a couple debug signals that tell me the following: > > > > -75MHz, post BUFG looks fine (I see output from the FPGA) > > > -DCM Lock is 0 > > > -Status(2 downto 0) are all 0. > > > One thought - what does your reset to the DCM look like? =A0It has a > > minimum pulse length documented in the datasheet for the part. > > > Cheers, > > Martin > > > -- > > martin.j.thomp...@trw.com > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/= /www.conekt.net/electronics.html > > Thanks for the reply - I saw the minimum pulse length requirements and > so I put this reset pulse extender in. It ensures that any pulse > coming from the reset button lasts for at least 256 clock cycles > (overkill I know but this was put in well past the point of > desperation). I have tried pressing the reset button several minutes > after powering the FPGA to see if the clock was slow to stabilize for > some reason, but nothing I do seems to make the output from the DCM > vary from '0'. Below is my reset manager code: > > =A0 =A0 =A0 =A0 rst_manager : process(clk,rstn) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable cnt : std_logic_vector(7 downto = 0); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable r : std_logic; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 constant ones : std_logic_vector(7 downto= 0) :=3D (others =3D> '1'); > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D not rstn; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if r =3D '1' then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt :=3D (others =3D> '0'= ); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if cnt =3D ones then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D = '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D = '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt :=3D = cnt + '1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 end process; What is your clock source? Are you sure it meets the input jitter requirements and frequency range requirements?Article: 141847
On Jul 13, 10:26=A0am, gabor <ga...@alacron.com> wrote: > On Jul 13, 10:05=A0am, muse_ee <brian.bubn...@gmail.com> wrote: > > > > > On Jul 13, 3:45=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote= : > > > > "muse_ee" <brian.bubn...@jhuapl.edu> writes: > > > > Hi, I'm trying to learn how to use the DCM's frequency synthesis ca= pability > > > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz c= lock. I > > > > used Xilinx Architecture wizard to generate the code and the clock > > > > multiplication works correctly in timing simulation. When I get to = the > > > > bench to test however, I don't get a multiplied clock output - the = line is > > > > 0. I have a couple debug signals that tell me the following: > > > > > -75MHz, post BUFG looks fine (I see output from the FPGA) > > > > -DCM Lock is 0 > > > > -Status(2 downto 0) are all 0. > > > > One thought - what does your reset to the DCM look like? =A0It has a > > > minimum pulse length documented in the datasheet for the part. > > > > Cheers, > > > Martin > > > > -- > > > martin.j.thomp...@trw.com > > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp= ://www.conekt.net/electronics.html > > > Thanks for the reply - I saw the minimum pulse length requirements and > > so I put this reset pulse extender in. It ensures that any pulse > > coming from the reset button lasts for at least 256 clock cycles > > (overkill I know but this was put in well past the point of > > desperation). I have tried pressing the reset button several minutes > > after powering the FPGA to see if the clock was slow to stabilize for > > some reason, but nothing I do seems to make the output from the DCM > > vary from '0'. Below is my reset manager code: > > > =A0 =A0 =A0 =A0 rst_manager : process(clk,rstn) > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable cnt : std_logic_vector(7 downt= o 0); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable r : std_logic; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 constant ones : std_logic_vector(7 down= to 0) :=3D (others =3D> '1'); > > =A0 =A0 =A0 =A0 begin > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D not rstn; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if r =3D '1' then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt :=3D (others =3D> '= 0'); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if cnt =3D ones then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <= =3D '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <= =3D '1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt := =3D cnt + '1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 end process; > > What is your clock source? =A0Are you sure it meets the input > jitter requirements and frequency range requirements? Thanks for the suggestion. I checked and clock source is a 75MHz Pletronics clock oscillator, SM7745DW (jitter under 3pS RMS according to datasheet). I believe that both parameters are within their acceptable ranges.Article: 141848
On 10 Jul., 22:23, Peter Alfke <pe...@xilinx.com> wrote: > On Jul 9, 2:14=A0pm, fl <rxjw...@gmail.com> wrote: > > > Hi, > > Block ram in FPGA can implement complex FSM, see the cited clue below. > > I was the author of the original =93clue=94, years ago, but unfortunately > I cannot offer a synthesis tool. Well, you can use a VHDL simulator. The rom takes a state and an input vector and generates a next state and an output. Copy the code from the case statement to a new vhdl file, write some lines to map the inputs/statebits to address lines and the outputs to data bits and write a wrappper state testbench to simulate all combinations. You can write the results to a file in the right format for the INIT attributs. Should not take much more than an hour for an existing state machine. Kolja Sulimma www.cronologic.deArticle: 141849
Hi, I am using a spartan 3an device to run a tftp server. Once I transfer a file using tftp put, I don't know how to read the file back or determine where the file was saved to. I am not sure how to use mfs_file_open. Could someone help? Thanks hv
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