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Xesium <amirhossein.gholamipour@gmail.com> wrote: < I'm wondering, using Xilinx CLB architecture, and hypothetically < assuming that we have direct control over the configuration bits and < detailed knowledge about the configuration, how can one minimally < design an adder which adds 15, 1-bit signals. < The result is 4 bits wide (it can be at most 1111 (=15)), so is it < possible to just use 4 LUTs (2 slices) to implement such a circuit? Traditionally (that is, before FPGAs) it was done with carry save adders. I believe that still works will in FPGA logic. A carry save adder has three inputs and two outputs, sum and carry. You start with five CSA, three bits to each. The output is five sums and five carries. Next add them using four CSAs. Using 4 input LUTs instead of three input CSA might reduce the logic slightly. The ones bit is the XOR of the 15 inputs, which can be done with five LUT4's. < I wrote a very basic VHDL code and after synthesizing it using ISE, < the result was 12 slices and 18 LUTs. Last I knew, the tools did pretty well. -- glenArticle: 141876
gabor wrote: > If all of the logic consists of driving the output from > the input (pin 71) then the problem is with your pullup. > Coolrunner 2 has a global pull type for the part which can > be on or off for individual pins. It cannot be different > (other than on or off) for different pins. Umm, maybe, the docs are just a bit unclear on this. MY READING of it, however, seems to be that the UNUSED "inputs" can all be assigned to keeper, weak pullup, or ground. Specifically, they use the term "unused inputs" several times. I take this to mean "unused PADS", but that could be a wrong interpretation. I think that IN USE input pads have more flexibility, and you can select keeper, pull up, Schmitt trigger, or comparator to ref voltage on a pin-for-pin basis in the constraint file. I will be getting my first Coolrunner 2 board back in a couple days, and it has some config jumpers where I need the pullup, so i will be finding out whether I am right or not. JonArticle: 141877
glen herrmannsfeldt wrote: > alan@nishioka.com <alan@nishioka.com> wrote: > (snip) >> re-reading gabor's response, i believe he is right. you have to use >> all keepers or all pullups. since the default for coolrunner2 is >> keeper (also called bus-hold), pullups in ucf are ignored and a >> warning given (did you ignore the warnings?). > > If I understand the original post, the LED goes from the output > to Vcc, not to ground. (Hopefully with a resistor.) In that > case, a pullup would not turn the LED on. The keeper may or may > not have enough pull to keep an LED on. The pullup is nominally 100K Ohms, that would not normally light any LED. JonArticle: 141878
On Jul 14, 3:08=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > I think that IN USE input pads have > more flexibility, and you can select keeper, pull up, Schmitt trigger, > or comparator to ref voltage on a pin-for-pin basis in the constraint > file. =A0I will be getting my first Coolrunner 2 board back in a couple > days, and it has some config jumpers where I need the pullup, so i will > be finding out whether I am right or not. http://www.xilinx.com/support/documentation/user_guides/ug445.pdf page 9 For CoolRunner-II devices, it is possible to have a combination of multiple termination modes for used and unused I/Os. However, not all combinations are possible. Below are the permitted combinations: Table 1: Input Termination Schemes Possible Input Termination Schemes All Pull-up All Bus-hold Combination of Pull-up and Float Combination of Bus-hold and Float All Float Table 2: Unused I/O Termination Schemes Unused I/O Termination Schemes All Pulled-up (not possible if Bus-hold is selected for input termination) All Bus-hold (not possible if Pull-up is selected for input termination) All Configurable Ground All FloatArticle: 141879
On Jul 14, 6:41=A0pm, "a...@nishioka.com" <a...@nishioka.com> wrote: > On Jul 14, 3:08=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > > > I think that IN USE input pads have > > more flexibility, and you can select keeper, pull up, Schmitt trigger, > > or comparator to ref voltage on a pin-for-pin basis in the constraint > > file. =A0I will be getting my first Coolrunner 2 board back in a couple > > days, and it has some config jumpers where I need the pullup, so i will > > be finding out whether I am right or not. > > http://www.xilinx.com/support/documentation/user_guides/ug445.pdf > page 9 > For CoolRunner-II devices, it is possible to have a combination of > multiple termination > modes for used and unused I/Os. However, not all combinations are > possible. Below are > the permitted combinations: > > Table 1: Input Termination Schemes > Possible Input Termination Schemes > All Pull-up > All Bus-hold > Combination of Pull-up and Float > Combination of Bus-hold and Float > All Float > > Table 2: Unused I/O Termination Schemes > Unused I/O Termination Schemes > All Pulled-up (not possible if Bus-hold is selected > for input termination) > All Bus-hold (not possible if Pull-up is selected for > input termination) > All Configurable Ground > All Float Or to belabor the point, no combination containing both keeper and pullup. "Configurable ground" is really a low driven output, the keeper / pullup circuit has nothing to do with it. Regards, GaborArticle: 141880
On Tue, 14 Jul 2009 20:25:19 +0100, Jonathan Bromley wrote: >>design an adder which adds 15, 1-bit signals. >I know how to do it in 9 LUTs. Whoops, I can't count. That should be 3+2+2+1+1+1+1 = 11. Don't know where I got 9 from, sorry. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141881
hi Good Day! I hope you all are fine. Actually i want to take some technical input. I want to build 10,000 floating point multiplier in FPGA fabric. So > Kindly suggest me Is it possible ? > How we can implement ? (my suggestion is MicroBlaze soft processor) > Which Chip_Set is best for this purpose ? Thanks in Advance ........... Best RegardsArticle: 141882
hi Good Day! I hope you all are fine. Actually i want to take some technical input. I want to build 10,000 floating point multiplier in FPGA fabric. So > Kindly suggest me Is it possible ? > How we can implement ? (my suggestion is MicroBlaze soft processor) > Which Chip_Set is best for this purpose ? Thanks in Advance ........... Best RegardsArticle: 141883
Nauman Mir <mir6@hotmail.com> wrote: < I want to build 10,000 floating point multiplier in FPGA fabric. What are you actually trying to do with those multipliers? Also, you don't say the width. You can probably do 10,000 1 bit by 1 bit multipliers, maybe 2 bit by 2 bit in a reasonable sized FPGA. If you use pipelined multipliers, you can get many products per second out of each one. You don't give any speed requirement at all. -- glenArticle: 141884
On Jul 14, 10:46=A0pm, AndreasWallner <Andreas.Wallner.et...@fh- joanneum.at> wrote: > Hi, > > I have a Problem getting the System ACE Controller to work. > I try it on a Spartan 3A DSP 1800 Board, to which I connected a > SystemACE Module from AVNet. > > If I format the CF Card completly, and do not create any partitions > (the drive then only contains the FAT16). > > If I try to create two partitions (with linux fdisk, one 64MB > Partition, and the second spanning the remaining card), format the > first one to FAT16 and copy the exact same files to the card the > System ACE board only displays an error and does not load the design. > > Are there any special points to take into consideration? > > Regards, > Andreas Hi Andreas, look on http://www.xilinx.com/products/boards/ml403/reference_designs.htm near the end of the page there is a image for the CF card with a DOS and Linux partition. (CF Card Image (DOS and Linux Partition)) You can download it and view it with a Disk Editor or Uedit in binary mode. Maybe you find the diffs to the Linux fdisk tool. Have Fun FlorianArticle: 141885
Dear all, I have some doubts. Please clarify, 1. Is parallel processing possible in DSP processors and other high level languages like C etc., If so, How?? 2. I am doing image processing on FPGA. I have to write a bitmap file from FPGA output. How can it be done?? 3. How a image can be processed parallely on FPGA. Waiting for replies.. Thanks prashArticle: 141886
On Thu, 09 Jul 2009 14:14:31 -0700, fl wrote: > Hi, > Block ram in FPGA can implement complex FSM, see the cited clue below. > My question here is how to convert the VHDL FSM to the block ram > contents? Is there a tool to combine the logic bits to the ram content? > Thanks. > > > > > > > > > > > > > Use the 4K bit RAM, properly initialized during configuration. So it > really is a > ROM, since you never write into it. > Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input and use > the > remaining 4 inputs as control. > You now have a 32-state FSM with 4 condition inputs, and 3 extra > arbitrarily decoded > outputs, beyond the 5 encoded outputs. You can define everything, like > recovery from > illegal states, etc. No holes. > > > In Virtex-II the ROM is bigger, 18K bits. So you can have a 128-state > FSM with 4 control inputs, with the ROMconfigured 2K x > 9. > Or 64 states with 5 control inputs. Before I forgot, anyone contemplating using a block ram as a rom should read this Xilinx Answer Record which describes a way that the rom contents can be corrupted: http://www.xilinx.com/support/answers/21870.htm Regards, AllanArticle: 141887
I cant believe that Altera dont have a core generator type program. It seems silly to be to mess around converting to a hex file when these programs will init the coef and create a rom for you. JonArticle: 141888
"PrAsHaNtH@IIT" <prashaenator@gmail.com> wrote > > 2. I am doing image processing on FPGA. I have to write a bitmap file > from FPGA output. How can it be done?? > Carefully open up your FPGA. Take a picture of what's inside with a digital camera. Connect the camera with a USB cable to your PC. Copy the picture file to your PC. Convert it to bitmap. Job done. /MikhailArticle: 141889
On Wed, 15 Jul 2009 10:43:28 -0400, "MM" <mbmsv@yahoo.com> wrote: >"PrAsHaNtH@IIT" <prashaenator@gmail.com> wrote >> >> 2. I am doing image processing on FPGA. I have to write a bitmap file >> from FPGA output. How can it be done?? >> > >Carefully open up your FPGA. Take a picture of what's inside with a digital >camera. Connect the camera with a USB cable to your PC. Copy the picture >file to your PC. Convert it to bitmap. Job done. That's just a little unfair, isn't it? But, Prashanth, you have rather brought that on yourself by being so vague. Do you want to create a bitmap file from your simulation results, so that you can visualize the results of an image processing operation in simulation? Or do you hope to get the FPGA to write a bitmap file somehow? If the latter, how do you intend to get the data out of the FPGA and into a PC where the file can be stored - USB? serial? ethernet? Your description is far too "high level" to be useful - it sounds as though you're some kind of manager :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141890
"Allan Herriman" <allanherriman@hotmail.com> wrote in message news:026dd4b6$0$20652$c3e8da3@news.astraweb.com... > On Thu, 09 Jul 2009 14:14:31 -0700, fl wrote: > >> Hi, >> Block ram in FPGA can implement complex FSM, see the cited clue below. >> My question here is how to convert the VHDL FSM to the block ram >> contents? Is there a tool to combine the logic bits to the ram content? >> Thanks. >> >> >> >> >> >> >> >> >> >> >> >> >> Use the 4K bit RAM, properly initialized during configuration. So it >> really is a >> ROM, since you never write into it. >> Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input and use >> the >> remaining 4 inputs as control. >> You now have a 32-state FSM with 4 condition inputs, and 3 extra >> arbitrarily decoded >> outputs, beyond the 5 encoded outputs. You can define everything, like >> recovery from >> illegal states, etc. No holes. >> >> >> In Virtex-II the ROM is bigger, 18K bits. So you can have a 128-state >> FSM with 4 control inputs, with the ROMconfigured 2K x >> 9. >> Or 64 states with 5 control inputs. > > > Before I forgot, anyone contemplating using a block ram as a rom should > read this Xilinx Answer Record which describes a way that the rom > contents can be corrupted: > > http://www.xilinx.com/support/answers/21870.htm > > Regards, > Allan Wow. That's one of those things that could be impossible to troubleshoot if one is not aware of that requirement. Thanks. Bob -- == All google group posts are automatically deleted due to spam ==Article: 141891
On Jul 15, 7:11=A0am, Allan Herriman <allanherri...@hotmail.com> wrote: > > Before I forgot, anyone contemplating using a block ram as a rom should > read this Xilinx Answer Record which describes a way that the rom > contents can be corrupted: > > http://www.xilinx.com/support/answers/21870.htm > > Regards, > Allan Thank you, Allan, for pointing this out (it is also documented in the User Guide). The problem is caused by metastability in the address register, fouling up the address decoder. The easy cure is to disable the clock whenever the address inputs are asynchronous. This should not be of concern to any FSM design, since its control inputs should be pre-synchronized under all circumstances. Peter AlfkeArticle: 141892
>I cant believe that Altera dont have a core generator type program. It >seems silly to be to mess around converting to a hex file when these >programs will init the coef and create a rom for you. > >Jon > I've just found another way to initialize a ROM on Quartus, that's by using the mif file, the format for mif file is much more simpler than hex file. Thank you all, TPArticle: 141893
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote > > it sounds as though you're some kind of manager :-) More like a student who doesn't have a clue... /MikhailArticle: 141894
On Jul 14, 2:31=A0pm, Amir <amirhossein.gholamip...@gmail.com> wrote: > Rick and Peter, > Thanks so much for your replies. They are extremely informative > indeed. > This is part of my PhD research to optimize some filtering circuits > for the architecture of FPGAs. I'm in particular working on Xilinx > Virtex devices. There is this binary adder tree that I design which in > parallel adds some inputs. However since the frequency becomes very > low, I was thinking to insert some registers in between and make it a > pipeline. So I was concerned about the area. From your explanation and > looking at the detailed architecture of a CLB (Xilinx ds031, Page 21) > I realized that the FF can be used to store not just the output of the > corresponding LUT but also some other inputs to the slice. So in fact > if I use a LUT, it costs me nothing to also use the FF next to it. > However that FF can be used to store some other signals generated from > other LUTs. The problem with using a FF to store an output from another LUT is routing. Why wouldn't the FF next the the other LUT be used? Regardless, you have little control over any of this unless you instantiate the logic which is very tedious. When using inference, the tool will pick what it thinks is the best placement and route that as optimally as it can. All you can do is control the logic that is generated by how you write your code. To this end, I write my code in small modules so that I have a clear idea of what I expect and tweek the code until I get that. Using small modules makes it much easier to understand the schematic that the tool gives me. > So putting this next to what Rick said which says most of the designs > are LUT limited than FF limited, then I guess depending on the design, > it might cost me nothing to add registers to my design. Because my > design is already using the LUTs and assuming enough abandoned wires > (big assumption indeed) using the FFs in those slices I can also > implement my registers. > On the other hand it also might cost me some more slices to implement > the additional pipeline registers if there is not enough wire or not > enough free FFs in the slices where LUTs have already been used. Or > even simply because the tool couldn't handle the available resources. In Vertex parts there is 1 FF for each LUT so the chances of FF limiting even a pipelined design are slim. Attaching FFs to the associated LUT uses no wires but rather use connections internal to the CLB. > Of course I understand what Peter is saying about the low level > handling of the tools and architecture. I understand that I don't have > much of flexibility at so low a level but I'm more concerned about the > possibilities based on the facts than really the ability to exactly do > it. > > Did I get your points correctly? Yes, I think so. If you are really concerned with efficiency, I find the coding of small modules to be the easiest way to get optimized designs. It also allows more reuse than with larger modules... sometimes. I find reuse to be a difficult thing to use in practice. It can also be expensive to design every module for reuse when only a fraction of them actually get reused. RickArticle: 141895
Is there any way how to make Xilinx FPGA Editor (and other old Wind/U based applications) running in Fedora 11, x86_64? In RHEL, CentOS, and older versions of Fedora (all x86_64) it is sufficient to set the $DISPLAY environment variable to :0 and to follow this http://www.xilinx.com/support/answers/22022.htm answer record. Unfortunately this does not work in F11/x86_64. I get the same error messages as described in the answer record but the answer itself does not help. According to "ldd -v ..../fpga_editor" I am not missing any required library. Thanks for your help, JanArticle: 141896
On Jul 15, 9:10=A0am, "BobW" <nimby_GIMME_SOME_S...@roadrunner.com> wrote: > "Allan Herriman" <allanherri...@hotmail.com> wrote in message > > news:026dd4b6$0$20652$c3e8da3@news.astraweb.com... > > > > > On Thu, 09 Jul 2009 14:14:31 -0700, fl wrote: > > >> Hi, > >> Block ram in FPGA can implement complex FSM, see the cited clue below. > >> My question here is how to convert the VHDL FSM to the block ram > >> contents? Is there a tool to combine the logic bits to the ram content= ? > >> Thanks. > > >> Use the 4K bit RAM, properly initialized during configuration. So it > >> really is a > >> ROM, since you never write into it. > >> Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input and u= se > >> the > >> remaining 4 inputs as control. > >> You now have a 32-state FSM with 4 condition inputs, and 3 extra > >> arbitrarily decoded > >> outputs, beyond the 5 encoded outputs. You can define everything, like > >> recovery from > >> illegal states, etc. No holes. > > >> In Virtex-II the ROM is bigger, 18K bits. So you can have a 128-state > >> FSM with 4 control inputs, with the ROMconfigured 2K x > >> 9. > >> Or 64 states with 5 control inputs. > > > Before I forgot, anyone contemplating using a block ram as a rom should > > read this Xilinx Answer Record which describes a way that the rom > > contents can be corrupted: > > >http://www.xilinx.com/support/answers/21870.htm > > > Regards, > > Allan > > Wow. That's one of those things that could be impossible to troubleshoot = if > one is not aware of that requirement. > Unbeknownst to anybody, including us at Xilinx, this situation has existed for many years in all generations of BlockRAMs. Then one day we had a customer who addressed the BRAM asynchronously to the clock, (obviously not while WE was active). The customer told us that they - most of the time- just ignored the read data output, but would stall the address change whenever they really cared about the read data. A very peculiar application that should work, but it resulted in occasional unpredictable data corruption. A typical case of metastability. That lead to a deeper investigation, and a complete understanding, creating the cited caveats. There is no "cure", but the work-around is easy: Just disable the clock when the address set-up time might be violated. BTW, the problem is so fundamental that Altera had to copy the same warning into their User Guide. Peter Alfke (Mr Metastable at Xilinx)Article: 141897
On Jul 16, 1:01=A0am, Peter Alfke <pe...@xilinx.com> wrote: > On Jul 15, 9:10=A0am, "BobW" <nimby_GIMME_SOME_S...@roadrunner.com> > wrote: > > > "Allan Herriman" <allanherri...@hotmail.com> wrote in message > > >news:026dd4b6$0$20652$c3e8da3@news.astraweb.com... > > > > On Thu, 09 Jul 2009 14:14:31 -0700, fl wrote: > > > >> Hi, > > >> Block ram in FPGA can implement complex FSM, see the cited clue belo= w. > > >> My question here is how to convert the VHDL FSM to the block ram > > >> contents? Is there a tool to combine the logic bits to the ram conte= nt? > > >> Thanks. > > > >> Use the 4K bit RAM, properly initialized during configuration. So it > > >> really is a > > >> ROM, since you never write into it. > > >> Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input and= use > > >> the > > >> remaining 4 inputs as control. > > >> You now have a 32-state FSM with 4 condition inputs, and 3 extra > > >> arbitrarily decoded > > >> outputs, beyond the 5 encoded outputs. You can define everything, li= ke > > >> recovery from > > >> illegal states, etc. No holes. > > > >> In Virtex-II the ROM is bigger, 18K bits. So you can have a 128-stat= e > > >> FSM with 4 control inputs, with the ROMconfigured 2K x > > >> 9. > > >> Or 64 states with 5 control inputs. > > > > Before I forgot, anyone contemplating using a block ram as a rom shou= ld > > > read this Xilinx Answer Record which describes a way that the rom > > > contents can be corrupted: > > > >http://www.xilinx.com/support/answers/21870.htm > > > > Regards, > > > Allan > > > Wow. That's one of those things that could be impossible to troubleshoo= t if > > one is not aware of that requirement. > > Unbeknownst to anybody, including us at Xilinx, this situation has > existed for many years in all generations of BlockRAMs. Then one day > we had a customer who addressed the BRAM asynchronously to the clock, > (obviously not while WE was active). The customer told us that they - > most of the time- just ignored the read data output, but would stall > the address change whenever they really cared about the read data. A > very peculiar application that should work, but it resulted in > occasional unpredictable data corruption. A typical case of > metastability. > That lead to a deeper investigation, and a complete understanding, > creating the cited caveats. > There is no "cure", but the =A0work-around is easy: Just disable the > clock when the address set-up time might be violated. > BTW, the problem is so fundamental that Altera had to copy the same > warning into their User Guide. > Peter Alfke =A0 (Mr Metastable at Xilinx) but the problem doesnt exist in Spartan generation incl S-6 and has been fixed in Virtex-6, I am correct? because the AR only talks V-2 to V-5? AnttiArticle: 141898
On Jul 15, 9:52=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jul 16, 1:01=A0am, Peter Alfke <pe...@xilinx.com> wrote: > > > > > > > On Jul 15, 9:10=A0am, "BobW" <nimby_GIMME_SOME_S...@roadrunner.com> > > wrote: > > > > "Allan Herriman" <allanherri...@hotmail.com> wrote in message > > > >news:026dd4b6$0$20652$c3e8da3@news.astraweb.com... > > > > > On Thu, 09 Jul 2009 14:14:31 -0700, fl wrote: > > > > >> Hi, > > > >> Block ram in FPGA can implement complex FSM, see the cited clue be= low. > > > >> My question here is how to convert the VHDL FSM to the block ram > > > >> contents? Is there a tool to combine the logic bits to the ram con= tent? > > > >> Thanks. > > > > >> Use the 4K bit RAM, properly initialized during configuration. So = it > > > >> really is a > > > >> ROM, since you never write into it. > > > >> Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input a= nd use > > > >> the > > > >> remaining 4 inputs as control. > > > >> You now have a 32-state FSM with 4 condition inputs, and 3 extra > > > >> arbitrarily decoded > > > >> outputs, beyond the 5 encoded outputs. You can define everything, = like > > > >> recovery from > > > >> illegal states, etc. No holes. > > > > >> In Virtex-II the ROM is bigger, 18K bits. So you can have a 128-st= ate > > > >> FSM with 4 control inputs, with the ROMconfigured 2K x > > > >> 9. > > > >> Or 64 states with 5 control inputs. > > > > > Before I forgot, anyone contemplating using a block ram as a rom sh= ould > > > > read this Xilinx Answer Record which describes a way that the rom > > > > contents can be corrupted: > > > > >http://www.xilinx.com/support/answers/21870.htm > > > > > Regards, > > > > Allan > > > > Wow. That's one of those things that could be impossible to troublesh= oot if > > > one is not aware of that requirement. > > > Unbeknownst to anybody, including us at Xilinx, this situation has > > existed for many years in all generations of BlockRAMs. Then one day > > we had a customer who addressed the BRAM asynchronously to the clock, > > (obviously not while WE was active). The customer told us that they - > > most of the time- just ignored the read data output, but would stall > > the address change whenever they really cared about the read data. A > > very peculiar application that should work, but it resulted in > > occasional unpredictable data corruption. A typical case of > > metastability. > > That lead to a deeper investigation, and a complete understanding, > > creating the cited caveats. > > There is no "cure", but the =A0work-around is easy: Just disable the > > clock when the address set-up time might be violated. > > BTW, the problem is so fundamental that Altera had to copy the same > > warning into their User Guide. > > Peter Alfke =A0 (Mr Metastable at Xilinx) > > but the problem doesnt exist in Spartan generation incl S-6 > and has been fixed in Virtex-6, I am correct? > > because the AR only talks V-2 to V-5? > > Antti The AR could not talk about future devices. All BlockRAMs including the newest -6 ones, have this problem, but it is so easy to avoid, just do not use the address input register as a synchronizer. Just disable the clock. And do not jump over to Altera, for they have the same problem or feature. The problem is easily avoided, once you know about it. It took more than 5 years to be found out by a weird customer design. I felt bad about this, until I had published the warnings in the User Guides. Peter AlfkeArticle: 141899
On Jul 16, 8:18=A0am, Peter Alfke <al...@sbcglobal.net> wrote: > On Jul 15, 9:52=A0pm, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Jul 16, 1:01=A0am, Peter Alfke <pe...@xilinx.com> wrote: > > > > On Jul 15, 9:10=A0am, "BobW" <nimby_GIMME_SOME_S...@roadrunner.com> > > > wrote: > > > > > "Allan Herriman" <allanherri...@hotmail.com> wrote in message > > > > >news:026dd4b6$0$20652$c3e8da3@news.astraweb.com... > > > > > > On Thu, 09 Jul 2009 14:14:31 -0700, fl wrote: > > > > > >> Hi, > > > > >> Block ram in FPGA can implement complex FSM, see the cited clue = below. > > > > >> My question here is how to convert the VHDL FSM to the block ram > > > > >> contents? Is there a tool to combine the logic bits to the ram c= ontent? > > > > >> Thanks. > > > > > >> Use the 4K bit RAM, properly initialized during configuration. S= o it > > > > >> really is a > > > > >> ROM, since you never write into it. > > > > >> Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input= and use > > > > >> the > > > > >> remaining 4 inputs as control. > > > > >> You now have a 32-state FSM with 4 condition inputs, and 3 extra > > > > >> arbitrarily decoded > > > > >> outputs, beyond the 5 encoded outputs. You can define everything= , like > > > > >> recovery from > > > > >> illegal states, etc. No holes. > > > > > >> In Virtex-II the ROM is bigger, 18K bits. So you can have a 128-= state > > > > >> FSM with 4 control inputs, with the ROMconfigured 2K x > > > > >> 9. > > > > >> Or 64 states with 5 control inputs. > > > > > > Before I forgot, anyone contemplating using a block ram as a rom = should > > > > > read this Xilinx Answer Record which describes a way that the rom > > > > > contents can be corrupted: > > > > > >http://www.xilinx.com/support/answers/21870.htm > > > > > > Regards, > > > > > Allan > > > > > Wow. That's one of those things that could be impossible to trouble= shoot if > > > > one is not aware of that requirement. > > > > Unbeknownst to anybody, including us at Xilinx, this situation has > > > existed for many years in all generations of BlockRAMs. Then one day > > > we had a customer who addressed the BRAM asynchronously to the clock, > > > (obviously not while WE was active). The customer told us that they - > > > most of the time- just ignored the read data output, but would stall > > > the address change whenever they really cared about the read data. A > > > very peculiar application that should work, but it resulted in > > > occasional unpredictable data corruption. A typical case of > > > metastability. > > > That lead to a deeper investigation, and a complete understanding, > > > creating the cited caveats. > > > There is no "cure", but the =A0work-around is easy: Just disable the > > > clock when the address set-up time might be violated. > > > BTW, the problem is so fundamental that Altera had to copy the same > > > warning into their User Guide. > > > Peter Alfke =A0 (Mr Metastable at Xilinx) > > > but the problem doesnt exist in Spartan generation incl S-6 > > and has been fixed in Virtex-6, I am correct? > > > because the AR only talks V-2 to V-5? > > > Antti > > The AR could not talk about future devices. > All BlockRAMs including the newest -6 ones, have this problem, but it > is so easy to avoid, just do not use the address input register as a > synchronizer. > Just disable the clock. And do not jump over to Altera, for they have > the same problem or feature. > The problem is easily avoided, once you know about it. It took more > than 5 years to be found out by a weird customer design. > I felt bad about this, until I had published the warnings in the User > Guides. > Peter Alfke future device? Spartan2 and spartan-3 were not future device at the time of writing of that AR Antti
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