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you are right glen and i'll use pipelined version of multiplication and that will give result in N clock cycles with respect to N multipliers....I make a multiplier with core generator and it utilizes 637 slices of spartan-3....I have FPGA-2 with 8 million gates....when i calculated for this, i would hardly to achieve my target. Thats why i put this on group. Now i want signed multiplier that should use less area and it must be efficient that will give me result in one clock cycle......thnx for your guidance rai glen herrmannsfeldt wrote: > Rai <raifasih@gmail.com> wrote: > > > thnx for your kind help and assistance. I got some of your points and > > will this work for signed numbers? I am using using signed > > multiplication using IP core generator. I'll use 100 of these > > multipliers and that makes a big problem while we are talking about > > fpga. It can't be implement on a single fpga considering the fact of > > area constraint. I also need my result in 1 cliock cycle for 16x16 > > multiplication. I am considering BOOTH Recoding algorithm and i want > > to know is there any algorithm which is most efficient then BOOTH > > algo? > > You don't say how big your FPGA is, or how much else you need. > 100 multiplies in one clock cycle sounds like a lot. > > Can you use pipelined multipliers that give N products in N > clock cycles, where N might be the width of the multiplier? > > -- glenArticle: 141801
On 9 Jul., 23:14, fl <rxjw...@gmail.com> wrote: > Hi, > Block ram in FPGA can implement complex FSM, see the cited clue below. > My question here is how to convert the VHDL FSM to the block ram > contents? Is there a tool to combine the logic bits to the ram > content? Thanks. > > Use the 4K bit RAM, properly initialized during configuration. So it > really is a > ROM, since you never write into it. > Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input and > use the > remaining 4 inputs as control. > You now have a 32-state FSM with 4 condition inputs, and 3 extra > arbitrarily decoded > outputs, beyond the 5 encoded outputs. You can define everything, like > recovery from > illegal states, etc. No holes. > > In Virtex-II the ROM is bigger, 18K bits. > So you can have a 128-state FSM with 4 control inputs, with the > ROMconfigured 2K x > 9. > Or 64 states with 5 control inputs. Hi, in the map properties you find an option "Map Slice Logic into unused Block RAMs", wich is disabled by default. Enable it. :-) Have a nice synthesis EilertArticle: 141802
Hello, is there anybody knows what the problem is? Thank you!Article: 141803
Rai <raifasih@gmail.com> wrote: > you are right glen and i'll use pipelined version of multiplication > and that will give result in N clock cycles with respect to N > multipliers....I make a multiplier with core generator and it utilizes > 637 slices of spartan-3....I have FPGA-2 with 8 million gates....when > i calculated for this, i would hardly to achieve my target. Thats why > i put this on group. Now i want signed multiplier that should use less > area and it must be efficient that will give me result in one clock > cycle......thnx for your guidance First, what is it that you actually need done? That is, what type of algorithm are the multipliers going into? How many mulitplies, and how wide, do you need per second? Likely you can get to 100MHz without so much work, 200MHz will be much harder. Do you really need 1e10 multiplies per second? 8 Million is a lot of gates, and it might be possible. -- glenArticle: 141804
Thanks for the reply, Gabor and Alan! Is there any specific fpga that works with generic eeprom that you know, so that I can look up the configuration document? Also, what are examples of eeprom that are common used noawdays? Also, what's the difference between using flash and eeprom? I looked up the Xilinx Virtex 5 and Spartan3 configuration user guide, but it doesn't give a step-by-step procedure on how to configure the FPGA or connect them. Is there any place where I can find a specific design to refer to?Article: 141805
On Jul 9, 11:43=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > "Nemesis" <neme...@nowhere.invalid> wrote in message > > news:20090709204834.4086.18180.XPN@orion.invalid... > > > Hi all, > > I'm using a Virtex4. > > > My project uses several clock generated by a DCM wich receive the > > external 100MHz. > > > For every of this clock I need the clock and its negated version. DCM > > gives 180=B0 version of almost every output but not for the CLKDIV outp= ut. > > Is possible to generate in a simple way a negated clock and have it > > recognized by the syntesizer (ISE8.2) like a real clock? > > > For example is it possible to use just a not port and put the exit in a > > clock buffer? > > Slices can be configured to work on either edge. =A0You can use a mixture= of: > > always @ (posedge clk) > always @ (negedge clk) > > and only one global clock resource is used. I'm not sure to understand. Both clocks (CLK and CLK180) are required by a FIFO module.Article: 141806
Ok i'll let you know my problem...I have two inputs with 8-bit width. These two inputs are the 8-bit image from camera. I need to correlate these two inputs by cross correlation and therefore i need to multiply these two inputs. my vector having 10,000 8-bit data. therefore i need 10,000 multiplication using 8-bit multiplier. My clock frequency is 66MHz. glen herrmannsfeldt wrote: > Rai <raifasih@gmail.com> wrote: > > you are right glen and i'll use pipelined version of multiplication > > and that will give result in N clock cycles with respect to N > > multipliers....I make a multiplier with core generator and it utilizes > > 637 slices of spartan-3....I have FPGA-2 with 8 million gates....when > > i calculated for this, i would hardly to achieve my target. Thats why > > i put this on group. Now i want signed multiplier that should use less > > area and it must be efficient that will give me result in one clock > > cycle......thnx for your guidance > > First, what is it that you actually need done? That is, what type > of algorithm are the multipliers going into? How many mulitplies, > and how wide, do you need per second? Likely you can get to 100MHz > without so much work, 200MHz will be much harder. Do you really > need 1e10 multiplies per second? 8 Million is a lot of gates, > and it might be possible. > > -- glenArticle: 141807
On 10 July, 11:17, Nemesis <gnemesis2...@gmail.com> wrote: > On Jul 9, 11:43=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote: > > > > > "Nemesis" <neme...@nowhere.invalid> wrote in message > > >news:20090709204834.4086.18180.XPN@orion.invalid... > > > > Hi all, > > > I'm using a Virtex4. > > > > My project uses several clock generated by a DCM wich receive the > > > external 100MHz. > > > > For every of this clock I need the clock and its negated version. DCM > > > gives 180=B0 version of almost every output but not for the CLKDIV ou= tput. > > > Is possible to generate in a simple way a negated clock and have it > > > recognized by the syntesizer (ISE8.2) like a real clock? > > > > For example is it possible to use just a not port and put the exit in= a > > > clock buffer? > > > Slices can be configured to work on either edge. =A0You can use a mixtu= re of: > > > always @ (posedge clk) > > always @ (negedge clk) > > > and only one global clock resource is used. > > I'm not sure to understand. > Both clocks (CLK and CLK180) are required by a FIFO module. What happens if you connect clk and ~clk to the true and negated clock ports? I think it will route the one global clock net to all slices in the FIFO and configure some as rising edge sensitive and some as falling edge sensitive.Article: 141808
"Rai" <raifasih@gmail.com> wrote in message news:8f8f48c1-e359-4096-a518-94aaa4b3bb29@m11g2000yqh.googlegroups.com... > Ok i'll let you know my problem...I have two inputs with 8-bit width. > These two inputs are the 8-bit image from camera. I need to correlate > these two inputs by cross correlation and therefore i need to multiply > these two inputs. my vector having 10,000 8-bit data. therefore i need > 10,000 multiplication using 8-bit multiplier. My clock frequency is > 66MHz. > Hi Rai, Have a read of this :- http://andraka.com/distribu.htm You could use your FPGA's clock multipliers, i.e. DCMs or PLLs, to make a faster clock, 4*66 = 264MHz for instance. Then use distributed arithmetic to do your calculations. With a modern FPGA you can probably clock even faster, but see how you go. HTH., Syms. p.s. This may be of interest also. http://andraka.com/cordic.htmArticle: 141809
Hello, I'm trying to implement 2 cores of microblaze on a virtex-4 (or virtex-5) fpga, using EDK tools and ISE. Please can anyone tell me about the procedure i should follow, noting that i already implemented one core and tested a C code on it. Thank you NadidjkaArticle: 141810
Hi, I'm trying to learn how to use the DCM's frequency synthesis capability
to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock. I
used Xilinx Architecture wizard to generate the code and the clock
multiplication works correctly in timing simulation. When I get to the
bench to test however, I don't get a multiplied clock output - the line is
0. I have a couple debug signals that tell me the following:
-75MHz, post BUFG looks fine (I see output from the FPGA)
-DCM Lock is 0
-Status(2 downto 0) are all 0.
I've tried the design on 2 different boards, ruling out defective
hardware. I'm really scratching my head here so I'd greatly appreciate some
help from a Xilinx guru!
Here is my VHDL for the clock multiplier (well, more accurately Xilinx's
VHDL):
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
DCM_INST : DCM
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 12.500,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"8080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS(7 downto 0)=>STATUS_OUT(7 downto 0));
Article: 141811On Jul 10, 3:23=A0am, Ben <leowy...@gmail.com> wrote: > Thanks for the reply, Gabor and Alan! > > Is there any specific fpga that works with generic eeprom that you > know, so that I can look up the configuration document? > Also, what are examples of eeprom that are common used noawdays? > Also, what's the difference between using flash and eeprom? > > I looked up the Xilinx Virtex 5 and Spartan3 configuration user guide, > but it doesn't give a step-by-step procedure on how to configure the > FPGA or connect them. Is there any place where I can find a specific > design to refer to? Ben, there was a decent article on command line configuration of the Spartan3E it was in the February issue of Nuts and Volts "FPGAs at the Command Line" by Bob Smith. He talks about the Xilinx tool set (XTS) and the bit stream in a small amount of detail to get the reader familiar. CyArticle: 141812
On Jul 10, 2:01=A0am, backhus <goo...@twinmail.de> wrote: > On 9 Jul., 23:14, fl <rxjw...@gmail.com> wrote: > > > > > > > Hi, > > Block ram in FPGA can implement complex FSM, see the cited clue below. > > My question here is how to convert the VHDL FSM to the block ram > > contents? Is there a tool to combine the logic bits to the ram > > content? Thanks. > > > Use the 4K bit RAM, properly initialized during configuration. So it > > really is a > > ROM, since you never write into it. > > Use it as 512 x 8 ROM. Feed 5 of the 8 outputs back to the input and > > use the > > remaining 4 inputs as control. > > You now have a 32-state FSM with 4 condition inputs, and 3 extra > > arbitrarily decoded > > outputs, beyond the 5 encoded outputs. You can define everything, like > > recovery from > > illegal states, etc. No holes. > > > In Virtex-II the ROM is bigger, 18K bits. > > So you can have a 128-state FSM with 4 control inputs, with the > > ROMconfigured 2K x > > 9. > > Or 64 states with 5 control inputs. > > Hi, > in the map properties you find an option "Map Slice Logic into unused > Block RAMs", wich is disabled by default. > Enable it. :-) > > Have a nice synthesis > =A0 Eilert- Hide quoted text - > > - Show quoted text - Thank you for the reply. A new question is how to use the dual port feature of BLK RAM to use it as two FSMs as the other poster suggested? See below link. Thanks. ............. In Virtex-II the ROM is bigger, 18K bits. So you can have a 128-state FSM with 4 control inputs, with the ROMconfigured 2K x 9. Or 64 states with 5 control inputs. Since these are synchronous dual-ported ROMs, you don't need any extra output or input registers, and you can run at 200 MHz. Also, you automatically get two FSMs in the same memory, both with the identical transition table, but individual control inputs and individual clocking. The link is: http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/3a3c7e43159= e30e3/4de1624925a109dc?hl=3Den&lnk=3Dgst&q=3DDISTRIBUTED+memory+fsm#4de1624= 925a109dcArticle: 141813
On Jul 9, 4:58=A0pm, nobody <cydrollin...@gmail.com> wrote: > Having enabled a pullup resistor on pin > 7i in the ucf, the switch i expected a momentary on and off again on > the LED when pressed and released. Instead, the LED lights and stays > on. I want the LED to follow the switch and not a one shot event. Any > ideas would be appreciated. so are you saying you power up, the led stays off, then you press the button once and the led stays on? sounds like a logic error. post your vhdl or verilog and we can tell you what is wrong.Article: 141814
On Jul 10, 10:54=A0am, "a...@nishioka.com" <a...@nishioka.com> wrote: > On Jul 9, 4:58=A0pm, nobody <cydrollin...@gmail.com> wrote: > > > Having enabled a pullup resistor on pin > > 7i in the ucf, the switch i expected a momentary on and off again on > > the LED when pressed and released. Instead, the LED lights and stays > > on. I want the LED to follow the switch and not a one shot event. Any > > ideas would be appreciated. > > so are you saying you power up, the led stays off, then you press the > button once and the led stays on? > sounds like a logic error. =A0post your vhdl or verilog and we can tell > you what is wrong. If all of the logic consists of driving the output from the input (pin 71) then the problem is with your pullup. Coolrunner 2 has a global pull type for the part which can be on or off for individual pins. It cannot be different (other than on or off) for different pins. So if any of your pins have a "keeper", pin 71 will also be a keeper which would behave just as you describe. What's the reasoning behind not putting a real pull-up resistor on the board? Power draw during button push? Cost savings? regards, GaborArticle: 141815
I have a mom switch normally open switching pin 71, general I/O, on a Coolrunner II CPLD, XC2C64A VQ100 to ground. I have an LED, 165 ohm connecting 3.3V into pin 8, general I/O, therefore a low emits radiation at 532nm, it does. Having enabled a pullup resistor on pin 7i in the ucf, the switch i expected a momentary on and off again on the LED when pressed and released. Instead, the LED lights and stays on. I want the LED to follow the switch and not a one shot event. Any ideas would be appreciated. Sincerely, Cy DrollingerArticle: 141816
Thanks for the replies: Alan, and Gabor. Below is the VHDL I appended
much of it so not to long but the logic for the switch is available as
well as a couple of lines for the UCF. I was not aware of the global
on keeper and pullup. I have tried the keeper or pullup in the ucf but
both have the same result as nothing in the UCF. The reason no pullup
on the board was I fully intended to use the pullup of the CPLD, that
is why Xilinx made them available so I did not have to. Thanks for the
consideration of my problem.
Is there a better way to post VHDL especially when it gets long?
UCF:
NET "SW(0)" LOC = "71" | PULLUP ;
NET "SW(1)" LOC = "72" | PULLUP ;
NET "SW(2)" LOC = "74" | PULLUP ;
NET "LEDs(1)" LOC = "P1" | PULLUP ;
NET "LEDs(2)" LOC = "P2" | PULLUP ;
NET "LEDs(3)" LOC = "P3" | PULLUP ;
NET "LEDs(4)" LOC = "P4" | PULLUP ;
NET "LEDs(5)" LOC = "P6" | PULLUP ;
NET "LEDs(6)" LOC = "P7" | PULLUP ;
NET "LEDs(7)" LOC = "P8" | PULLUP ;
NET "LEDs(8)" LOC = "P9" | PULLUP ;
VHDL
entity CPLD is
Port (
mclk : in STD_LOGIC; --pin 22
mclk_ce : out STD_LOGIC; --pin 70 Logic '0' MCLK high imp.
logic '1' MCLK 50 MHz pdf clk_osc
Variant : out STD_LOGIC_VECTOR (0 to 2); --pin 34, 33, 30
Mode : out STD_LOGIC_VECTOR (0 to 2); --pin 42, 39, 36
LEDs : inout STD_LOGIC_VECTOR (8 downto 1); --pin
1-4 and 6-9
SW : inout STD_LOGIC_VECTOR (0 to 2)); --pin 71, 72, 74 need to
be debounced
end CPLD;
architecture Behavioral of CPLD is
signal done :std_logic;
signal prog_B :std_logic;
Signal clk_count : integer range 0 to 50000000 :=0;
begin
one_second: process(mclk)
begin
if mclk'event and mclk='1' then
if clk_count = 50000000 then
clk_count <= 0;
if LEDs(8) ='1' then
LEDs(8) <= '0';
else
LEDs(8) <='1';
end if;
else
clk_count <= clk_count + 1;
end if;
end if;
end process one_second;
-- Author : Cy Drollinger
-- Date : 6-18-09
-- Description : Hardwiring the CPLD for the board configuration of
the usb and fpga
-- FPGA MODE --
--Mode <= "101"; --DS312 page 67 mode jtag
--Mode <= "111"; --DS312 page 67 mode jtag
--Mode <= "110"; --DS312 page 67 mode Slave Parallel
--Mode <= "011"; --DS312 page 67 mode BPI down
--Mode <= "010"; --DS312 page 67 mode BPI up
--Mode <= "001"; --DS312 page 67 mode SPI
--Mode <= "000"; --DS312 page 67 mode master serial
-- FPGA SPI FLASH VARIANCE --
--Variant <= "111"; --DS312 page 78 variant for fast
read write spi flash M25P16
Variant <= "101"; -- Read
--Variant <= "110"; --Read Array
done <= FPGA_done;
LEDs(1) <= '0';
LEDs(2) <= '0';
LEDs(3) <= '0';
LEDs(4) <= '0';
LEDs(5) <= '0';
LEDs(6) <= sw(0);
LEDs(7) <= sw(1);
--LEDs(8) <= sw(2);
prog_B <= SW(0);
FPGA_prog_B <= prog_B;
mclk_ce <= '1';
end Behavioral;
Article: 141817On Jul 10, 8:52=A0am, nobody <cydrollin...@gmail.com> wrote: > Thanks for the replies: Alan, and Gabor. Below is the VHDL I appended > much of it so not to long but the logic for the switch is available as > well as a couple of lines for the UCF. > NET "SW(0)" LOC =3D "71" | PULLUP ; > > NET "LEDs(8)" LOC =3D "P9" | PULLUP ; > > VHDL > > one_second: process(mclk) > begin > =A0 =A0 if mclk'event and mclk=3D'1' then > =A0 =A0 =A0 if clk_count =3D 50000000 then > =A0 =A0 =A0 =A0 =A0 =A0clk_count <=3D 0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if LEDs(8) =3D'1' the= n > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 LEDs(8) <=3D '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 LEDs(8) <=3D'1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0 =A0clk_count <=3D clk_count + 1; > =A0 =A0 =A0 =A0end if; > =A0 =A0 end if; > end process one_second; > LEDs(1) <=3D '0'; > LEDs(2) <=3D '0'; > LEDs(3) <=3D '0'; > LEDs(4) <=3D '0'; > LEDs(5) <=3D '0'; > LEDs(6) <=3D sw(0); > LEDs(7) <=3D sw(1); > --LEDs(8) <=3D sw(2); did you post the right code? this code looks like it is supposed to flash the led at 1s. does it work? also, you say led is on pin8, but led(8) is on pin9.Article: 141818
> I'm trying to implement 2 cores of microblaze on a virtex-4 (or virtex-5) > fpga, using EDK tools and ISE. > Please can anyone tell me about the procedure i should follow, noting that > i already implemented one core and tested a C code on it. You can hand-edit the mhs and mss files to duplicate entries and add a unique suffix to each modified core. If the mb are to communicate, then a shared opb/plb bus is needed (or a fsl link). I typically put shared resources (e.g. uart) on a separate bus with bridges to unique buses, and use a multiported mpmc to access SDRAM memory on the MLxxx demo boards. Note that XPS is quite picky about modified core & port names. Our company has tools which automate the building of multiprocessors -- there is an appnote which you might find useful at www.codetronix.com >Downloads>AppNotes>MPSoC Contact me privately if you want simple working xps project examples using multiple microblazes with plb, opb or fsl. /PerArticle: 141819
Hi, You just have to feedback the CLK0 to CLKFB! otherwise the DLL will not lock :) On Jul 10, 4:40=A0pm, "muse_ee" <brian.bubn...@jhuapl.edu> wrote: > Hi, I'm trying to learn how to use the DCM's frequency synthesis capabili= ty > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock. = I > used Xilinx Architecture wizard to generate the code and the clock > multiplication works correctly in timing simulation. When I get to the > bench to test however, I don't get a multiplied clock output - the line i= s > 0. I have a couple debug signals that tell me the following: > > -75MHz, post BUFG looks fine (I see output from the FPGA) > -DCM Lock is 0 > -Status(2 downto 0) are all 0. > > I've tried the design on 2 different boards, ruling out defective > hardware. I'm really scratching my head here so I'd greatly appreciate so= me > help from a Xilinx guru! > > Here is my VHDL for the clock multiplier (well, more accurately Xilinx's > VHDL): > =A0 =A0GND_BIT <=3D '0'; > =A0 =A0CLKIN_IBUFG_OUT <=3D CLKIN_IBUFG; > =A0 =A0CLKFX_BUFG_INST : BUFG > =A0 =A0 =A0 port map (I=3D>CLKFX_BUF, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKFX_OUT); > > =A0 =A0CLKIN_IBUFG_INST : IBUFG > =A0 =A0 =A0 port map (I=3D>CLKIN_IN, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKIN_IBUFG); > > =A0 =A0DCM_INST : DCM > =A0 =A0generic map( CLK_FEEDBACK =3D> "NONE", > =A0 =A0 =A0 =A0 =A0 =A0 CLKDV_DIVIDE =3D> 2.0, > =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_DIVIDE =3D> 4, > =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_MULTIPLY =3D> 5, > =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_DIVIDE_BY_2 =3D> FALSE, > =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_PERIOD =3D> 12.500, > =A0 =A0 =A0 =A0 =A0 =A0 CLKOUT_PHASE_SHIFT =3D> "NONE", > =A0 =A0 =A0 =A0 =A0 =A0 DESKEW_ADJUST =3D> "SYSTEM_SYNCHRONOUS", > =A0 =A0 =A0 =A0 =A0 =A0 DFS_FREQUENCY_MODE =3D> "LOW", > =A0 =A0 =A0 =A0 =A0 =A0 DLL_FREQUENCY_MODE =3D> "LOW", > =A0 =A0 =A0 =A0 =A0 =A0 DUTY_CYCLE_CORRECTION =3D> TRUE, > =A0 =A0 =A0 =A0 =A0 =A0 FACTORY_JF =3D> x"8080", > =A0 =A0 =A0 =A0 =A0 =A0 PHASE_SHIFT =3D> 0, > =A0 =A0 =A0 =A0 =A0 =A0 STARTUP_WAIT =3D> FALSE) > =A0 =A0 =A0 port map (CLKFB=3D>GND_BIT, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKIN=3D>CLKIN_IBUFG, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DSSEN=3D>GND_BIT, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSCLK=3D>GND_BIT, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSEN=3D>GND_BIT, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSINCDEC=3D>GND_BIT, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 RST=3D>RST_IN, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKDV=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX=3D>CLKFX_BUF, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX180=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK0=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X180=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK90=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK180=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK270=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOCKED=3D>LOCKED_OUT, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSDONE=3D>open, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 STATUS(7 downto 0)=3D>STATUS_OUT(7 downto= 0));Article: 141820
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I am curious if anyone here has ever dug into at what point the DCM's lock signal will trip. I assume that once the output and reference are within some tolerance that the lock will go true. Maybe there is a filter on it as well so it has to be in tolerence for some number of cycles of something first. Same may hold true that the clock must be out of bounds by some tolerence for some number of cycles before the lock will clear (assuming the input clock stays running). Maybe the DCM continues to settle in further after lock is true. From my own tests, the later seems to be true at least with the V4. I am sure I am splitting hairs with the question and maybe 99.999% of designs could care less about any gains from something like this. If you have dug into the details of the inner workings of the DCM, please post your findings.Article: 141822
On Jul 9, 2:14=A0pm, fl <rxjw...@gmail.com> wrote: > Hi, > Block ram in FPGA can implement complex FSM, see the cited clue below. I was the author of the original =93clue=94, years ago, but unfortunately I cannot offer a synthesis tool. The design is nicely universal. Before you start the design, you obviously already know the number of states S, the number of conditional inputs N, and the number of outputs Q. For total generality, you need a ROM with (log base 2 of S) + N input lines, and (log base 2 of S) + Q outputs. Let=92s assume a 2K x 18 BlockRAM with 11 address inputs: You can have 32 states, 6 condition inputs and 13 outputs, or 64 states, 5 controls, and 11 outputs. Total generality means: You can jump from any state to any other state, as determined by any combination of control codes. And any state generates any desired combination of outputs. All that in one BlockRAM, running at up to 500 MHz. Control inputs are precious, and you may sometimes want to encode them. Peter Alfke, XilinxArticle: 141823
In article <6f0e936a-d2c2-4ccb-a316-ffef43ce913a@d4g2000yqa.googlegroups.com>, Peter Alfke <peter@xilinx.com> writes: >On Jul 9, 2:14=A0pm, fl <rxjw...@gmail.com> wrote: >I was the author of the original =93clue=94, years ago, but unfortunately >I cannot offer a synthesis tool. Somewhere around 30-100 states it gets simpler to think of it as software/microcode rather than a traditional FSM. Then you have to write an assembler. We used to start with the one leftover from the last project. Anybody got a handy sample? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 141824
We have a product coming shortly based on our Craignell2 but a development board format that might offer an alternative. If you have a few weeks then wait and see if suits your application. John Adair Enterpoint Ltd. On Jul 6, 2:19=A0pm, "AstroLad" <Astro...@cox.net> wrote: > Does anyone know of anything similar to the Suzaku SZ030/SZ130? It's just > about a perfect fit for a short production run product I'm helping a frie= nd > with. Perfect that is except the price. What we need is an FPGA as good o= r > better than a XC3S1000, 1MB or more of RAM (SRAM or SDRAM) and 100MB > Ethernet. It does not absolutely have to be a Spartan. An Altera Cyclone = of > some flavor would do if the price were right. We already have a lot of > development done using Digilent Spartan boards. We don't need the > Microblaze as we have a CPU from OpenCores that is adequate.
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