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Hi everyone! I'm trying to create a bootloader application for booting Microblaze from 32Mbit SPI flash. I've looked at the examples at http://www.xilinx.com/products/boards/s3estarter/files/s3esk_serial_flash.pdf and everything works fine. On power-up fpga is configured from SPI flash then bootloader starts from block RAM, it copies main program from SPI flash to DDR RAM and microblaze starts executing it. But when I try to boot my application that uses interrupts and 64KB of stack and heap, I get stuck. I use the following procedure: - create *.elf file of application (it works if I download it with: XMD% dow executable.elf) - create *.b file from *.elf file with mb-objcopy - download *.b file to DDR RAM with: XMD% dow -data binary.b <DDR Address> - manually set vectors (reset, interrupt) using: XMD% mwr - set program counter to 0 and run My application starts, draws initial GUI screen and then freezes (could it be due to stack overflow?). But if I do the following: - XMD% dow executable.elf - XMD% dow -data binary.b <DDR Address> - XMD% run it works fine. I am trying to do booting process from XMD, then have the same thing done by my bootloader. Is it possible that my bootloader does everything just the same as: XMD % dow executable.elf? Can anyone tell me what am I doing wrong? Or if anybody has an example of how to make an SPI bootloader? Any suggestions would be very appreciated. Thanks.Article: 137901
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: > Brian Drummond <brian_drummond@btconnect.com> wrote: > ... > > http://www.xilinx.com/products/v6s6.htm > > It seems to be on now. > Argh, no PQ208 option... And no 3.3V IO for the Virtex-6 Devices -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 137902
On Feb 2, 12:41=A0am, reganirel...@gmail.com wrote: > 1 more things I should have added: > > I have used XAPP485 to do the deserializing of the stream. Camera Link puts FVAL and LVAL in the same LVDS pair for the channel link interface. So it is possible that only that one pair has some signal integrity problem, possibly too much skew to the clock pair? If that is the case and the other pairs work OK, you could get good pixel data while the FVAL and LVAL signals bounce around. Regards, GaborArticle: 137903
On Feb 2, 3:00=A0am, backhus <n...@nirgends.xyz> wrote: > Hi Ehsan, > you don't have to worry much about the fan out. > The synthesis tool takes care of it. Funny, we've had problems with this. We ended up duplicating our CE signal into a vector and putting the appropriate preserve attributes on every element, such that each element has a relatively low fanout. ChrisArticle: 137904
Hi, Endpoint block plus 1.9 use an Expension ROM BAR, you have to make a completion when the system try to read this rom when startup pc. For more info, take a look at UG341 page 43. Bernard Massi a écrit : > Hi everyone, I'm trying to program a Xilinx Virtex 5 (on Avnet PCI > Express Development Kit board). I downloaded the bistream generated by > the PIO example design which comes up with the PCI core (endpoint > block 1.9) but when I reboot the system in order to recognize the > board, the PC hangs forever. Do you have any idea about what it could > depend on? By the way, the board is a x8 lane, but it is plugged in a > x16 lane slot. > > Thanks in advance.Article: 137905
> This has been noted on the Xilinx forums and many > people are annoyed by it. =A0Xilinx responded that their > http based downloader works better to serve large > numbers of downloads. =A0Often your best choice is to > request a CD or DVD by mail, especially if your > Internet connection is not blazing fast. > > Gabor- Hide quoted text - Nice that they dropped that service as part of the maint. contracts. No DVDs No phone support (depending on who you are) If you use a webcase, the goal is not for them to answer your question but to close the webcase. You get some pretty funny and bad advice now days. Must buy software from rep's who can't handle simple license problems. They are moving in the right direction I would say.Article: 137906
LittleAlex wrote: > > Get a used one on eBay, of buy one OEM from the same place Altera > does. > Also, Terasic has a clone of the USB Blaster for $50: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=53&No=46 -hpaArticle: 137907
Hi .*,
in my partially reconfigurable Xilinx EDK design, I'm trying to
constrain a certain BUFG to a BUFGMUX location. The BUFG in question
is located inside a DCM wrapper, and its instantiation is controlled
by a generic:
### excerpt from DCM source code $XILINX_EDK/hw/XilinxProcessorIPLib/
pcores/dcm_module_v1_00_c/hdl/vhdl/dcm_module.vhd>
Using_BUGF_for_CLK0 : if (C_CLK0_BUF) generate
CLK0_BUFG_INST : BUFG
port map (
I => CLK0_BUF,
O => CLK0);
end generate Using_BUGF_for_CLK0;
###
How do I find the actual instance name of this BUFG to put into my UCF
file? I've tried looking it up in the fpga_editor, which gives me
"dcm_0/dcm_0/Using_BUGF_for_CLK0.CLK0_BUFG_INST", which doesn't work
(ngdbuild complains about unrecognized LOC constraints). I've tried
allowing unmached constraints (-aul), mapping the design, and
converting it to a xdl file using "xdl -ncd2xdl". That crashed on me
with an assertion error. I've tried almost every combination of
slashes, underscores and periods to separate the components of the
instance name, to no avail.
I'm using ISE9.2.04/EDK9.2.02 with EAPR patch PR7. The FPGA is a
xc2vp30-ff896.
Any suggestions would be greatly appreciated!
Thanks
- Enno
Article: 137908On Feb 2, 2:46=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Brian Drummond <brian_drumm...@btconnect.com> wrote: > > ... > > >http://www.xilinx.com/products/v6s6.htm > > It seems to be on now. > > Argh, no PQ208 option... > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Uwe, did you really expect Xilinx could ever offer PQ208 again? the market segment where 100% solder joint inspection is required is too small for Xilinx to take it seriously in the package selection. sure the X-ray inspection is major PITA and expensive, but thats not enough a reason for Xilinx to offer PQ208 i have to say i was positivly surprised to see any non-BGA packages at all! the chip-scale package selection is not that bad actually. of course what is MAJOR issue is that the AES encryption is available only for the largest S-6 devices. this means that xilinx can enter the large volume consumer market at all. The device DNA really isnt any option. AnttiArticle: 137909
Hello, In case anyone hasn't already seen, Xilinx has some preliminary information about Virtex-6 and Spartan-6 online here - http://www.xilinx.com/products/v6s6.htm . I do have a question about Virtex-6 and it's one LUT6/two flip-flop architecture. I'm struggling to think of why a user would have any use for that second flip-flop. It seems to me that the second flip-flop only has use when the LUT6 is split into two LUT5's. However, the family overview indicates that a dual-LUT5 has the same restriction as in Virtex-5 - the inputs to the dual-LUT5s have to be the same. I know in my designs I don't tend to get many LUT5s synthesized, so I'm not sure how often that actually happens. The only other case I can even think of is to use the second flip-flop as solely a storage element, but without the ability to drive the clock enable input of the flop by some sort of combinational signal (ie, an address decode) without "spending" the associated LUT6, it's use seems very limited. I am very cognizant of the fact that the people here and at Xilinx are smarter than me. So, I figured that I'd give them a chance to explain the design choice. I'm always interested in ways to use FPGA resources more effectively. Thanks! - NathanArticle: 137910
Antti <Antti.Lukats@googlemail.com> writes: > the market segment where 100% solder joint inspection is required > is too small for Xilinx to take it seriously in the package selection. For some of us, it's not about inspecting the joint, it's about making it. CSP/BGA packages are a non-starter for small-shop prototyping. The 1.0mm BGA packages are marginal for prototype-level PCB fabs, and even then you can only use the outer few rows of balls.Article: 137911
On Feb 2, 7:19=A0pm, DJ Delorie <d...@delorie.com> wrote: > Antti <Antti.Luk...@googlemail.com> writes: > > the market segment where 100% solder joint inspection is required > > is too small for Xilinx to take it seriously in the package selection. > > For some of us, it's not about inspecting the joint, it's about making > it. =A0CSP/BGA packages are a non-starter for small-shop prototyping. > The 1.0mm BGA packages are marginal for prototype-level PCB fabs, and > even then you can only use the outer few rows of balls. well I have a 0.5mm BGA using more than outer pads and made on 2 layer with cheap PCB technology :) (as a finger excercise...) it's funny the ex-technology master of that PCB fab looked the PCB and could not belive when i told him where the PCB was made... the PCB was made without solder mask, chemical tin, soldered with hot air repair station, and the FPGA does work also :) with 1.0mm there is MUCH more playgroung available Antti From rgaddi@technologyhighland.com Mon Feb 02 09:31:22 2009 Path: flpi142.ffdc.sbc.com!flph199.ffdc.sbc.com!prodigy.com!flph200.ffdc.sbc.com!prodigy.net!newshub.sdsu.edu!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Mon, 02 Feb 2009 11:31:19 -0600 Date: Mon, 2 Feb 2009 09:31:22 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: Dangling blockram output - how to remove warning? Message-Id: <20090202093122.a11cf9f8.rgaddi@technologyhighland.com> References: <76d6d248-7dfa-4701-9741-e52d8affea57@g3g2000pre.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 28 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-L6Lokg4bfCnKXvWwR3C6KY5AZ1d79ImV3bA7wMllEO+ch7gT8M0aI7fy7RL2iiyht/jyPW7SfmRwWdj!Me/oVL1F3t3uzhULXx8NGMWSIF7YAeVNTxqjHdYvBi3xeERrkSlyhIfI7Bf9V8SCOYMvy7erzHgz!6m+cDA4cCvmdl8ndQfE= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: prodigy.net comp.arch.fpga:151019 X-Received-Date: Mon, 02 Feb 2009 12:31:20 EST (flpi142.ffdc.sbc.com) On Sun, 1 Feb 2009 13:46:03 -0800 (PST) aleksa <aleksaZR@gmail.com> wrote: > I'm using CORE generated block ram (ROM, actually) > with the width of 12 bits and ISE 10.1 creates > a 16bit wide bus and gives me a warning > for upper 4 bits (which I don't need): > > WARNING PhysDesignRules:1109 - Blockcheck:Dangling > BLOCKRAM_BLOCKRAMA output. Pin OUT12-15 of comp > ROM/B6.A is not connected. > > How can I remove the warnings? > > I think I can safely ignore them, > but I don't like warnings.. > > TIA At least out of XST (where I often get an embarrassing number of warnings), I've resorted to post-filtering the results with an AWK script to strip out warnings that I've decided I'm okay with. Something similar can be done here. After all, if you can't see the problem, it doesn't exist, right? -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 137912
Nathan Bialke wrote: > Hello, > > In case anyone hasn't already seen, Xilinx has some preliminary > information about Virtex-6 and Spartan-6 online here - > http://www.xilinx.com/products/v6s6.htm . > > I do have a question about Virtex-6 and it's one LUT6/two flip-flop > architecture. I'm struggling to think of why a user would have any use > for that second flip-flop. It seems to me that the second flip-flop > only has use when the LUT6 is split into two LUT5's. However, the > family overview indicates that a dual-LUT5 has the same restriction as > in Virtex-5 - the inputs to the dual-LUT5s have to be the same. I know > in my designs I don't tend to get many LUT5s synthesized, so I'm not > sure how often that actually happens. The only other case I can even > think of is to use the second flip-flop as solely a storage element, > but without the ability to drive the clock enable input of the flop by > some sort of combinational signal (ie, an address decode) without > "spending" the associated LUT6, it's use seems very limited. > > I am very cognizant of the fact that the people here and at Xilinx are > smarter than me. So, I figured that I'd give them a chance to explain > the design choice. I'm always interested in ways to use FPGA resources > more effectively. I haven't looked at the new Xilinx architecture, but it sounds like the capabilities provided by shrinking geometries has reached the point of saying bye-bye to the highly regarded LUT4. We discussed this recently here and it was mentioned that as geometries continue to shrink, it will be come more advantageous to provide more capability in the logic with relatively reduced routing. By "relatively" reduced, I mean they will not have as much routing per "gate equivalent" as the logic cells get more complex. It actually makes sense to do this and I am a bit surprised that it has taken this long to get to the LUT5/6 instead of the LUT4/5. In the meantime they have added, first memory blocks, then MACs and finally more functional DSP units. Along the way the I/O has been suped up with high speed serdes, but that is not really related to the logic/routing mix. The question of LUTn vs FF ratio is a tradeoff. Different designs has different needs. It is not at all uncommon for comms designs to use naked FFs for delay elements. Other designs might use only a fraction as many FFs as LUTs although I don't know how this will change with 6 LUTs. It is very common for multiple 4 LUTs to feed a single FF. So it is not surprising that more FFs are included for a given number of 6 LUTs. So what other functional blocks will be coming along as the densities continue to increase? Some MCU devices provide complex serial I/O units that can flexibly drive multiple serial I/O interface types. Likewise they often provide widely capable timer functions. These specific functions may not have wide utility in FPGAs, but I expect some types of generically capable logic other than LUTs, memory and DSP blocks will identified and implemented. I think that LUTs can only go so far. The problem of selling the routing and giving the logic for free limits how low the price can get and therefore use in the highest volume applications. RickArticle: 137913
On 2009-02-02, FredrikH <fredrik.holmsten@gmail.com> wrote: > Your decoding core also looks interesting. Please tell me more about > it. You are mentioning processor - is it a custom hardware accelerated > processor executing code?? Or? It is a floating point DSP processor. (But not IEEE floating point, you don't need 32-bit floating point numbers to decode MP3 files). Anyway, besides some standard DSP stuff (multiply-accumulate, special address generators) it is a fairly standard single issue SISD RISC processor. > Generally, do you have any idea how many streams you can encode/decode > in real time in a 30 000 LUT FPGA? You?re free to use any technique! This is going to be fairly speculative. Also, I will only consider decoding here since I don't have much experience with encoding. You didn't state what FPGA family you are using, so I'll choose the Virtex-4 (speedgrade 12) as that is the only family I have recent numbers for. I also assume that you don't care very much about audio latency. (If you do, you may want to use layer I or II instead if I understand things correctly.) With 2370 LUTs per processor I can fit around 12 cores into the FPGA. (12.7 actually, but lets save those LUTs for memory controllers, etc.) If I just duplicate the cores I would need around 12*22 block rams as well which is probably beyond your blockram budget. However, by using some sort of SIMD technique it would be possible to significantly reduce the amount of program memory required by the various filters. Lets say that the amount of program memory per core would be 2 RAMB16 (plus some shared program memory for the IMDCT/DCT part of the algorithm, but that is not going to be very large in comparison so lets ignore that). For intermediate storage when decoding one bitstream we require around 12000 bytes, roughly 6 blockRAMs. This means that we will only need around 72 blockrams for intermediate data. Plus 2*12 RAMB16 for program code that cannot be shared. (Could perhaps reduce this by half by using both ports.) Plus shared program memory for the filters when using the cores in SIMD mode (around 11 RAMB16). I haven't really considered Huffman decoding now, but I believe that to be solvable by using a few Huffman decoding accelerators. Lets assume that we will not get into any problems when trying to clock all cores at 200 MHz (one core can be clocked at this frequency without any problems). Since each core is able to handle one MP3 bitstream at 20 MHz (theoretical worst case, average required clock rate is probably around 14 MHz or so for a 128 kbit stereo MP3) we should be able to handle around 120 bitstreams simultaneously. Unfortunately we don't have enough temporary store to do this. So we will need to context switch fairly frequently. Memory bandwidth estimation when decoding 120 bitstreams: Full context switch of all cores: roughly 144000 bytes write, 144000 bytes read Bitstream input: worst case 320kbit/s streams: 4.8 Mbyte / s Audio output: (worst case) 48 KHz, 16 bit/sample, stereo: 23 Mbyte / s We will probably need to context switch quite a lot. Lets say 10 times per second (if we can tolerate at least 1s audio delay). That means a memory traffic of 28.8 Mbyte/s for context switches. For the audio output we really need to send data to the main memory to buffer it and then read it back from the main memory: 46 Mbyte / s Conclusion: With a 100 MHz 8-bit memory interface the memory bandwidth is doable. Final conclusion: It should be possible to decode 120 bitstreams in real time on a 30000 LUT Virtex-4 (speedgrade 12) assuming that you are allowed to use off-chip memory. Speculation: If you optimize the architecture for the Virtex-4 FPGA you could probably double this (assuming a faster memory interface to off-chip memory). Out of interest, how many bitstreams do you need to decode and encode simulatenously? :) /AndreasArticle: 137914
On 31 Jan, 07:01, Antti <Antti.Luk...@googlemail.com> wrote: > On Jan 31, 8:06=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Jan 30, 6:43=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > > > > > What happened to 4 & 5? > > > > Looks like Xilinx marketing want to 'resync' as the Virtex 6 and > > > Spartan 6 > > > (and hey, it's a number =A0higher than Altera so that's worth somethi= ng > > > in their > > > world, right ;) > > > > Anyone seen package choices for Spartan 6 yet ? > > > > Are Xilinx going to push prices, or leave the sub $1 / Low power area > > > to Actel ? > > > I sure wish they would support the smaller leaded packages. =A0A decent > > sized chip in a 100 pin QFP would be so nice; low price, easy assembly > > and good access to the pins for debug. =A0I don't get why they haven't > > done this before. =A0Every I/O adds cost. =A0They won't get under $10 i= n > > moderate quanties until they pick some better packages. > > > Rick > > Sorry Rick I can not comment in public. I hope it all be known on > monday. > I have some comments, i make them public as soon as the info is no > longer under NDA > (that is i can comment on what xilinx has made public itself) > > Antti I just had an email from Xilinx announcing the Virtex-6 and Spartan-6: http://www.xilinx.com/products/v6s6.htm LeonArticle: 137915
I've already found solutions to the problem. I needed to set reset, interrupt, etc. vectors in bootloader or in my application. One way to do this can be found here :http://forums.xilinx.com/xlnx/ board/message? board.id=EDK&thread.id=6833&view=by_date_ascending&page=2 But I used a simpler one. I downloaded my application with XMD (that way it works) and then read correct vector values with XMD% mrd 0x0 10. Then I set those values in my bootloader application and it works great! Kind regards!Article: 137916
On 31 Jan, 06:06, rickman <gnu...@gmail.com> wrote: > On Jan 30, 6:43=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > > > > What happened to 4 & 5? > > > Looks like Xilinx marketing want to 'resync' as the Virtex 6 and > > Spartan 6 > > (and hey, it's a number =A0higher than Altera so that's worth something > > in their > > world, right ;) > > > Anyone seen package choices for Spartan 6 yet ? > > > Are Xilinx going to push prices, or leave the sub $1 / Low power area > > to Actel ? > > I sure wish they would support the smaller leaded packages. =A0A decent > sized chip in a 100 pin QFP would be so nice; low price, easy assembly > and good access to the pins for debug. =A0I don't get why they haven't > done this before. =A0Every I/O adds cost. =A0They won't get under $10 in > moderate quanties until they pick some better packages. > > Rick TQ144 is the smallest Spartan-6. LeonArticle: 137917
On 30 Jan, 11:00, colin <colin_toog...@yahoo.com> wrote: > Hello > > Has anyone here successfully built a byteblaster clone. I have > connected up the JTAG pins as specified and Quartus accepts that a > byteblaster is fitted. I can see activity on TCLK, TMS and TDI at the > FPGA and TDO is getting back to the parallel port but Quartus cannot > auto detect anything. My system works with a proper > Byteblaster but I have to give it back soon. > > Any ideas will be appreciated. > > Colin I've got a PCB design for a clone of the original parallel port BB you can have. LeonArticle: 137918
Leon <leon355@btinternet.com> wrote: > TQ144 is the smallest Spartan-6. ... and the onle non-BGA -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 137919
On Mon, 2 Feb 2009 00:59:11 -0800 (PST), Digi Suji <digisuji@gmail.com> wrote: >Hi, > >My design has modules like i2c controller, cpu, sram, gpio. I >integrated all the above modules. This design is implemented in >Spartan 3e based Digilent Basys board. The design when triggered, >reads data from the externally connected I2C EEPROM, copies into SRAM >in the design and then triggers the cpu to process the data and output >the result on to the leds on board. > >When I configure the FPGA with the bit file(write the bit file into >ROM on board/FPGA), the design works fine for the first time but when >I push the FPGA reset button to reconfigure the FPGA, the design does >not work. When I power the whole board off, wait for some time and >then repeat the process, it works fine only for the first time. You're probably not using the reset correctly. Make sure you synchronize the reset signal to your internal clock (ie pass it through a 2 bit shift register and use the output as the reset) which would allow you to check the timing of it whether it's synchronous or asynchronous. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 137920
On Feb 2, 8:33=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Leon <leon...@btinternet.com> wrote: > > TQ144 is the smallest Spartan-6. > > ... and the onle non-BGA > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- it could be that there is one BIG client who needs this package this also explains why it was in initial offering for the S3A as only non-BGA (at initial announcment of s3a) AnttiArticle: 137921
kristian <kris11@gmx.de> wrote: > I'm implementing a autocorrelation function using a fft and ifft hard core > (v6.0) on a Virtex5. When starting the fft, I see at the output that the > result is reversed in the frequency domain. If you are feeding the result of fft into ifft, possibly with some frequency domain filtering, it is much more efficient that way. If not, there should be cores that generate in the more usual order. -- glenArticle: 137922
Nathan Bialke <nathan@bialke.com> wrote: > In case anyone hasn't already seen, Xilinx has some preliminary > information about Virtex-6 and Spartan-6 online here - > http://www.xilinx.com/products/v6s6.htm . > I do have a question about Virtex-6 and it's one LUT6/two flip-flop > architecture. I'm struggling to think of why a user would have any use > for that second flip-flop. It seems to me that the second flip-flop > only has use when the LUT6 is split into two LUT5's. However, the > family overview indicates that a dual-LUT5 has the same restriction as > in Virtex-5 - the inputs to the dual-LUT5s have to be the same. If the inputs to an LUT5 are the same, that doesn't mean the outputs are the same. I could easily imagine designs that would take five inputs, put them through two different blocks of logic, and register the two outputs. -- glenArticle: 137923
Antti wrote: > On Feb 2, 8:33 pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- > darmstadt.de> wrote: >> Leon <leon...@btinternet.com> wrote: >>> TQ144 is the smallest Spartan-6. >> >> ... and the onle non-BGA >> -- >> Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de >> >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > it could be that there is one BIG client who needs this package > this also explains why it was in initial offering for the S3A > as only non-BGA (at initial announcment of s3a) > > Antti Hi, It might be the only TQ package that has a hope in hell of having decent SI performance with the rise times of these new parts. I'd suggest only QFNs would be an alternative to the BGA packages. I see 3.3V logic has gone from the V6 parts. Cheers, Syms.Article: 137924
Hi everyone, I have 2 unrelated questions: 1) I have a Xilinx ML505 board and I am looking for a way to make my SRAM power cycle automatically. Ideally I would like the SRAM to power off, then power on again after 30 seconds or more. Is there any way to have either the SRAM individually, or the board as a whole, do this? 2) The ML505 schematics say the RS 232 port is DTE, while the User Guide says it is DCE. Can anyone confirm which is correct? Do I need a null-modem cable or a straight-through cable to connect to a PC? Thank you, Robyn Colopy
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