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Weng Tianxiang wrote: > Here it is a Xilinx invention about 4*4 module. The topic of this newsgroup is vhdl. -- Mike TreselerArticle: 141576
"Mike Treseler" <mtreseler@gmail.com> wrote in message news:4A477373.8040406@gmail.com... > Fredxx wrote: > >> Hmm - perhaps you're interfacing with an external IC. Are you going to >> tell me you'd blindly write a testbench without confirming that your >> interface in real hardware is correctly understood? > > Standard interfaces are well documented. > Certainly I have to verify a few things on the bench, > but starting with a sim improves my odds. It sounds we're really singing from the same hymn sheet, the difference is I'm more honest to say that simulation is sometimes no substitution for reality. > >> It's clear you've never got a PCI or PCIe interface working without >> resorting to the likes of chipscope, where reality doesn't even match >> signals as per standards. > > We purchased a PCIe core that came with a testbench. > I just worked. > Perhaps I'm missing something here, but I would hope the purchased core and test bench would work straight out of the box?Article: 141577
Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You should have FPGA / CPLD Design / Verification on your Profile. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC and other HDL's as well. Vendors included: Xilinx, Altera, Actel, Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, Synopsys, Aldec, NI, Altium, and Many Others. Networking on LinkedIn can be a way to get technical questions answered. It can also be a way to meet contacts with expertise in other domains of knowledge other than your own. Additionally, many career enhancing contacts, and mentors can potentially found especially if one is at a smaller company that lacks the resources for extensive internal networking. http://www.linkedin.com/groups?about=&gid=56713 Website: https://sites.google.com/site/fpgacpldgroup/Article: 141578
On Jun 28, 5:09=A0pm, cpld-fpga-asic <cpld.fpga.a...@gmail.com> wrote: > Group for People Involved In the Design and Verification of FPGA's, > other Programmable Logic , and CPLD's to Exchange Idea's and > Techniques. You should have FPGA / CPLD Design / Verification on your > Profile. (The focus is more on FPGA/CPLD in the product as opposed to > FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > Synopsys, Aldec, NI, Altium, and Many Others. > > Networking on LinkedIn can be a way to get technical questions > answered. It can also be a way to meet contacts with expertise in > other domains of knowledge other than your own. Additionally, many > career enhancing contacts, and mentors can potentially found > especially if one is at a smaller company that lacks the resources for > extensive internal networking. > > http://www.linkedin.com/groups?about=3D&gid=3D56713 > > Website:https://sites.google.com/site/fpgacpldgroup/ could you describe the last technical FPGA related question that your linkedin networking group solved? unless you are able todo that, i see you repeated postings to c.a.f. as complete spam AnttiArticle: 141579
vcar, I suspect this cross-domain path is the "first-word fall-through" path: when you write the first word in the -empty- FIFO, it immediately becomes available on the read port. In such, this path is real. (With two clocks running at 4ns and 3.75ns, the smallest distance between two edges is indeed .250ns=A0in each direction) However, as a designer, if you know that this will never be exercised, you need to declare it as a false path. In your case, you probably should declare false paths between the two clocks (two constraints to cover each direction), which will cover all paths crossing from one clock to the other. - gaelArticle: 141580
Antti.Lukats@googlemail.com wrote: > ok, here some comparison > > S3-area optimize 1447 slices > S3-speed optimize 1482 slices > S6-area optimize 606 slices > S6-speed optimize 557 slices !? > > (only synthesis option changed) > > the design tested is a known 32 bit processor, > well Xilinx is defenetly enhancing the marketing-gate strategy > the SLICE count is more then ever un-comparable Can't that be a result of the 6-input-LUT that S6 now has? Shouldn't make that much of a difference, but it should influence the results at least a little. Doesn't explain why the speed optimized version is smaller than the area-optimized one, though... cu, SeanArticle: 141581
On Jun 28, 3:21=A0am, vcar <hi...@163.com> wrote: > The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks, > say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock > A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now > the problem comes when performing STA. The Timing Analyzer reports > that: > > Slack: =A0-10.394ns (requirement - (data path - clock path skew + > uncertainty)) > =A0 Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMC > (RAM) > =A0 Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 > (FF) > =A0 Requirement: =A0 =A0 =A0 =A0 0.250ns > =A0 Data Path Delay: =A0 =A0 =A02.008ns (Levels of Logic =3D 0) > =A0 Clock Path Skew: =A0 =A0 =A0-8.259ns (3.005 - 11.264) > =A0 Source Clock: =A0 =A0 =A0 =A0trn_clk_c rising at 56.000ns > =A0 Destination Clock: =A0 =A0DDR2_CLK0 rising at 56.250ns > > For certain path crossing the different clock domains, the auto > constraints turned out to be 0.25ns (4ns =96 3.75ns). This is impossible > to achieve. > > What should I do to pass the STA? The timing delay between the rising edges of 250 and 266 MHz is not limited to 250 ps. (You got that false impression from the rounding off to 3.75 ns) In reality, there is no lower limit at all, down to the fractional femtoseconds. That is what makes the control of Full and Empty flags so challenging. Peter Alfke, XilinxArticle: 141582
On Fri, 26 Jun 2009 11:58:36 +0200, Dirk Koch <dirk.koch@cs.fau.de> wrote: >Be careful with Avnet boards, >We bought once Virtex-4 LX Evaluation Boards equipped with >"engineering samples" that have dozens of "undocumented features" >that are quite painful to figure out. >That’s something for early adaptors but not really reliable for >common use. Methinks those interested in Virtex/Spartan 6 NOW _do_ qualify as early adaptors :-) regards, GerhardArticle: 141583
On 28 Jun., 17:32, Sean Durkin <news_MO...@tuxroot.de> wrote: > > S6-area optimize =A0 =A0 606 =A0slices > > S6-speed optimize =A0557 =A0slices !? Doesn't explain why the speed optimized > version is smaller than the area-optimized one, though... Slice numbers are meaningless. 2 LUTs might end up in the same slice or in two different slices during placement/retiming, etc. I might as well be that the area optimized version has less LUTs but they are placed in more slices. As soon as you add more logic to the device the packing will get denser. Kolja SulimmaArticle: 141584
On Jun 28, 11:27=A0pm, Kolja <ksuli...@googlemail.com> wrote: > On 28 Jun., 17:32, Sean Durkin <news_MO...@tuxroot.de> wrote: > > > > S6-area optimize =A0 =A0 606 =A0slices > > > S6-speed optimize =A0557 =A0slices !? > > =A0Doesn't explain why the speed optimized > > > version is smaller than the area-optimized one, though... > > Slice numbers are meaningless. 2 LUTs might end up in the same slice > or in two different slices during placement/retiming, etc. I might as > well > be that the area optimized version has less LUTs but they are placed > in more slices. > As soon as you add more logic to the device the packing will get > denser. > > Kolja Sulimma yes, it doesnt, that was the point, with the new Slices in S6 it is really just marketing gates how it is calculated the equivalent luts (lut4) and of course the slice packing is another story still, in both cases the chip was mostly empty, so it gives some very dumb comparison of what to expect, sure the picture can be different for different design well at least its clear the s3-s6 slice ration is more then just 2 because of wider lut AnttiArticle: 141585
On Sun, 28 Jun 2009 06:42:25 -0700 (PDT), "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com> wrote: |On Jun 28, 3:42 pm, CMOS <manusha1...@gmail.com> wrote: |> hi, |> im plannining to buy a vertex 2 based FPGA board. this is the link. |> |> http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,453&Prod... |> |> does this board worthy for the price of $299? |> |> CMOS | |absolutly, if you get it for $299! | |too bad Xilinx is no longer supporting Virtex-II with their ISE | |ISE 10.1 is the last version that offered V-II support, | |Antti |========== $299 is the acedemic pricing. jamesArticle: 141586
Peter, I suspect the OP actually constrained his clocks in ns, rounding 266Mhz to 3.75ns. That would explain why the STA calculates a 250ps distance (which is correct for 3.75ns and 4ns clocks). If not, this would show a bug in STA since the distance (i.e. "Requirement") between the clocks should then be 0 (after rounding). The issue though lies in declaring these clocks as unrelated, typically with false paths. - gaelArticle: 141587
There is the details information about my design for your better understanding. The async FIFO is common FIFO, not the first-word fall-through FIFO. The Clock A and Clock B are generated by one clock source but from different PLL/DCM. So ISE will auto relate the two clocks as related clocks. All the signals in my design crossing clock A and clock B are passing through async FIFO like the one I listed (addr_cntrl_fifo_inst). Since there is async FIFO which will handle the async clock domain problem, I think my design should have two unrelated clocks, not the related clocks. And all I need to do is to add false path on the crossing paths between clock A & clock B. Am I right?Article: 141588
On Jun 27, 8:39=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > I want to expand unsigned 4*4 module to signed 16*16 module and cannot > find any references. > > Who knows it please give me a help. > > Thank you. > > Weng To use a multiplier module, you must consider the product output from this module to be a partial product which is added to the other partial products to form the complete product. To do a 16x16 multiply using 4x4 multiplier modules will require 16 of these modules. Consider each 16 bit number to be composed of a3*2**12 + a2*2**8 + a1*2**4 + a0 and b3*2**12 + b2*2**8 + b1*2**4 + b0 Your partial products will be a0*b0 + a0*b1*2**4 + a1*b0*2**4 + a1*b1*2**8 + ... I think you can see where this is going. RickArticle: 141589
Sudhir It's a matter of luck which works out cheaper for a given project. Some designs will have a better fit in an Altera and some conversely Xilinx. Pricing will also vary a lot if it's a "volume" project. On the xilinx front it would also be worth considering the Spartan-3A or Spartan-3A DSP. If your manufacturing doesn't start for 6 months or so Spartan-6 will be a good option as well. Not to leave them out Altera will no doubt be offering some competition to Spartan-6. You can try a lot of these device out for fit in the fre versions of ISE and Quartus respectively. John Adair Enterpoint Ltd.- Home of Craignell. The DIL FPGA Solution. On 27 June, 13:39, Sudhir Singh <Sudhir.Si...@email.com> wrote: > Hi Folks, > I am currently in the process for selecting an FPGA for one of my > projects. I have always used Xilinx FPGAs but now am considering using > Altera. The Altera Cyclone III FPGAs looks like a very cost effective > device but I have no idea how well it compares performance wise (will > be used for DSP application) to a Spartan3E. > I would be very grateful if someone would be able to provide me few > pros and cons of Cyclone III. > > Thanks > SudhirArticle: 141590
On Wed, 24 Jun 2009 10:45:55 +0100, Jonathan Bromley wrote: >I've encountered what seems to me > to be a bug in XST For anyone reading this thread in the future, please note my correction... see the thread Dual-port RAM synthesis - AN APOLOGY to Xilinx starting 28 June 2009. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141591
On Jun 28, 10:34=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > On Jun 28, 3:21=A0am, vcar <hi...@163.com> wrote: > > > The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks, > > say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock > > A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now > > the problem comes when performing STA. The Timing Analyzer reports > > that: > > > Slack: =A0-10.394ns (requirement - (data path - clock path skew + > > uncertainty)) > > =A0 Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAM= C > > (RAM) > > =A0 Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_2= 3 > > (FF) > > =A0 Requirement: =A0 =A0 =A0 =A0 0.250ns > > =A0 Data Path Delay: =A0 =A0 =A02.008ns (Levels of Logic =3D 0) > > =A0 Clock Path Skew: =A0 =A0 =A0-8.259ns (3.005 - 11.264) > > =A0 Source Clock: =A0 =A0 =A0 =A0trn_clk_c rising at 56.000ns > > =A0 Destination Clock: =A0 =A0DDR2_CLK0 rising at 56.250ns > > > For certain path crossing the different clock domains, the auto > > constraints turned out to be 0.25ns (4ns =96 3.75ns). This is impossibl= e > > to achieve. > > > What should I do to pass the STA? > > The timing delay between the rising edges of 250 and 266 MHz is not > limited to 250 ps. (You got that false impression from the rounding > off to 3.75 ns) In reality, there is no lower limit at all, down to > the fractional femtoseconds. That is what makes the control of Full > and Empty flags so challenging. > Peter Alfke, Xilinx Hi Peter, challenging does not mean "undoable" for Xilinx I hope? because in one large project, there is again a showstopper and it is now because of xilinx coregen FIFO flags do not seem to work properly unfortunatly adding chipscope to the FPGA design makes the MPMC2 DDR2 memory to fail so the system debug is not possible. Simulation the full design is also not possible the client does not have centuries to wait for simulation results. is it OK, to expect that ISE 10.1 SP3 coregen FIFO's work? or do they all work just under ideal case scenario and actually fail in each and every real design? those fifos and the debugging isnt my task in that project i was just asked to help out with DEBUGGING the coregen FIFO's but we have hard time with that AnttiArticle: 141592
On Sun, 28 Jun 2009 19:48:33 -0700 (PDT), vcar <hitsx@163.com> wrote: >Since there is async FIFO which will handle the async clock domain >problem, I think my design should have two unrelated clocks, not the >related clocks. And all I need to do is to add false path on the >crossing paths between clock A & clock B. Am I right? I think so. If you tell the STA tool that the two clocks are unrelated (different clock groups) then it should automatically cut all paths between the two clock domains; there should be no need to set false paths. You DO need false paths if the two clocks really are related, so that some paths need to be timed, but your FIFO (or whatever) removes the need for STA on certain paths between the two clock domains. Which STA tool are you using? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 141593
Hi, Specvially if it is used for learning purposes, you will find it VERY useful and instructive. Good quality audio, video, networking, 2 PowerPCs, DDR module... quite a lof fun! If you can only get the industrial pricing, I'd recommend you look for something V4, V5 or even better, V6 based. As well, if this is going top be used in a new product, V2Pro is maybe not the best thing you can find nowadays, there are way better other offerings in the market, not only from Xilinx, but from Altera, Lattice, etc. -- Jaime Andres Aranguren C. SanJaaC Electronics Soluciones en DSP www.sanjaac.com "james" <george@washington.edu> escribió en el mensaje news:22pf4551mmkl7b7oemjotrpsv9cr0imhas@4ax.com... > On Sun, 28 Jun 2009 06:42:25 -0700 (PDT), > "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com> wrote: > > |On Jun 28, 3:42 pm, CMOS <manusha1...@gmail.com> wrote: > |> hi, > |> im plannining to buy a vertex 2 based FPGA board. this is the link. > |> > |> > http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,453&Prod... > |> > |> does this board worthy for the price of $299? > |> > |> CMOS > | > |absolutly, if you get it for $299! > | > |too bad Xilinx is no longer supporting Virtex-II with their ISE > | > |ISE 10.1 is the last version that offered V-II support, > | > |Antti > |========== > > $299 is the acedemic pricing. > > jamesArticle: 141594
Hi, Also, you can better compare C3 to more "modern" offerings from Xilinx, like S3A(N) or S3A-DSP. -- Jaime Andres Aranguren C. SanJaaC Electronics Soluciones en DSP www.sanjaac.com <Antti.Lukats@googlemail.com> escribió en el mensaje news:a30100b2-fd3c-421f-af7c-8c969316c04c@x5g2000yqk.googlegroups.com... On Jun 27, 3:39 pm, Sudhir Singh <Sudhir.Si...@email.com> wrote: > Hi Folks, > I am currently in the process for selecting an FPGA for one of my > projects. I have always used Xilinx FPGAs but now am considering using > Altera. The Altera Cyclone III FPGAs looks like a very cost effective > device but I have no idea how well it compares performance wise (will > be used for DSP application) to a Spartan3E. > I would be very grateful if someone would be able to provide me few > pros and cons of Cyclone III. > > Thanks > Sudhir it is matter of taste and preferences but if you compara S3E and C-III i see no reasons not to prefer C-III but as said its a question of taste, or possible corporate policy I would recommend C-III over S3E but my most argument is SPI multiboot capability C-III has it, S3E doesnt of course the amount of BRAM too smallest device CIII has 46 compared to 8K in S3E AnttiArticle: 141595
Hi Guys, Thanks for your replies. John, its interesting that you suggested Spartan-3A DSP and Spartan-6 coz I had enquired with a distributor about these two devices just today. Hopefully Spartan-3A DSP will have a good pricing. We have to have the boards fabricated in 4 months time so Spartan-6 may be no-goer at this stage. I didn't realise that CIII's LUTs can not be configured as distributed memory. Cheers SudhirArticle: 141596
On Jun 28, 5:56=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote: > It will depend on the configuration of the din and dout ports to how many > block rams coregen will use. Have a look at the V5 libraries guide to see > how a bram can be configured. > > Jon It appears that coregen counts the block rams in Virtex 4 block ram sizes (so it shows double what it really is for a Virtex 5). The .xrpt output file lists XST_RAMS as 4 as expected. I will verify in par but I believe this is the source of my confusion. JoeArticle: 141597
On Jun 28, 4:45=A0pm, james <geo...@washington.edu> wrote: > On Sun, 28 Jun 2009 06:42:25 -0700 (PDT), > > "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > > |On Jun 28, 3:42=A0pm, CMOS <manusha1...@gmail.com> wrote: > |> hi, > |> im plannining to buy a vertex 2 based FPGA board. this is the link. > |> > |>http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,453&Prod= ... > |> > |> does this board worthy for the price of $299? > |> > |> CMOS > | > |absolutly, if you get it for $299! > | > |too bad Xilinx is no longer supporting Virtex-II with their ISE > | > |ISE 10.1 is the last version that offered V-II support, > | > |Antti > |=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > $299 is the acedemic pricing. > > james I really wish more companies didn't specifically target "academic", and would offer a more broad "non-industrial" price. I'm not in college anymore, but I still try to keep my skills honed at home - thus, I don't have a student ID, but I still consider myself to be a "student".Article: 141598
On Jun 28, 10:52=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Jun 28, 5:09=A0pm, cpld-fpga-asic <cpld.fpga.a...@gmail.com> wrote: > > > > > Group for People Involved In the Design and Verification of FPGA's, > > other Programmable Logic , and CPLD's to Exchange Idea's and > > Techniques. You should have FPGA / CPLD Design / Verification on your > > Profile. (The focus is more on FPGA/CPLD in the product as opposed to > > FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > > and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > > Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > > Synopsys, Aldec, NI, Altium, and Many Others. > > > Networking on LinkedIn can be a way to get technical questions > > answered. It can also be a way to meet contacts with expertise in > > other domains of knowledge other than your own. Additionally, many > > career enhancing contacts, and mentors can potentially found > > especially if one is at a smaller company that lacks the resources for > > extensive internal networking. > > >http://www.linkedin.com/groups?about=3D&gid=3D56713 > > > Website:https://sites.google.com/site/fpgacpldgroup/ > > could you describe the last technical FPGA related question > that your linkedin networking group solved? > > unless you are able todo that, i see you repeated postings > to c.a.f. as complete spam > > Antti Hi, I am one of the moderators at this group and I must be honest about it. It is not a very technically oriented group. I have tried to make some technically oriented posts there with few responses. This did not seem to stimulate much in the way of subsequent new topics either. I have also made an effort to separate the technical content from the recruiting content and gotten feedback that the recruiters are the ones paying the way for LinkedIn and cutting them out would be a mistake. So I have given up on this group as well as other FPGA related groups at LinkedIn. I have not removed myself from membership, but I can't say I recommend them unless you wish to use it for employment or self promotion. RickArticle: 141599
On Jun 29, 10:35=A0am, radarman <jsham...@gmail.com> wrote: > On Jun 28, 4:45=A0pm, james <geo...@washington.edu> wrote: > > > > > On Sun, 28 Jun 2009 06:42:25 -0700 (PDT), > > > "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > > > |On Jun 28, 3:42=A0pm, CMOS <manusha1...@gmail.com> wrote: > > |> hi, > > |> im plannining to buy a vertex 2 based FPGA board. this is the link. > > |> > > |>http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,453&Pr= od... > > |> > > |> does this board worthy for the price of $299? > > |> > > |> CMOS > > | > > |absolutly, if you get it for $299! > > | > > |too bad Xilinx is no longer supporting Virtex-II with their ISE > > | > > |ISE 10.1 is the last version that offered V-II support, > > | > > |Antti > > |=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > $299 is the acedemic pricing. > > > james > > I really wish more companies didn't specifically target "academic", > and would offer a more broad "non-industrial" price. I'm not in > college anymore, but I still try to keep my skills honed at home - > thus, I don't have a student ID, but I still consider myself to be a > "student". My previous employer had an "industry discount" which applied to pretty much anyone non-academic. The reason was that academic institutions tended to require more product support. So in effect the educational institutions were the only ones paying full price. Of course our products were esoteric enough at the time that we didn't expect the academic users to design us in when they left school... Regards, Gabor
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