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"Brian Drummond" <brian_drummond@btconnect.com> wrote in message
news:6fe3d5pmrusq6cgp4s2vi2ct4sqah2jto8@4ax.com...
> On Sun, 11 Oct 2009 03:43:14 -0500, "Jon Slaughter"
> <Jon_Slaughter@Hotmail.com>
> wrote:
>
>>I'd like to get started in writing some simple fpga applications(LED
>>blinker, etc...).
>>
>>I would like to use a C++ based design. I see that SystemC is C++ based
>>and
>>is free but I'm unsure how all the different steps work.
>
> If you have $50k or so for a SystemC toolchain, consider it; for a
> reliable tool
> flow at price:free, stick with VHDL (or Verilog. The language wars rage,
> and
> basically reduce to: some prefer Verilog because it's more like C; I
> strongly
> prefer VHDL because it's more like Pascal.)
>
>>Do I simply write code in my prefered language(VHDL, Verilog, SystemC,
>>etc...) and use the appropriate tool to "compile" it then bring that into
>>an
>>appropriate program to create a hex dump for sending to the fpga(or send
>>directly from the program)?
>
> Not quite.
>
>>I have some proASIC's I brought a while back that I would like to use. The
>>libero IDE just crashes on my comp so I can't use it.
>
> The tools are probably more important than the chips, at least for
> learning.
> When you need the ultimate performance, or the last cent on the BOM, then
> worry
> about the chip.
>
> Xilinx Webpack on Linux or Windows (my choice) or Altera Quartus (Windows
> only
> for the free Web edition) are the way to go. (Others may me incomplete; no
> simulator? or simply not work...)
>
>>Can someone give me very simple and straight forward process for how one
>>goes about getting code to machine?
>>
>>For example, with microchip pics:
>>
>>1. Write code
>
> Ditto but the code looks different.
> e.g. for a LED blinker:
> (1) identify a clock input to your FPGA (from the board's documentation
> e.g. a 50MHz crystal oscillator, and a LED for output.
> (2) write a synchronous divide by 50M counter in VHDL; see "counter" and
> "clocked process" in the synthesis style guide supplied with the tools),
> and
> connect the clock and counter MSB(*) to signals named "Clock" and "LED"
> (3) write a constraint file (.ucf for Xilinx) which connects "Clock" and
> "LED"
> to the appropriate FPGA pins, and sets the I/O standards, e.g. LED drive
> strength. Also tell it your clock rate (see "timing constraints").
> Stage 2 "compile" tools will meet that speed target, or tell you why it
> can't.
>
> (*) for equal on/off times you want a /25M counter followed by a /2 stage
>
> 1.5 Simulate.
>
> For a LED blinker you don't want to simulate 1 second...
> Simulation is slow. So make the counter division ratio a constant, and
> change it
> between 50M for operation, and (say) 50 for simulation. More generally;
> think
> about testability; i.e. how to test in reasonable time.
>
> Write a testbench to supply a clock. (The tools have templates for this)
> For a
> LED flasher I wouldn't bother writing a tester for the output signal; just
> watch
> it toggling in the wave window.
>
>
>>2. Compile code to binary using MPLab or other supported IDE.
>
> Synthesize; fix any synth errors.
> Back end tools; (Translate/Map/Place&Route for Xilinx); fix any errors.
> (e.g. rewrite for faster logic if it can't meet your speed target.
> Unlikely at
> 50MHz; probable at 200MHz)
>
> Generate bitfile.
>
>>(2.5. Simulate if necessary)
>
> Rarely if ever do you need to simulate after Stage 2. It can OCCASIONALLY
> be
> useful for identifying missing timing constraints, or chasing synth tool
> bugs.
> But it's MUCH slower than "behavioural simulation" on the source.
>
>>3. Program chip using a programmer(or directly from MPLab)
>
> Depends on the board.
> (1) Program ("configure") via JTAG to chip
> (2) Program FLASH memory, maybe via JTAG, and configure from that
> (3) load bitfile into CompactFlash card and transfer that to socket on
> board.
> (4) etc. Some cards are configurable across the PCI bus.
>
>>(4. Debug)
> Simulate at 1.5; there may be board level issues to debug, but not many.
>
>>Right now I don't have a programmer but if it's simply done through JTAG
>>and
>>any appropriate JTAG interface can do it then it shouldn't be a problem.
>>I'll just program a pic to dump the data to the fpga? (similar to
>>programming a pic from the pc, for example.)
>
> USB to JTAG cable is common. (From Xilinx for a price. Other versions from
> other
> people for less. Antti and others will know far more on the specifics)
>
>>Main thing right now is that I just need to get coding... wether it's
>>SystemC or not... But I would like to be able to code independently of the
>>fpga so I don't lock myself into one(at this point at least).
>
> Download Webpack/Quartus and get going.
>
> The constraint file will be device-specific, but that's all.
> Pure VHDL is pretty much portable, barring tool bugs.
> (Vendor specific models, e.g. for DSP blocks, RAM blocks, PowerPCs, clock
> PLLs
> are a different matter)
>
> You can get 90% done before deciding on the hardware...
>
> Boards: look at www.enterpoint.co.uk among others.
>
Thanks, You cleared up a few of the things I was vague on. But I'm still a
bit vague as you say the tools such as quartus is device independent? This
means I can use it for non altera products?
As I said, I brought some proASIC3's a while back and would like to use them
for simple things to learn fpga. The libero IDE simply crashes in XP and
complains of a license problem in vista(didn't do this in 8.5 but I recently
upgraded and now it won't work... trying to update the license file if they
ever send it).
In any case if I can get 90% done without the hardware then I guess I should
get started.
Actually my end goal for this is to write a parallel LED driver frontend.
Basically deals with the PWM and serial communications between the drivers
and uC. Since each driver drives a matrix it requires a relatively high
refresh rate(100*num rows) which the uC cannot communicate with all the
drivers(since it would have to do so sequentially(or approximately at
least). With the fpga I figure I can parallel all the devices, handle the
PWM quite easily(just basically a compare), and decode some serial comm from
the uC. I think it shouldn't be a problem for the fpga.
Also, Their is free software for the SystemC that you can "Synthesize" code.
I'm not sure how far it goes though.
http://www.systemc.org/downloads/standards/
I prefer to program in C++ since I have been programming in C/C++/C# for
many years. While my simple applications do not require oop it's always nice
to have when things get more complex.
Anyways, thanks for the help...
Article: 143426
I got the problem while receiving the value of "count" (i.e. of
integer type with value positive as well as negative) in MICROBLAZE
that was send from custom IP named as encoder module using "User
Logic Software Register" IPIF. Encoder module counts the value of
encoder pulses ranges from -5000 to +5000.
I assigned value of "count" to IP2Bus_Data by converting it to
std_logic_vector type and receive this value in microblaze software
application using variable "Data_receive" of int type. and
"Data_received" was displayed into Hyper Terminal But data received
was not as expecting mainly the negative numbers.....so how this
problem is resolved to get exact data, positive as well as negative.
Can i receive the data in Microblaze application in std_logic_vector
form?? i mean std_logic_vector equivalent form....
OR is there any easier method of transferring negative data ...??
Another problem is...... i found SIGNED(N downto 0) is same as
std_logic_vector except it represents +ve as well as -ve
numbers....But it didn't work in my program...why??
my code written in "user_logic".vhd template is given below.....
------------------------------------------------------------------------------------------------------------------------------
signal cnt: integer range -5000 to 5000:=0;
my_uut1:process(channel_A) is
begin
if(channel_A 'event and channel_A='1') then
direction<= '1' and channel_B;
end if;
end process;
my_uut2:process(channel_A) is
begin
if(channel_A 'event and channel_A='1') then
if(direction='0') then
cnt<=cnt+1;
else
cnt<=cnt-1;
end if;
end if;
end process;
IP2Bus_Data(0 to 15) <= (others=>'0');
IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16);
-----------------------------------------------------------------------------------------------------------------------------
SOFTWARE APPLICATION IN MICROBLAZE
Xint DataRead;
encoder_module_p = (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR;
XASSERT_NONVOID(encoder_module_p != XNULL);
encoder_module = (Xuint32 *)encoder_module_p;
while(1){
DataRead = ENCODER_MODULE_mReadSlaveReg0(encoder_module, 0);
xil_printf("Received data: %d\r\n", DataRead);
}
----------------------------------------------------------------------------------------------------------------------------------------
any suggestion is greatly appreciated!!
Article: 143427Hello Monurlu, Do you use xilkernel ? I experienced problems with it in past projects. The fact is it loses events sometimes. Your problem can also be related to the kind of interrupt generated by your IP. We discovered that edge-triggred interrupts are not managed properly. Level-triggered interrupts should be prefered. Hope this help... Manu monurlu a écrit : > Hi, > Xilinx EDK 9.2i. A custom ip generates interrupts to Microblaze > system. Another custom ip generates periodic timer interrupts. > Interrupt controller misses no interrupt from the timer, but fails to > capture about 10 percent of the interrupts from other custom ip. I > placed a counter at the point where the interrupt signal is sent to > processor to make sure that it actualy happens. Counter perfectly > scores but I am not able to receive 10% of the interrupts in processor > side. I am beginning to think that xps interrupt controller has a bug. > But then how come it captures all timer interrupts? > I checked if the interrupt signal goes back to low after it is raised, > and has no problem there. > It is fairly slow compared to processor plb bus clock too. I also > switched priorities of two interrupts with no effect. > Has anyone seen such a "funny" behavior with xps interrupt controller? > > Thanks for reading this.Article: 143428
For the Multi-FPGA boards, checkout: www.dinigroup.com and I belief Synopsys has software called Certify that will partition your design for you. Have fun.Article: 143429
Hi,
I'm using the ML403 board for the interrupt-based system. In this system,
floating point operations in interrupt handler are required and APU is
employed to accelerate the single precision floating point operation. The
software is running with the standalone BSP on the PPC. The snippet is
shown below:
// global variables
static float a=1.0F;
static float b=2.0F;
void TimerCounterHandler(void *CallBackRef, Xuint8 TmrCtrNumber)
{
a += b;
}
It seems that PPC is blocked when timer interrupt handler
“TimerCounterHandler†is executed. Any advice on how to resolve the
problem.
Best Regards,
Max
Article: 143430First of all check what is available for those boards. Setup your development system and compile the supplied demo configuration. If this does not work, wait or chose another board. Also check what is supplied in the demos. Are these VHDL or Verilog sources or only some macros you can add to your design or not. Can you live with that? You will find that a little older board is the better choice because there is more available while the chip is not mature yet. Being one of the early adopters is easily going to be a hard job. Even for a beginner. For Xilinx I'd recommend a Spartan 3E board. A friend and I just targeting the Spartan 3A Xtreme DSP board from Avnet. But this is more expensive and still a little poor supported. Looks like Xilinx learned from this and does a better job with their Spartan-6 board. You probably find an Altera alternative either. I am not familiar with Altera boards. Maybe someone else has a recommendation. And again, first try to do some small changes to the original design like changing polarity of LEDs or something similar. If you cannot get this work you are getting in hassle you cannot solve as a beginner. You can find lots of CPUs in the web. They are powerful enough for such a system. Look at www.opencores.org.Article: 143431
As an additional question, what do you recommend as literature for starting out on FPGA design ? Regards, JurgenArticle: 143432
Jurgen Defurne <jurgen.defurne@telenet.be> wrote: > As an additional question, what do you recommend as literature for > starting out on FPGA design ? www.google.com? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143433
Antti.Lukats@googlemail.com wrote: > On Oct 7, 4:45 pm, Thomas Rudloff <thomasREMOVE_rudloffREM...@gmx.net> > wrote: >> qamrul wrote: >>> Hi All, >>> I need to provide 8 clock outs shifted by 45 degree, >>> clk_0 -> 0 degree phase shift >>> clk_1 -> 45 degree phase shift >>> clk_1 -> 90 degree phase shift >>> clk_1 -> 135 degree phase shift >>> clk_1 -> 180 degree phase shift >>> clk_1 -> 225 degree phase shift >>> clk_1 -> 270 degree phase shift >>> clk_1 -> 315 degree phase shift >>> clk_1 -> 360 degree phase shift >>> Is it at all possible? >>> Thanks in advance for your feed back. >>> Qamrul >> As discussed you can interleave two DCMs. Now you can tune the delay of >> the second one. On a Spartan3 you have 256 steps for a period. >> Setting delay to 32 should give you 1/8 period delay. >> I read somewhere about a resolution in the range of 50ps IIRC. >> That's well above the 1064MHz discussed in this thread. >> >> On later Spartan3 families you have more effort to calculate the delay. >> Maybe the software assists you. You have RTFM on DCMs. >> >> Regards >> Thomas > > Thomas > > its no issue to have 2 DCMs interleaved > they will have proper 8 phases too, thats fine > but you need to have those 8 clocks to some flip flops > and this route will destroy some of the timing > unless you route it fully in manual mode using > DIRT > constraints. > its not the issue of having 8 phases of clock > on DCM outs, that no problem > Oh, I see. I saw some limitations when I tried to use the four phases plus the two 2x phases as global clocks. Can the chip be partitioned to have all eight clocks on GBUFs? Another solution could be to work with four inverted clocks if the added skew is acceptable. OTOH, one can double the clock and work with four phases. Should be the better approach. Regards ThomasArticle: 143434
"Jon Slaughter" <Jon_Slaughter@Hotmail.com> wrote:
>
>
>
>Thanks, You cleared up a few of the things I was vague on. But I'm still a
>bit vague as you say the tools such as quartus is device independent? This
>means I can use it for non altera products?
>
>
>In any case if I can get 90% done without the hardware then I guess I should
>get started.
>
>Actually my end goal for this is to write a parallel LED driver frontend.
>Basically deals with the PWM and serial communications between the drivers
>and uC. Since each driver drives a matrix it requires a relatively high
>refresh rate(100*num rows) which the uC cannot communicate with all the
>drivers(since it would have to do so sequentially(or approximately at
>least). With the fpga I figure I can parallel all the devices, handle the
>PWM quite easily(just basically a compare), and decode some serial comm from
>the uC. I think it shouldn't be a problem for the fpga.
IMHO you should step a bit further into the real world. The main
question you should ask yourself is: how much time can I to spend on
this project?
You could cut the corners and use schematic entry and use 74***
replacements or go all the way and learn VHDL (IMHO VHDL is more like
a real language than Verilog which just looks like netlist).
And there is more to it than just creating the logic. You'll have to
understand how constraints work to specify the timing.
Either way, your project seems perfect for the first FPGA design.
Almost any device will do. So choose a supplier with the lowest price,
free software and devices in a package you can put on a board and get
on with it!
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143435On Sun, 11 Oct 2009 07:50:29 -0500, "Jon Slaughter" <Jon_Slaughter@Hotmail.com> wrote: > >Thanks, You cleared up a few of the things I was vague on. But I'm still a >bit vague as you say the tools such as quartus is device independent? This >means I can use it for non altera products? I *hope* I didn't say that! Quartus is Altera-specific; Webpack is Xilinx-specific, etc. But pure VHDL code you write and simulate with one toolchain (say, you like the simulator) should be device-independent, and re-synthesise for another vendor's device (in that vendor's tools!) with very little difficulty. >As I said, I brought some proASIC3's a while back and would like to use them >for simple things to learn fpga. The libero IDE simply crashes in XP and >complains of a license problem in vista(didn't do this in 8.5 but I recently >upgraded and now it won't work... trying to update the license file if they >ever send it). If you can't develop in Libero you can't use those FPGAs. But you may be able to develop in other tools, and then beg a little time on a machine that DOES run Libero. Or for $50-100 get another hardware platform. How much is your time worth? - BrianArticle: 143436
Hi, Here is a suggested methodology, based on my extensive experience with FPGA prototyping... (1) Design conversion There are several types of ASIC elements that are not compatible with FPGA prototyping: (1.1) Memories ASIC designs contains foundry-specific memory instances. For FPGA prototyping, these should be replaced by FPGA friendly models. The best solution is to rely on the ability of synthesis tool to synthesize memories. In many cases, the simulation model from the memory vendor will work fine. If not, you need to write your own functional model. (1.2) DesignWare As mentioned by other posters, both Synopsys (Synplify and Certify) and Mentor (Precision) have a built-in DW library that contains basic DW IPs optimized for FPGA implementation. For unsupported DW IPs, you will need to supply synthesizable model. Here again, simulation models will mostly work fine, but are likely to result in poor performance. You can always write you own models when required. (1.3) Instantiated library cells In some cases, your ASIC may contain instantiated cells from the foundry-specific library. These can be handled automatically by Synopsys Synplify/Certify by simply providing the .lib file(s) to the synthesis tool. The alternate option is to supply synthesizable models. Often, the simulation library will do the trick for basic cells. (1.4) Other hard IPs (analog, serdes, pll, etc) For all other hard IPs (i.e. w/o a synthesizable model) you will need to either partition it out of FPGAs (see partitioning topic below), or write a FPGA friendly model. A good example is PLLs, which are available on FPGAs, yet most likely with a different interface than your ASIC one. (1.5) Gated-clock and Generated-clock FPGAs have a limited number of clock trees. Consequently, gated and generated clocks must be transformed to "clock-enables". Synopsys (Synplify and Certify) supports automatic conversion of gated and generated clocks. Last I checked, Mentor Precision supports gated- clock conversion but not generated-clock conversion (though rumored to be coming). Important note: gated/generated clock conversion is a global optimization that requires the entire design to be provided at once to the synthesis tool. Indeed, if the gated cell (the AND gate for example) is located in a different partition (i.e. a distinct synthesis project) than the driven FFs, then conversion cannot be performed. (1.6) Latches Latches are supported by most FPGA vendors, though unequally. Watch out vendors that implement latches as a feedback mux, as these typically incur a noticeable clock skew. Additionally, and of critical importance, no FPGA tools (synthesis or P&R) supports "time- borrowing", and latches are treated as FFs during timing analysis. This can result in both false positive and false negative, in presence of shoot-through (of which time-borrowing is a special case). If you have isolated latches that are always surrounded by rising-edge FFs (either in the FPGA or outside the FPGA), then the default FF modeling is safe (conservative). => A completed conversion should result in successful synthesis to the FPGA target (possibly overflowing the resources of the target device). (2) Partitioning If the ASIC is too big to fit into one FPGA, then you need to partition the logic. This consists in resolving several equations simultaneously: - IOs: each partition should contain less IOs that the number of pins on the target device - resources: each partition should not overflow the resource count for each resource type (LUTs, DFFs, DSP blocks, memories, PLLs, clock trees, etc) - board routability: if you're using an off-the-shelve board (Dini, Synopsys/Hardi, Gidel, etc), you need to ensure that the number of connections between any pairs of FPGAs can be accommodated by the routing tracks on the board. If you plan on building a custom board, this is not an issue. - performance: any path spanning two or more FPGAs will suffer from severe performance degradation due to the IO delays (several ns). If performance matters, one should try to contain critical paths in a single device. Synopsys Certify is the leading tool for FPGA partitioning. Although both Synopsys and Auspy provide automatic partitioning, one most needs to help the tool by manually specifying partition assignments. That's largely due to the fact that partitioning algorithms don't "see" (e.g. understand) your design, which can lead to poor results. At that game, Certify has more powerful features for RTL and source code partitioning, i.e. at the level you're familiar with (Try partitioning synthesized LUTs by hand ...). To my knowledge, Certify is also the only tool that resolves the board routability for you: its reads-in the netlist of the target board, and applies a routing algorithm to map the connections between partitions onto wires on the board. This lets you quickly identify invalid partitions when using off-the-shelve boards. => A valid partitioning should result in successful place and route for each FPGA. (3) Board management You now need handle a few things to map your design to the target board. (3.1) Board creation If you're not using an off-the-shelve board, you'll need to design your own. Taray 7Circuits is a very neat tool that essentially is a "PCB floorplanner". It allows you to quickly (i.e not manually) create your board and automatically handles IO constraints (connectivity, electrical, banking rules). There is a very nice flow with Synopsys Certify to use 7Circuits to design your prototyping board (check Taray's web site) (3.1) Pin assignments This consists in assigning every pin of each FPGA to the adequate logic port, to properly connect the devices together. In other words, this consists in "mapping" (routing) each connection between partitions to a wire on the board. For off-the-shelve boards, both Synopsys Certify and Auspy handle this automatically for you. This saves the horribly tedious and error-prone job of performing pin- assignment for each FPGA (picture a complex board with 4 FPGAs each having 1,000+ pins - good luck handling this by hand looking at the board schematic and your partitioned design). For custom boards, Taray 7Circuits will do the pin assignment for you. (3.2) I/O timing constraints This consists in applying input/output delay constraint to each pin of each FPGA to ensure there are no timing violations for path spanning across FPGAs. There again, both Certify and Auspy use timing-budgeting to automatically generate timing constraints all FPGA pins. That is an essential feature to avoid hidden timing violations on the board that can take weeks or months to be identified (in lieu of a functional bug). => At that point, you should be able to download each bitstream into the board and boot it. (4) Debug methodology Your ASIC is now alive on the FPGA board. But most likely what you see is ... well, functional bugs :~(. Debug such a beast if far from being easy, and you should plan for it in advance: (4.1) Probes One basic debugging method is to send selected signals to FPGA pins for observation with a logic analyzer. Auspy, Certify let you add probes without editing your HDL. I don't know if Precision also supports this (though I would guess it does). (4.2) On-chip debugging This consists in probing signals into FPGA memories and uploading through JTAG. Synopsys Identify leads the pack, followed by SignalTap and ChipScope from Altera and Xilinx, as well as tools from Temento or DAFCA (no experience with these last two). One of the nicest feature of Identify is to display the signal values back in your HDL. That's much more efficient than looking at waveforms. Also, and importantly, it is essential to insert such debugging logic *before* synthesis, in the RTL. That's because FPGA synthesis perform many complex optimizations, and sequential optimizations, can change very subtly the behavior of your FFs (for example, pushing an inverter through a FF). If your debug logic is inserted after synthesis, you could very well end-up chasing false positive (i.e. chasing a non- existent bug). However, if you insert your debug logic in the RTL, this will prevent the synthesis from changing the functional behavior of your FF (because the FF output is now 'observed'). Here, favor tools that can insert debug logic in your HDL without requiring manual edit. Temento and Synopsys both have this feature, and Auspy does not seem to support this. (4.3) Assertions I personally believe that synthesizing assertion into your FPGA prototype is a very powerful methodology, in particular when combined with on-chip debugging. This indeed allows capturing violations in on- chip memories, but can also be used to trigger signal probing to help diagnose the cause of the violation. I don't know which synthesis tools actually support assertion synthesis yet. (5) Additional considerations (5.1) While I would believe the majority of FPGA prototypes to have 2-8 devices, I've heard of prototypes with 50+ -large- devices. (5.2) Advanced partitioning features include pin-multiplexing (to save FPGA pins at the expense of performance), high-speed IO (LVDS/SERDES) support (to save FPGA pins with no performance impact), RTL hierarchy manipulations (to allow for non module-based partitioning, such as datapath slicing), logic replication (to save FPGA pins and board traces), feedthrough elimination (to save FPGA pins), etc (5.3) Emulation systems (EVE, Cadence, Synopsys, Mentor) also map entire ASICs onto FPGAs for the sake of functional debugging. They typically provide an extremely automated flow (much easier than FPGA prototyping) and superior debugging tools (in particular, full observability). However, these systems are *much* more expensive than FPGA prototypes, and provide much lower operating frequencies (< 10 MHz). (6) Conclusions (6.1) For basic prototyping (vanilla RTL with 1 or 2 FPGAs), you can use Mentor Precision or Synopsys Synplify and do partitioning and board management by hand. I would stay away from FPGA vendor synthesis tools who often want to "help the customer" by cleaning-up your design in a way that does not exactly preserve the HDL behavior (not a good idea for ASIC prototyping). (6.2) For complex prototyping, you will have to use dedicated tools. You can either opt for the integrated Synopsys flow (Certify + Identify) or the composite Mentor + Auspy + Temento flow. That's it for now, hope it helps, - gael PS: Despite my best efforts to be exhaustive and objective, I apologize in advance for tools/companies I may have omitted or mis- represented. I welcome their feedback through email: gael (at) gaelpaul (dot) comArticle: 143437
Hi, Please help. I want to enclose the following equation data n/2**j with a lower boundary character pair within Microsoft Office Word 2007. 0 <= i <= low_boundary(n/2**j) ; Thank you. WengArticle: 143438
On Oct 11, 9:16=A0pm, Thomas Rudloff <thomasREMOVE_rudloffREM...@gmx.net> wrote: > Antti.Luk...@googlemail.com wrote: > > On Oct 7, 4:45 pm, Thomas Rudloff <thomasREMOVE_rudloffREM...@gmx.net> > > wrote: > >> qamrul wrote: > >>> Hi All, > >>> I need to provide 8 clock outs shifted by 45 degree, > >>> clk_0 -> 0 degree phase shift > >>> clk_1 -> 45 degree phase shift > >>> clk_1 -> 90 degree phase shift > >>> clk_1 -> 135 degree phase shift > >>> clk_1 -> 180 degree phase shift > >>> clk_1 -> 225 degree phase shift > >>> clk_1 -> 270 degree phase shift > >>> clk_1 -> 315 degree phase shift > >>> clk_1 -> 360 degree phase shift > >>> Is it at all possible? > >>> Thanks in advance for your feed back. > >>> Qamrul > >> As discussed you can interleave two DCMs. Now you can tune the delay o= f > >> the second one. On a Spartan3 you have 256 steps for a period. > >> Setting delay to 32 should give you 1/8 period delay. > >> I read somewhere about a resolution in the range of 50ps IIRC. > >> That's well above the 1064MHz discussed in this thread. > > >> On later Spartan3 families you have more effort to calculate the delay= . > >> Maybe the software assists you. You have RTFM on DCMs. > > >> Regards > >> Thomas > > > Thomas > > > its no issue to have 2 DCMs interleaved > > they will have proper 8 phases too, thats fine > > but you need to have those 8 clocks to some flip flops > > and this route will destroy some of the timing > > unless you route it fully in manual mode using > > DIRT > > constraints. > > its not the issue of having 8 phases of clock > > on DCM outs, that no problem > > Oh, I see. I saw some limitations when I tried to use the four phases > plus the two 2x phases as global clocks. Can the chip be partitioned to > have all eight clocks on GBUFs? Another solution could be to work with > four inverted clocks if the added skew is acceptable. > OTOH, one can double the clock and work with four phases. Should be the > better approach. > > Regards > Thomas Thomas this is all trickery that doesnt solve the problem he does need 8 flip flops to be triggered with "clock precision" of 1064mhz it doesnt work out without extensive use of directed routing (use DIRT constraints) and even then i think its not doable in S3 it doesnt mean his task (in S3) is impossible just that simple 8 clock approuch in S3 is not feasible AnttiArticle: 143439
On Oct 12, 1:33=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sun, 11 Oct 2009 07:50:29 -0500, "Jon Slaughter" <Jon_Slaugh...@Hotmai= l.com> > wrote: > > > > >Thanks, You cleared up a few of the things I was vague on. But I'm still= a > >bit vague as you say the tools such as quartus is device independent? Th= is > >means I can use it for non altera products? > > I *hope* I didn't say that! Quartus is Altera-specific; Webpack is > Xilinx-specific, etc. > > But pure VHDL code you write and simulate with one toolchain (say, you li= ke the > simulator) should be device-independent, and re-synthesise for another ve= ndor's > device (in that vendor's tools!) with very little difficulty. > > >As I said, I brought some proASIC3's a while back and would like to use = them > >for simple things to learn fpga. The libero IDE simply crashes in XP and > >complains of a license problem in vista(didn't do this in 8.5 but I rece= ntly > >upgraded and now it won't work... trying to update the license file if t= hey > >ever send it). > > If you can't develop in Libero you can't use those FPGAs. > But you may be able to develop in other tools, and then beg a little time= on a > machine that DOES run Libero. > > Or for $50-100 get another hardware platform. How much is your time worth= ? > > - Brian Brian, I have seen Libero to crash very very seldom (I have one design that crashes actel fitter) a person who is not able to install Libero, well ability to install and run software is i would say necessary to anyone who wants to work with FPGA's. Actel libero ALL version have worked on more than one PC (XP/Vista) each time i have installed them. hmm.. I havent upgraded to 8.6! could be 8.6 no longer works, unitl 8.5 all versions works for sure AnttiArticle: 143440
Hello all,
I have a module named moduleA, I have a testbench moduleA_tb and
instantiate moduleA_uut inside, and use $sdfannotate ("delay.sdf") to
back annotate the design.
I use ncverilog to run timing simulation, and got below warnings:
ncelab: *W,SDFINF: Instance moduleA not found at scope level <top-
level> <./delay.sdf, line 283422>.
The delay.sdf is gotten from ASIC team, I found the instance names in
it are moduleA.i1.xxx etc. I think I need to change all of them to
moduleA_uut.i1.xxx, then I don't get the SDFINF warning when rerun the
simulation, but thousands of "ncelab: *W,SDFNEP: Unable to annotate to
non-existent path (xxx)" warnings and "Warning! Timing violation"
during simulation.
I'm not very familiar with simulation, am I doing the right thing?
Article: 143441Are the microchip pic's pins current limit? Specifically for the pic24F family. I have all the IO pins going to offboard connectors and I'm wondering what would happen if the connectors were accidently shorted(say a wire fell on them). I believe the pic's have thermal protection so it's a matter of simply saving the individual pins. I can add in some series resistance to limit the current in this application but wondering if they are needed? (it's not prefered though because some of these pins are going to be for general use)Article: 143442
Sorry, wrong group ;/Article: 143443
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:hfm4d5hb053p9j8g38c3nvvepgoseplqlv@4ax.com... > On Sun, 11 Oct 2009 07:50:29 -0500, "Jon Slaughter" > <Jon_Slaughter@Hotmail.com> > wrote: > >> >>Thanks, You cleared up a few of the things I was vague on. But I'm still a >>bit vague as you say the tools such as quartus is device independent? This >>means I can use it for non altera products? > > I *hope* I didn't say that! Quartus is Altera-specific; Webpack is > Xilinx-specific, etc. > > But pure VHDL code you write and simulate with one toolchain (say, you > like the > simulator) should be device-independent, and re-synthesise for another > vendor's > device (in that vendor's tools!) with very little difficulty. > >>As I said, I brought some proASIC3's a while back and would like to use >>them >>for simple things to learn fpga. The libero IDE simply crashes in XP and >>complains of a license problem in vista(didn't do this in 8.5 but I >>recently >>upgraded and now it won't work... trying to update the license file if >>they >>ever send it). > > If you can't develop in Libero you can't use those FPGAs. > But you may be able to develop in other tools, and then beg a little time > on a > machine that DOES run Libero. > > Or for $50-100 get another hardware platform. How much is your time worth? It's worth a lot... hence the reason I don't worry about the cost when I'm learning something new. In any case, I just installed quartus. I've heard some people complaining about it being a bit buggy. But at least it gets to the IDE. Thanks, JonArticle: 143444
On Oct 12, 9:59=A0am, "Jon Slaughter" <Jon_Slaugh...@Hotmail.com> wrote: > "Brian Drummond" <brian_drumm...@btconnect.com> wrote in message > > news:hfm4d5hb053p9j8g38c3nvvepgoseplqlv@4ax.com... > > > > > > > On Sun, 11 Oct 2009 07:50:29 -0500, "Jon Slaughter" > > <Jon_Slaugh...@Hotmail.com> > > wrote: > > >>Thanks, You cleared up a few of the things I was vague on. But I'm stil= l a > >>bit vague as you say the tools such as quartus is device independent? T= his > >>means I can use it for non altera products? > > > I *hope* I didn't say that! Quartus is Altera-specific; Webpack is > > Xilinx-specific, etc. > > > But pure VHDL code you write and simulate with one toolchain (say, you > > like the > > simulator) should be device-independent, and re-synthesise for another > > vendor's > > device (in that vendor's tools!) with very little difficulty. > > >>As I said, I brought some proASIC3's a while back and would like to use > >>them > >>for simple things to learn fpga. The libero IDE simply crashes in XP an= d > >>complains of a license problem in vista(didn't do this in 8.5 but I > >>recently > >>upgraded and now it won't work... trying to update the license file if > >>they > >>ever send it). > > > If you can't develop in Libero you can't use those FPGAs. > > But you may be able to develop in other tools, and then beg a little ti= me > > on a > > machine that DOES run Libero. > > > Or for $50-100 get another hardware platform. How much is your time wor= th? > > It's worth a lot... hence the reason I don't worry about the cost when I'= m > learning something new. > > In any case, I just installed quartus. I've heard some people complaining > about it being a bit buggy. But at least it gets to the IDE. > > Thanks, > Jon- Hide quoted text - > > - Show quoted text - if people complain about Quartus being buggy, you should really get Xilinx tools then you have a big can of bugs, in real nice package honestly, ALL FGPA tools work (=3D=3D are useable with some effort), but you have to spend some of your valuable time with them AnttiArticle: 143445
hi a first version of the solution is available from its temporary home at my brains download area http://groups.google.com/group/antti-brain/files?hl=en it does allow unmodified PonyProg 2.07c to use Altera USB blaster to program SPI devices, instrucions are in the download archive its very raw version, first FTDI device is assumed to the be the blaster testing is done with U2TOOL in USB blaster mode, programming ATtiny45 succesfully Antti PS I double posted to fpga/embedded as usb blaster users are more likely on fpga side and AVR users more likely on the embedded side, and some may have usb blaster and may want to use ponyprog to program some spi devisesArticle: 143446
rickman wrote: > On Oct 10, 5:51 am, n...@puntnl.niks (Nico Coesel) wrote: >> Joseph Yiu <joseph....@somewhereinarm.com> wrote: >>> rickman wrote: >>>> As others have indicated, it may be easy to implement CPUs in FPGAs, >>>> but they do not run nearly as fast as high end CPUs in fixed silicon. >>>> Martin indicated that if your algorithm is amenable to breaking it >>>> into many processes running in parallel, many processors can be used, >>>> each doing a part of the calculation with the load fairly balanced. >>> Regarding speed, actually you could have better performance by running a >>> CPU in FPGA compared to standard microcontrollers. Flash memory usually >>> have a flash memory of 25MHz to 50MHz, while block RAM in FPGA can be >>> much faster. So you can run a processor at high clock speed on FPGA >>> (e.g. 100MHz) with zero wait state, compared to microcontroller products >>> running at 100MHz with 1 or 2 wait states on silicon. >> That's not true. Most of such microcontrollers have wider flash and >> use pre-fetch and branch prediction buffers (a small smart cache) to >> undo the effects of the slower flash. NXP has been doing this for >> years with the LPC2000 series and has included similar schemes on >> their new LPC1300 en LPC1700 series. > > Yes, but they only get speeds up to roughly 100 MHz. An FPGA CPU with > internal memory can run 200 MHz or faster, depending on the CPU. The > only ARM parts that run much faster than 100 MHz are not using Flash > at that speed or have cache. That's a very mixed-up argument. Microcontrollers aimed at lower speeds run happily from flash (especially with wider buses and some buffering). At higher speeds, you run from RAM or flash with caches. Whereas on an FPGA, you run from RAM or from flash with caches. What's the difference? In either case, you fit your memory buses, bandwidths and caches to suit the desired throughput of the processor. > However, clock speed is not the > determining factor of processor speed, as we all know. Most FPGA CPUs > are rather simple CPUs with simple instruction sets and get lower MIPS > per MHz. The real advantage of a soft CPU is the flexibility you have > to integrate it with peripherals or possibly the fact that you can > eliminate cost by not having a separate CPU. In other cases you can > connect multiple CPUs with high speed interfaces. It all comes down > to the cost and the flexibility, whichever is important to you. > That part is all true. The general rule is that you get more bang for the buck (and for the power) with a hardware CPU - /if/ it does the job you need. Soft CPUs are for flexibility and convenience (if you've got a big FPGA already, the soft CPU is free).Article: 143447
On Oct 12, 10:14=A0am, David Brown <da...@westcontrol.removethisbit.com> wrote: > rickman wrote: > > On Oct 10, 5:51 am, n...@puntnl.niks (Nico Coesel) wrote: > >> Joseph Yiu <joseph....@somewhereinarm.com> wrote: > >>> rickman wrote: > >>>> As others have indicated, it may be easy to implement CPUs in FPGAs, > >>>> but they do not run nearly as fast as high end CPUs in fixed silicon= . > >>>> Martin indicated that if your algorithm is amenable to breaking it > >>>> into many processes running in parallel, many processors can be used= , > >>>> each doing a part of the calculation with the load fairly balanced. > >>> Regarding speed, actually you could have better performance by runnin= g a > >>> CPU in FPGA compared to standard microcontrollers. Flash memory usual= ly > >>> have a flash memory of 25MHz to 50MHz, while block RAM in FPGA can be > >>> much faster. So you can run a processor at high clock speed on FPGA > >>> (e.g. 100MHz) with zero wait state, compared to microcontroller produ= cts > >>> running at 100MHz with 1 or 2 wait states on silicon. > >> That's not true. Most of such microcontrollers have wider flash and > >> use pre-fetch and branch prediction buffers (a small smart cache) to > >> undo the effects of the slower flash. NXP has been doing this for > >> years with the LPC2000 series and has included similar schemes on > >> their new LPC1300 en LPC1700 series. > > > Yes, but they only get speeds up to roughly 100 MHz. =A0An FPGA CPU wit= h > > internal memory can run 200 MHz or faster, depending on the CPU. =A0The > > only ARM parts that run much faster than 100 MHz are not using Flash > > at that speed or have cache. > > That's a very mixed-up argument. =A0Microcontrollers aimed at lower speed= s > run happily from flash (especially with wider buses and some buffering). > =A0 At higher speeds, you run from RAM or flash with caches. =A0Whereas o= n > an FPGA, you run from RAM or from flash with caches. =A0What's the > difference? =A0In either case, you fit your memory buses, bandwidths and > caches to suit the desired throughput of the processor. > > > However, clock speed is not the > > determining factor of processor speed, as we all know. =A0Most FPGA CPU= s > > are rather simple CPUs with simple instruction sets and get lower MIPS > > per MHz. =A0The real advantage of a soft CPU is the flexibility you hav= e > > to integrate it with peripherals or possibly the fact that you can > > eliminate cost by not having a separate CPU. =A0In other cases you can > > connect multiple CPUs with high speed interfaces. =A0It all comes down > > to the cost and the flexibility, whichever is important to you. > > That part is all true. > > The general rule is that you get more bang for the buck (and for the > power) with a hardware CPU - /if/ it does the job you need. =A0Soft CPUs > are for flexibility and convenience (if you've got a big FPGA already, > the soft CPU is free).- Hide quoted text - > > - Show quoted text - David, yes/no as usual, right at the higher end, you defenetly get more processor power in dedicated microcontroller than in FPGA (despite Xilinx once tried to explain that Virtex4 outperforms Pentium class processor both on performance AND price) however the border is moving all the time, smallest and chepest FPGA (that i still call FPGA) is A3P060, costs about 3.5$ medium qty, it is just almost too small for soft core, but depending the requirements it may still be possible to actually have an small RISC core inside, the price of the RISC would be rather high (in terms of utilization) say close to 2.5$ but it would outperform the "real risc" it emulates on the clock speed, so you get an superspeed AVR for 2.5$ thats not that bad :) besides my super speed AVR directly boots from sd card into RAM (ok only 512 instruction so its tiny!) in smallest Altera you can have soft cores wich cost in terms of % of resources maybe around < 0.25$ what is BELOW the price you can buy flash mcu's (OTP/ROM mcu can go below 0.2$) the price of 32 bit MCU capable of running uClinux made with FPGA (% FPGA + ext ram) is around 5..10$ at the moment (total price a bit higher as most of the FPGA is empty) so in some cases the MCU-proc solutions are closing up the flash-mcu solutions. AnttiArticle: 143448
Jurgen There are a few things here http://www.enterpoint.co.uk/techitips/techitips.html that may be of interest and help. John Adair Enterpoint Ltd. - Home of Merrick1. The HPC Solution. On 11 Oct, 16:03, Jurgen Defurne <jurgen.defu...@telenet.be> wrote: > As an additional question, what do you recommend as literature for > starting out on FPGA design ? > > Regards, > > JurgenArticle: 143449
hello everyone I have a problem: After downloading a mcs file to a xc18v02 PROM used for a XC2VP2 Xilinx Virtex Pro II Fpga, the whole module lost power and now I count only 2V instead of 2.5 or 3.3 V in the power supply. I am supposed to see what is going wrong, in order to change what has been broken. I have no idea what I should do. Any ideas? --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
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