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On Mar 23, 8:08=A0am, Mawa_fugo <cco...@netscape.net> wrote: > On Mar 21, 4:36=A0pm, Patrick Maupin <pmau...@gmail.com> wrote: > > > > > On Mar 20, 3:17=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > On Mar 20, 2:52=A0am, modimo <g.mod...@gmail.com> wrote: > > > > > On 20 Mar, 04:28, Mawa_fugo <cco...@netscape.net> wrote: > > > > > > On Mar 19, 10:05=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > > > > On Mar 19, 3:55=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > > > > On Mar 19, 2:17=A0pm, John_H <newsgr...@johnhandwork.com> wro= te: > > > > > > > > > On Mar 19, 3:01=A0pm, Mawa_fugo <cco...@netscape.net> wrote= : > > > > > > > > > > Hi all, > > > > > > > > > > There's an instance of BRAM in spartan3 device. =A0I used= coregen with > > > > > > > > > *.coe file to init the data for the memory module > > > > > > > > > > My question, is there anyway to edit the mcs file (we use= flatform > > > > > > > > > flash for config) to change the content of init data ..."= without spend > > > > > > > > > 20 minutes to re-run the whole ISE processes > > > > > > > > > > Thanks, > > > > > > > > > "There's an app for that." > > > > > > > > >http://www.xilinx.com/products/ipcenter/dr_dt_data2mem.htm > > > > > > > > Thanks for the link, I do search around and all route to that= page.. > > > > > > > But I'm not sure I can get anything, > > > > > > > Is there any download-able thing ? > > > > > > > > Thanks > > > > > > > Have you looked in your Xilinx directories for your installed I= SE? > > > > > > > From a random sell sheet: > > > > > > > ISE=99 WebPack FPGA Design Tool Suite > > > > > > =95 Timing driven FPGA hardware implementation tools > > > > > > =95 Design entry, synthesis and verification capabilities > > > > > > =95 Data2MEM =96 application for loading on-chip memory > > > > > > > It looks like it's included standard. > > > > > > Yes, I see that execute file data2mem, look like old day command > > > > > line. =A0Guessing it's just another non-user-friendly Xilnx apps = ;-) > > > > > > Thanks > > > > > Console apps are user-friendly matter of who their friends are ;) > > > > > Some examples should be helpfulhttp://home.mnet-online.de/al/BRAM_B= itstreams.html > > > > > There is also app for updating picoblaze code through jtag that als= o > > > > could be useful after some modifications.http://forums.xilinx.com/x= lnx/board/message?board.id=3DPicoBlaze&messag... > > > > In my app, the data width is 1 bit, with 128k depth, that means I hav= e > > > 8 BRAM16 inst > > > > ---------below is my bmm file > > > > ADDRESS_SPACE mem_module RAMB16 [0x00000000:0x00001FFFF] > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B76/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y12; > > > END_BUS_BLOCK; > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B79/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y14; > > > END_BUS_BLOCK; > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B82/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y13; > > > END_BUS_BLOCK; > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B85/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y15; > > > END_BUS_BLOCK; > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B88/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y17; > > > END_BUS_BLOCK; > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B91/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y18; > > > END_BUS_BLOCK; > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B94/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y19; > > > END_BUS_BLOCK; > > > > BUS_BLOCK > > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B97/RAMB16BWER [0:0] =A0PLACED =3D > > > X2Y16; > > > END_BUS_BLOCK; > > > > END_ADDRESS_BLOCK; > > > > ----below is the command line I try to see if I can extract the data > > > from existing bit file > > > > $ data2mem -bm mybmmfile.bmm -bt existingbitfile.bit > log.txt > > > > -------- But it always gives the below error > > > > ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE > > > 'mem_module'. > > > =A0 =A0 ADDRESS_SPACE was defined as 0x00020000 bytes, but the > > > ADDRESS_RANGE total is 0x00004000 bytes. > > > > ---Then I try to change the address space to > > > > ADDRESS_SPACE mem_module RAMB16 [0x00000000:0x000003FFF], > > > > ---It then gives no error but the log.txt file is just a blank, > > > nothing show up > > > > ---I wonder if this tool can't handle data width with 1 bit wide???? > > > The tool doesn't have a clue. =A0Just lie to it and tell it your RAM is > > 8 bits wide. > > Okie, I can lie it about the address, but how can I "lie" it about the > data ? > > Let me guess, I will have to tell it in byte, by concatenate 8 bits > together ? > > TIA Okie, problem solved, thanks all for your helpArticle: 146601
On Mar 23, 5:17=A0am, Jason Thibodeau <jason.p.thibod...@gmail.com> wrote: > I'm sorry, Kal and Ed, I should have been more specific. > > I know what the gates are, but they are not defined in the code > anywhere. I am figuring I need to include a library where they will be > defined, but I don't know which I should be using, or if any are even > available in the Xilinx flow. > > I import the (verilog) benchmark, instantiate it in my VHDL toplevel, > and when it is synthesized, I have 614 errors since the gates are not > defined. > > I was hoping it would be something as simple as including a library. > > On 03/23/2010 12:47 AM, Muzaffer Kal wrote: > > > > > > > On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > > <ed.mcgetti...@xilinx.com> =A0wrote: > > >> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> > >> wrote: > >>> I'm having a terrible time finding a solution to a library problem. > > >>> I am implementing some IWLS benchmarks on a Spartan3e, and I need som= e > >>> standard cells such as: > > >>> AOI21X1 > >>> AND3X1 > >>> AND2X1 > >>> NAND2X1 > > >>> etc. > > >>> Does anyone have a suggestion? Am I overlooking something simple? > > >>> Thanks in advance. > >>> -- > >>> Jason Thibodeau > > >> The standard cell library should document the function of each these > >> cells. =A0Likely guesses are. > > >> AOI21X1 - 2-Input AND-OR with Inversion on inputs? > >> AND3X1 - 3-Input AND > >> AND2X1 - 2-Input AND > >> NAND2X1 - 2-Input NAND > > >> etc... =3D etc... :-) > > >> Ed McGettigan > > > If we had more info, we can make better guesses. The ports are > > extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which > > is OR-inverted =A0with the third ie y =3D !((a0&a1) | b0). > > One more thing which is again very helpful is to get the simulation > > model of the standard cell library and use it without any timing as > > the behavioral model. Synthesis tools do a pretty decent job of doing > > the mapping. > > -- > Jason Thibodeauwww.jayt.org- Hide quoted text - > > - Show quoted text - It should be as simple as "including a library", but this won't come from Xilinx. You need to get it from the creator of the standard cell library that was used to insert these primitives into the HDL code that you are using. This must exist somewhere or simulation would not be possible. When you work this out and run through synthesis the performance of the design will likely be much better with a flatten design so that the basic primitives can be optimized correctly. Ed McGettigan -- Xilinx Inc.Article: 146602
On 03/23/2010 12:06 PM, Ed McGettigan wrote: > On Mar 23, 5:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com> > wrote: >> I'm sorry, Kal and Ed, I should have been more specific. >> >> I know what the gates are, but they are not defined in the code >> anywhere. I am figuring I need to include a library where they will be >> defined, but I don't know which I should be using, or if any are even >> available in the Xilinx flow. >> >> I import the (verilog) benchmark, instantiate it in my VHDL toplevel, >> and when it is synthesized, I have 614 errors since the gates are not >> defined. >> >> I was hoping it would be something as simple as including a library. >> >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote: >> >> >> >> >> >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan >>> <ed.mcgetti...@xilinx.com> wrote: >> >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> >>>> wrote: >>>>> I'm having a terrible time finding a solution to a library problem. >> >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and I need some >>>>> standard cells such as: >> >>>>> AOI21X1 >>>>> AND3X1 >>>>> AND2X1 >>>>> NAND2X1 >> >>>>> etc. >> >>>>> Does anyone have a suggestion? Am I overlooking something simple? >> >>>>> Thanks in advance. >>>>> -- >>>>> Jason Thibodeau >> >>>> The standard cell library should document the function of each these >>>> cells. Likely guesses are. >> >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs? >>>> AND3X1 - 3-Input AND >>>> AND2X1 - 2-Input AND >>>> NAND2X1 - 2-Input NAND >> >>>> etc... = etc... :-) >> >>>> Ed McGettigan >> >>> If we had more info, we can make better guesses. The ports are >>> extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which >>> is OR-inverted with the third ie y = !((a0&a1) | b0). >>> One more thing which is again very helpful is to get the simulation >>> model of the standard cell library and use it without any timing as >>> the behavioral model. Synthesis tools do a pretty decent job of doing >>> the mapping. >> >> -- >> Jason Thibodeauwww.jayt.org- Hide quoted text - >> >> - Show quoted text - > > It should be as simple as "including a library", but this won't come > from Xilinx. You need to get it from the creator of the standard cell > library that was used to insert these primitives into the HDL code > that you are using. This must exist somewhere or simulation would not > be possible. > > When you work this out and run through synthesis the performance of > the design will likely be much better with a flatten design so that > the basic primitives can be optimized correctly. > > Ed McGettigan > -- > Xilinx Inc. This is the direction in which I just headed. I added the GSCLib_3.0.vhd available from the IWLS benchmark tar file. When I add this to the project, I get an error: ERROR:HDLParsers - Cannot rename dependency database for library "ieee", file is "./xst/ieee/hdpdeps.ref", Temporary database file "./xst/xil_7sDTXM" will remain. System error message is: No such file or directory (I had to edit the pathnames in the error message, but the full pathnames are listed in the actuall error message). I was having this same problem yesterday with a different library. When I remove the GSCLib_3.0.vhd file from the project, it reverts to my previous 600+ errors. Any idea what is happening here? -- Jason ThibodeauArticle: 146603
On Mar 22, 2:33=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > d_s_klein <d_s_kl...@yahoo.com> writes: > > It's part of Altera's 'check for updates'. > > > Just install rpm and be done with it; that's what I did. > > It seems like the real rpm is causing problems when I run > sopc_builder: > > Error: i2c_hdmi: error: cannot open Packages index using db3 - No such fi= le or directory (2) > > I don't have a single rpm file in my Altera installation nor in my > design database, or in my home directory. Is Quartus actually trying > to store IP in /var/lib/rpm (which usually requires root access)? > > This is odd as I never had any problems with Quartus up to 9.0. > > Petter > -- > .sig removed by request. Petter, Looks like rpm hasn't been through a successful "first run". The db3 file contains the rpm 'state' as it were. Let rpm rebuild its database - if that doesn't work, I'll dig out my install notes. RKArticle: 146604
On Mar 23, 2:56=A0pm, Gabor <ga...@alacron.com> wrote: > Any plans to support the other half of hardware developers in > the Verilog camp? We do want to support Verilog and SystemVerilog in the future. However, for now we concentrate on VHDL. http://www.sigasi.com/faq/what-about-systemverilog-and-other-languages PhilippeArticle: 146605
On Mar 22, 12:43=A0pm, Philippe <philippe.f...@gmail.com> wrote: > Integrated Development Environments (IDEs) have long been the primary > tool for software engineers. Like an airplane cockpit, an IDE is the > control center from which the engineer accesses all of the data and > tools that he needs. IDEs, and especially Eclipse, have proven to be > extensible, open, high quality platforms. > > However, until now, IDEs have not been popular in hardware development > circles. This is partly because many of the available IDEs for > hardware development have not lived up to the potential of IDEs that > is typical in the software world. Instead, IDEs tend to be overly > complex, closed, and they lock the customer in. > > Today, though, Eclipse is finally gaining traction among EDA > (electronic design automation) and FPGA companies. One such EDA > company, Sigasi, has just released the first commercial VHDL plugin > for Eclipse. Now, at last, hardware design teams can use Eclipse as a > basis for their own customized IDEs, based on the commercial and open- > source plugins that they need in their central cockpit for hardware > design. > > I've published a white paper on this subject.http://www.sigasi.com/conten= t/why-hardware-designers-should-switch-ec... > I'd be interested to know what you guys think. > > kind regards > > Philippe Faes > Founding CEO Sigasihttp://www.sigasi.com I'm another long-term emacs user. Eclipse is the standard environment for the Xilinx SDK and I quickly discovered that I did not like it. It's slow, and completely non-obvious, and has a lot of hidden directories and files in the project directories and at least in the Xilinx-specific environment I had no idea which of those magic files were actually important to the build process and which were cruft. (And Xilinx didn't have a good answer.) You want a good IDE for C programming? Apple's Xcode. I am not kidding. But for VHDL, nothing beats emacs and Reto's vhdl-mode. And why should I pay to get something that doesn't do nearly what emacs/vhdl-mode does? -aArticle: 146606
On Tue, Mar 23, 2010 at 12:42 PM, Ed McGettigan
<ed.mcgettigan@xilinx.com> wrote:
On Mar 23, 9:10 am, Jason Thibodeau <jason.p.thibod...@gmail.com>
wrote:
> On 03/23/2010 12:06 PM, Ed McGettigan wrote:
>
>
>
>
>
> > On Mar 23, 5:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com>
> > wrote:
> >> I'm sorry, Kal and Ed, I should have been more specific.
>
> >> I know what the gates are, but they are not defined in the code
> >> anywhere. I am figuring I need to include a library where they
will be
> >> defined, but I don't know which I should be using, or if any
are even
> >> available in the Xilinx flow.
>
> >> I import the (verilog) benchmark, instantiate it in my VHDL
toplevel,
> >> and when it is synthesized, I have 614 errors since the gates
are not
> >> defined.
>
> >> I was hoping it would be something as simple as including a
library.
>
> >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote:
>
> >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan
> >>> <ed.mcgetti...@xilinx.com> wrote:
>
> >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com>
> >>>> wrote:
> >>>>> I'm having a terrible time finding a solution to a library
problem.
>
> >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and
I need some
> >>>>> standard cells such as:
>
> >>>>> AOI21X1
> >>>>> AND3X1
> >>>>> AND2X1
> >>>>> NAND2X1
>
> >>>>> etc.
>
> >>>>> Does anyone have a suggestion? Am I overlooking something
simple?
>
> >>>>> Thanks in advance.
> >>>>> --
> >>>>> Jason Thibodeau
>
> >>>> The standard cell library should document the function of
each these
> >>>> cells. Likely guesses are.
>
> >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs?
> >>>> AND3X1 - 3-Input AND
> >>>> AND2X1 - 2-Input AND
> >>>> NAND2X1 - 2-Input NAND
>
> >>>> etc... = etc... :-)
>
> >>>> Ed McGettigan
>
> >>> If we had more info, we can make better guesses. The ports are
> >>> extremely helpful in fact. Usually AOI21 is AND-OR of two
inputs which
> >>> is OR-inverted with the third ie y = !((a0&a1) | b0).
> >>> One more thing which is again very helpful is to get the
simulation
> >>> model of the standard cell library and use it without any
timing as
> >>> the behavioral model. Synthesis tools do a pretty decent job
of doing
> >>> the mapping.
>
> >> --
> >> Jason Thibodeauwww.jayt.org-Hide quoted text -
>
> >> - Show quoted text -
>
> > It should be as simple as "including a library", but this won't
come
> > from Xilinx. You need to get it from the creator of the
standard cell
> > library that was used to insert these primitives into the HDL code
> > that you are using. This must exist somewhere or simulation
would not
> > be possible.
>
> > When you work this out and run through synthesis the performance of
> > the design will likely be much better with a flatten design so that
> > the basic primitives can be optimized correctly.
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> This is the direction in which I just headed. I added the
GSCLib_3.0.vhd
> available from the IWLS benchmark tar file. When I add this to the
> project, I get an error:
>
> ERROR:HDLParsers - Cannot rename dependency database for library
"ieee",
> file is "./xst/ieee/hdpdeps.ref", Temporary database file
> "./xst/xil_7sDTXM" will remain. System error message is: No
such file
> or directory
>
> (I had to edit the pathnames in the error message, but the full
> pathnames are listed in the actuall error message).
>
> I was having this same problem yesterday with a different
library. When
> I remove the GSCLib_3.0.vhd file from the project, it reverts to my
> previous 600+ errors.
>
> Any idea what is happening here?
>
> --
> Jason Thibodeau- Hide quoted text -
>
> - Show quoted text -
I'm not sure.
Did you compile the GSCLib_3.0 into "library work"? If you tried to
compile it into "library IEEE" that might explain the error message.
It looks like you are using the library that is found here:
http://openedatools.si2.org/cgi-bin/cvsweb.cgi/OAGear/Examples/IWLS/library/GSCLib_3.0.vhd?cvsroot=oagear
If anyone else wants to chime in.
Ed McGettigan
--
Xilinx Inc.
I think Ed mistakenly replied to my email address instead of the group,
so I copied it here.
My response: No I did not compile it into "IEEE", I put it into "work",
and I also tried its own library. Both options gave me the same error.
Article: 146607Philippe <philippe.faes@gmail.com> wrote: >Integrated Development Environments (IDEs) have long been the primary >tool for software engineers. Like an airplane cockpit, an IDE is the >control center from which the engineer accesses all of the data and >tools that he needs. IDEs, and especially Eclipse, have proven to be >extensible, open, high quality platforms. I couldn't agree more. I have read the other responses but what I read there is: I don't know Eclipse and I don't want to learn. I used to be among those until I gave Eclipse a good try. After getting used to the not so obvious layout and terms I understood the underlying ideas which are really nifty. Nowadays I develop everything with Eclipse because it helps me to keep a good overview on my projects. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 146608
On 23/03/10 12:23, jjplaw wrote: > Newbie here. I'm running a program that invokes a tcl file. I'm trying to > execute the xilinx tcl commands from that tcl script. > > In the tcl script, i only have the following code. > > source $env(XILINX)/bin/xilinx-init.tcl > > But i received the following error when the script gets invoked: > > error reading package index file C:/Xilinx/10.1/ISE/bin/pkgIndex.tcl: load: > Cannot match with any static package. > Try "load_unsupported" to load dynamic packages into statically wrapped > applications. > error reading package index file C:/Xilinx/10.1/ISE/bin/pkgIndex.tcl: load: > Cannot match with any static package. > Try "load_unsupported" to load dynamic packages into statically wrapped > applications. > can't find package xilinx > while executing > "package require xilinx" > (file "C:\Xilinx\10.1\ISE/bin/xilinx-init.tcl" line 30) > invoked from within > "source $env(XILINX)/bin/xilinx-init.tcl" > ........... > .... > > Anyone here with experience dealing with xilinx tcl commands? > Any idea how to solve this? Please advise.... > What command are you using to execute the tcl? With Xilinx, I would expect you to be using xtclsh, regards Alan -- Alan FitchArticle: 146609
Petter Gustad <newsmailcomp6@gustad.com> wrote: >Alan Fitch <apf@invalid.invalid> writes: > >> I find Eclipse baffling, though I wouldn't say I hate it. It seems to >> have weird jargon (what is a perspective?). > >Hi Alan, > >I've been using Makefiles and Emacs for many years. Using Eclipse I >have to search the hierarchy of perspectives, menus, tabs, etc. to >click a button in order to add -Os to CFLAGS for gcc! > >Also I don't like the concept of workspaces which are using files and >directories in a fixed place in the file system (even it it's your >home directory). I like to check out my design (being software or HDL) >from a revision control system anywhere and build it there, which >means using relative pathnames. Not true. Your can check out a project in any place and Eclipse will be perfectly happy since it will recreate the makefiles before building. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 146610
Philippe wrote: > I've published a white paper on this subject. > http://www.sigasi.com/content/why-hardware-designers-should-switch-eclipse > I'd be interested to know what you guys think. > > Philippe Faes > Founding CEO Sigasi > http://www.sigasi.com everybody preaches for his own church ;-) yg -- http://ygdes.com / http://yasep.orgArticle: 146611
Jason Thibodeau wrote: > BLOOOAAAATTTEEEEDDDDD oh yes, that too. > Eclipse is painful to use for me. I'm a Vi guy. > > Let the Vi/Emacs wars ensue :) anyone with me in favor of nano ? yg -- http://ygdes.com / http://yasep.orgArticle: 146612
On 03/23/2010 01:23 PM, Jason Thibodeau wrote: > > > On Tue, Mar 23, 2010 at 12:42 PM, Ed McGettigan > <ed.mcgettigan@xilinx.com> wrote: > > On Mar 23, 9:10 am, Jason Thibodeau <jason.p.thibod...@gmail.com> > wrote: > > On 03/23/2010 12:06 PM, Ed McGettigan wrote: > > > > > > > > > > > > > On Mar 23, 5:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com> > > > wrote: > > >> I'm sorry, Kal and Ed, I should have been more specific. > > > > >> I know what the gates are, but they are not defined in the code > > >> anywhere. I am figuring I need to include a library where they > will be > > >> defined, but I don't know which I should be using, or if any are even > > >> available in the Xilinx flow. > > > > >> I import the (verilog) benchmark, instantiate it in my VHDL toplevel, > > >> and when it is synthesized, I have 614 errors since the gates are not > > >> defined. > > > > >> I was hoping it would be something as simple as including a library. > > > > >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote: > > > > >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > > >>> <ed.mcgetti...@xilinx.com> wrote: > > > > >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> > > >>>> wrote: > > >>>>> I'm having a terrible time finding a solution to a library > problem. > > > > >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and I > need some > > >>>>> standard cells such as: > > > > >>>>> AOI21X1 > > >>>>> AND3X1 > > >>>>> AND2X1 > > >>>>> NAND2X1 > > > > >>>>> etc. > > > > >>>>> Does anyone have a suggestion? Am I overlooking something simple? > > > > >>>>> Thanks in advance. > > >>>>> -- > > >>>>> Jason Thibodeau > > > > >>>> The standard cell library should document the function of each > these > > >>>> cells. Likely guesses are. > > > > >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs? > > >>>> AND3X1 - 3-Input AND > > >>>> AND2X1 - 2-Input AND > > >>>> NAND2X1 - 2-Input NAND > > > > >>>> etc... = etc... :-) > > > > >>>> Ed McGettigan > > > > >>> If we had more info, we can make better guesses. The ports are > > >>> extremely helpful in fact. Usually AOI21 is AND-OR of two inputs > which > > >>> is OR-inverted with the third ie y = !((a0&a1) | b0). > > >>> One more thing which is again very helpful is to get the simulation > > >>> model of the standard cell library and use it without any timing as > > >>> the behavioral model. Synthesis tools do a pretty decent job of > doing > > >>> the mapping. > > > > >> -- > > >> Jason Thibodeauwww.jayt.org-Hide quoted text - > > > > >> - Show quoted text - > > > > > It should be as simple as "including a library", but this won't come > > > from Xilinx. You need to get it from the creator of the standard cell > > > library that was used to insert these primitives into the HDL code > > > that you are using. This must exist somewhere or simulation would not > > > be possible. > > > > > When you work this out and run through synthesis the performance of > > > the design will likely be much better with a flatten design so that > > > the basic primitives can be optimized correctly. > > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > > This is the direction in which I just headed. I added the GSCLib_3.0.vhd > > available from the IWLS benchmark tar file. When I add this to the > > project, I get an error: > > > > ERROR:HDLParsers - Cannot rename dependency database for library "ieee", > > file is "./xst/ieee/hdpdeps.ref", Temporary database file > > "./xst/xil_7sDTXM" will remain. System error message is: No such file > > or directory > > > > (I had to edit the pathnames in the error message, but the full > > pathnames are listed in the actuall error message). > > > > I was having this same problem yesterday with a different library. When > > I remove the GSCLib_3.0.vhd file from the project, it reverts to my > > previous 600+ errors. > > > > Any idea what is happening here? > > > > -- > > Jason Thibodeau- Hide quoted text - > > > > - Show quoted text - > > I'm not sure. > > Did you compile the GSCLib_3.0 into "library work"? If you tried to > compile it into "library IEEE" that might explain the error message. > > It looks like you are using the library that is found here: > > http://openedatools.si2.org/cgi-bin/cvsweb.cgi/OAGear/Examples/IWLS/library/GSCLib_3.0.vhd?cvsroot=oagear > > > If anyone else wants to chime in. > > Ed McGettigan > -- > Xilinx Inc. > > > I think Ed mistakenly replied to my email address instead of the group, > so I copied it here. > > My response: No I did not compile it into "IEEE", I put it into "work", > and I also tried its own library. Both options gave me the same error. I am writing my own library right now. With any luck I will not encounter the error I have seen previously. Thanks for the suggestions, all. -- Jason ThibodeauArticle: 146613
On Mar 23, 1:45=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > After getting used to the not so obvious layout and terms I understood > the underlying ideas which are really nifty. There's a term for that: "Stockholm Syndrome"Article: 146614
Peter wrote: ... >> Wow! I wouldn't have thought them to still be available! I've >> an XC4xxx in a design that I had abandoned figuring it would be >> impossible to get... I have some 4K designs out there that still are built. Chips are available but Xilinx makes sure that no one touches them unless absolutely needed (by price). > > I think the 4k devices are pretty well available. Also there is a huge > (vast) surplus component market out there. You could keep yourself > stocked in 1990s parts for ever. They gradually get more expensive, > and are rarely available right there when you want them (the stocks > appear at random times) and you can't get real production volumes, but > "low cost" and "Xilinx" was never said in the same sentence :) I have seen quite a lot of projects that they won via the price. Especially with Spartans. > The top > end 4k devices were about $1500 when I looked at using one for > building a replacement for a UART (one of the TMS9900 family) which TI come on, an UART is nothing that requires a top end 4k. Thats like "that 40 ton truck was not cost effective to deliver my beer bottle @ home." > stopped making but there were many 1000s in the field and for some > bizzare reason they had defective silicon which made them all fail > after some years. I lined-up an FPGA designer for the customer on that > job... That would have been a fun project - building a drop-in > replacement for a fairly complex uP peripheral chip. Obviously one > would not be implementing stuff like SDLC... maybe something like <http://www.oho-elektronik.de/> > >> So, your attitude is "move on to new tools *if* the need arises"? > > Actually, my attitude would be to bit-bang it with an Atmel uC. Every > single FPGA design I ever did could have been done with a fast simple > uC, with a bit of imagination Then you didn't have the right projects for FPGAs. - except the ASIC prototyping projects, > obviously. Might need a few chips on the outside but the learning > curve of assembler programming is maybe 1% of the l.c. on FPGA design. > And you don't have to re-learn everything every time the FPGA vendor > turns everything upside down in trying to keep ahead of the > competition. Try to make a Software defined radio with a 1300 MSPS ADC, down converters and polyphase filters with one of those Atmels. OK, the ADCs were kinda Atmel or so. > I decided long ago that FPGAs are a technology for "must > get there now before the competition no matter what the long term cost > is" and the long term cost is that after a few years you cannot > maintain the design because after the original designer has left > nobody will want to touch it. And the later tools will not import the > original designs, which is really great.... Program your stuff yourself in Verilog or VHDL or Matlab and resist the sticky "easy" way of X/A block generators. > in fact that happened > right after Xilinx dropped Viewlogic as schematic entry. It was a lot of work to make them drop Viewlogic and Omation crap in favor of DOS Orcad. > I had loads > of correspondence with them at the time but their view was "tough... > move on". All schematics had to be re-drawn in the new tool. You could > keep VL running somewhere but if the dongle broke, everything was > orphaned. Luckily, as I said, the dongle got cracked ;) I still have 4 original dongles, 2 full and 2 APR only.... and there was just a counter inside that counted from 0 to something like 250, the 'something' being the options available. I knew no one in the field who did not know that. You cannot stop a guy with a logic analyzer on his table with a simmple counter. We ran 4 Compaq '286s overnight to possibly get a working 30[249]0 the next morning. A lot of prehistoric versions are available on Xilinx' web site. I didn't test it because I have it archived anyway. Maybe it's harder to archive a computer that can run it. Anybody interested in a shiny SILOS simulator license with handbook and original dongle? regards, GerhardArticle: 146615
rickman wrote:
> On Mar 22, 1:46 pm, Jim Stewart <jstew...@jkmicro.com> wrote:
>> rickman wrote:
>>
>> snip..
>>
>>> I wonder how long it will be before we give up on schematics
>>> altogether and just write pin lists or net lists?
>> After I'm retired I hope. A well drawn schematic is a
>> thing of beauty, helping techs to troubleshoot and
>> customers to understand a product.
>>
>> You could also ask when mechanical engineers will stop
>> using fab drawings and just send the data as G codes.
>
> I guess if you have an analog design with a lot of small components a
> schematic is good, but for many digital designs there is almost no
> point. Look inside any number of modern products and you see one, two
> or three large IC packages with lots of traces between them and few
> smaller components. The schematics for these products are horrendous,
> often much less clear than a simple pin list. Its not that they were
> drawn badly, but that it is impossible to draw a 300+ pin part with
> much utility. Even by breaking the part into sections it still ends
> up being a pin list with a box around it.
>
> I'll grant that analog designs can gain from schematic, but many of
> the digital ones are pointless when drawn.
I recently played with the Altium Designer, seems to be quite OK, and I
exported a low noise amplifier in VHDL for the fun of it:
entity MAT02 is port (
base: inout something;
emitter: inout something;
collector: inout something
);
end entity MAT02;
...........
q1: mat02 port map (
base => input,
emitter => tail_current_source,
collector => left_c
)
was quite pointless for an analog design. But then you can spice that amplifier,
at least from the original circuit.
(cited from memory under influence of some nice Rioja :-) )
OTOH you can easily bridge the gap between a Xilinx user constraint file and
the things on the board that are connected to the FPGA. I like it. Maybe I'll buy it.
Gerhard
Article: 146616As I mentioned in another message, I am attempting to implement an IWLS benchmark on a spartan3e. I wrote definitions for all the undefined gates, and it now synthesizes just fine. However, I am attempting to manually place and route some main blocks in the design. When I go into PlanAhead, I do not see my benchmark listed in the primitives. This benchmark has an lfsr feeding it (the lfsr is also not able to be seen in PlanAhead), and the ourputs are tied to a signal, but are not tied to pins on the fpga. What am I doing wrong? -- Jason ThibodeauArticle: 146617
>What command are you using to execute the tcl? With Xilinx, I would >expect you to be using xtclsh, > >regards >Alan > >-- >Alan Fitch > Probably i'm asking the wrong question. I intend to run most the xilinx tcl commands from project creation to bitstream creation. But the script is being invoked from an exe file. When the script gets invoked, it's evaluated in a Tcl regular shell causing all the xilinx tcl commands to be undefined/no recognized. How do i load/initialize the xilinx tcl libraries into that script so that i can use the xilinx tcl commands. I tried using "source $env(XILINX)/bin/xilinx-init.tcl" which was taken from the Xilinx Development System Reference Guide document(Chapter 3, page 54) but i received the error above. Please advise. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146618
Hi Srikanth, Some of my colleagues at Altera just ran this, and got the correct result (old_data). They had a couple of ideas of what might be happening though -- basically depending on exactly how you set the megafunction up, you could get X data in this case. 1. In the mem_init page of the RAM, 2-Port megafunction, are you selecting "Initialize memory contents to XXX...X on power up in simulation"? If you are, then you'll get X's until you load the RAM via explicit writes in your design. 2. Are you using two clocks on the 2-port RAM? If so, I believe we'll have cases where we don't know what data will show up on the output when you read the same address you're writing to, as exactly what happens when the clocks are get to certain alignments becomes so timing sensitive that it is undefined. If it's not either of these two cases, if you send an archive of your design to me I can forward it on to the developers who looked at this for a more in-depth look. Hope this helps, Vaughn [v b e t z (at) altera.com]Article: 146619
On Mar 23, 6:02=A0pm, Gabor <ga...@alacron.com> wrote: > On Mar 23, 6:19=A0am, Magne Munkejord <magnem...@yahoo.no> wrote: > > > > > > > Seeker wrote: > > > On Mar 23, 2:07 pm, Magne Munkejord <magnem...@yahoo.no> wrote: > > >> Hi, > > > >> Each address designates a 64 bit word in memory. > > >> Are you sure about the FIFO's width? As far as I remember this was 1= 28 > > >> bits for read and write data. The command FIFOs width is 36. > > > >> The DDR2 controller transmits 64 bits at rising and 64 bits at falli= ng > > >> edge of the clock, 128 bits per clock cycle. > > > >> A burst size of 8 means 8x64 bits words burst length which is 4x128 = bits > > >> words in your data FIFOs (read or write) per read/write command. > > > >> HTH, > > > >> Magne > > > > Thanks for the reply, > > > You are right, the data FIFO is 128 bits wide. > > > In case of a burst length of 4, every write command would have 2x128 > > > bits write (4x64 bits). If each address designates a 64 bit word in > > > memory (which is what I thought), the addresses should be generated > > > with an offset of 4 (since there are 4 64 bit words, each 64 bits > > > corresponds to a location in memory), the addresses should progress > > > like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation > > > generated from MIG progresses the addresses with an offset of 8? Is i= t > > > just to show writing and reading of the memory? > > > > Seeker... > > > Could be, but I remember that a burst length of 8 is also an option in > > the MIG so maybe they made the testbench so that it would work for both > > options (4 and 8 burst length) or maybe the testbench is confused which > > option is set? > > (by "offset of 8" I assume you mean increments of 8.) > > > Magne > > Maybe the testbench writer was just lazy and an offset of 8 > would "work" for either case because you never overwrite > any data even though in the burst of 4 case you skip over > half the available memory? > > - Gabor- Hide quoted text - > > - Show quoted text - @Magne I think you are right. I ran a simulation with the burst length of 8 and the address generation was following the same pattern. Thanks everyone for your replies. Seeker..Article: 146620
Gerhard Hoffmann <usenet@hoffmann-hochfrequenz.de> wrote >Then you didn't have the right projects for FPGAs. Sure, to a degree. >Try to make a Software defined radio with a 1300 MSPS ADC, down converters >and polyphase filters with one of those Atmels. >OK, the ADCs were kinda Atmel or so. I bet the FPGA implementation would have been too pricey for the market though - unless military. So you would have effectively been doing an ASIC prototype with it. >It was a lot of work to make them drop Viewlogic and Omation crap >in favor of DOS Orcad. Yes, I recall seeing Orcad libraries at the time. That was another unfortunate product - their windoze version could not properly import DOS Orcad schematics (really clever). >I still have 4 original dongles, 2 full and 2 APR only.... and there >was just a counter inside that counted from 0 to something like 250, >the 'something' being the options available. I knew no one in the field >who did not know that. You cannot stop a guy with a logic analyzer on >his table with a simmple counter. That's true. I have a schematic of the Viewlogic dongle somewhere. But not the later XACT5 one. I think that one had an EEPROM. >We ran 4 Compaq '286s overnight to possibly get a working 30[249]0 the next morning. What is that? >A lot of prehistoric versions are available on Xilinx' web site. I didn't >test it because I have it archived anyway. Maybe it's harder to archive >a computer that can run it. Archiving the PC *is* something a lot of big firms do, apparently. They also archive tape drives.Article: 146621
On Mar 22, 1:31=A0am, Alessandro Basili <alessandro.bas...@cern.ch> wrote: > On 3/20/2010 10:46 AM, HT-Lab wrote: > > > > > There are lots of places were you can legally download it from, if you = do a > > google search (amba bus protocol) then the first entry is wikipedia and= the > > second is: > > >http://ens.ewi.tudelft.nl/Education/courses/et4351/amba.pdf > > > If you read the second page it states: > > > Document confidentiality status > > This document is Open Access. This document has no restriction on distr= ibution. > > I just had a read to this document:http://www.opencores.org/downloads/soc= _bus_comparison.pdf > > Apparently the wishbone seams much easier to use then the other two > reported, but it seems to be it doesn't support address pipelining (as > Rob already mentioned), which so far I don't have any element to > evaluate whether this is a main problem or not. > > My main intent is to promote, or support and spread the concept of > _reuse_ especially in the research world (where I belong to) where > people are kind of keen to "reinvent" the wheel. I believe that a lot of > efforts can be made more fruitful if a common interface would be availabl= e. > > Al > > -- > Alessandro Basili > CERN, PH/UGC > Hardware Designer The idea of using WISHBONE was two-fold: 1) It's simplicity and openness 2) If the OpenCores community would standardise on it, we could potentially develop "wrappers" or "bridges" to other buses, such as AHB and OPB for example. If you are developing an IP Core for deposit on OpenCores, it would make sense to use WISHBONE, if it will be technically feasible. Cheers, rudiArticle: 146622
On Mar 18, 8:09=A0am, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: .... > Ain't I allowed to complain about the hard-core DRAM interface? We're > trying to get it to work at 128 MHz, the very bottom of its specified > speed range. > > John Hmm, may the 128Mhz is the problem ! Seems to work just fine at 675 MHz ! :) Cheers, rudiArticle: 146623
>http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&item=290416326824 > >x----------x I am adding my stock of Xilinx parts to the software for sale: 1 x XC3090A-6-PC84C 8 x XC3142-5-TQ100C 4 x XC3042-70-TQ100C 2 x XC3064A-7-TQ144C All unused. x----------xArticle: 146624
> I intend to run most the xilinx tcl commands from project creation to > bitstream creation. But the script is being invoked from an exe file. When > the script gets invoked, it's evaluated in a Tcl regular shell causing all > the xilinx tcl commands to be undefined/no recognized. Is there a reason why you are running your script with tclsh from your exe, rather than using xtclsh? xtclsh understands the xilinx tcl commands.
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