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Jason Thibodeau wrote:
> I'd like to bump this. Any word on how Ic an stop it from optimizing my
> required logic away? Why wouldn't Xilinx just allow me to turn off
> optimization?
If you use VHDL, there are some "pragma" or "attribute"s
("set_dont_touch" or "keep" ?) that specify that a net must be kept.
It worked for me on Actel/Synplify but I don't remember the syntax.
I suppose that the same exists in Verilog.
A quick googling told me (unchecked) :
http://www.xilinx.com/itp/xilinx8/books/data/docs/xst/xst0059_8.html
www.altera.com/literature/hb/qts/qts_qii51008.pdf
and more, but I couldn't spend much time on this.
HTH
yg
--
http://ygdes.com / http://yasep.org
Article: 146776Jason Thibodeau wrote: > I'd like to bump this. Any word on how Ic an stop it from optimizing my > required logic away? Why wouldn't Xilinx just allow me to turn off > optimization? ok in fact I have found the following : http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir.htm http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_keep.htm http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_noprune.htm http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_preserve.htm just use these keywords to search in XST's docs. _o/ yg -- http://ygdes.com / http://yasep.orgArticle: 146777
On Mar 28, 8:31=A0am, Randy Yates <ya...@ieee.org> wrote: > I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator > that already has a high (baseband) sample rate - around 40-80 MHz. > > What kind of (single-bit) output rate can you get with a CPLD or FPGA > device? FPGAs are not analog devices!! You would probably want to have something retime and buffer any delta-sigma style signal coming from the FPGA to get the precision phase and amplitudes for a proper analog result. Running clean analog cleanup filters at that frequency can be pretty daunting as well. You could probably extend the lookup concept for the raw delta sigma output stream but do you have the number of needed bits figured out? For the analog case, you could add multiple simple lookup values for multiple adjacent pulses to account for the transmit intersymbol interference, no memory required. But for a delta-sigma stream you need to have all the lookup bits to produce your oversampled stream. Your best bet for output rate would probably be LVDS differential. On the Spartan-3A, for instance, you should be able to hit 668Mb/s. If you go to the more costly families the Gigabit transceivers can go a little beyond 3Gb/s. Have you used delta-sigma converters before? Do you know what order filter you'd be pursuing and what your oversampling rate needs to be to achieve the 14 bits you were talking about? Or are you happy with 6 bits of I/Q effective resolution? I don't know of anyone personally who has rolled their own delta sigma DACs but I know there are different kinds out there including a bandpass style that gives modulation of a carrier, typically Fs/4, that could help you achieve your end result cleaner. You could conceivably go straight mixer instead of I/Q modulator if you used the lookup approach with a much wider lookup. Rather than using small on- board memories, going much larger with an external SRAM or the jumbo memory blocks like in the Altera Stratix parts could give you a direct Delta Sigma stream output. The streams would have to be carefully tailored to be spliceable or include some of the residual values from the modulator making the lookup a huge table. At least I imagine bandpass SAW filters are easier to come by in your frequency range. Simplifying the project hardware sounds potentially fun but full of opportunities to do things wrong. Are you aware of the Analog Devices digital modulator chips? I used to follow their TXDACs and saw them becoming more and more capable over time.Article: 146778
On Mar 28, 1:22=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > > If you're going to feed the clock back, then you'll want to parallel > terminate to ground rather than series terminate at the source. I figured the external lines are small enough that the transmission line characteristics are no longer as important as the lumped model. Having a series resistor could help the transmitter avoid too much of a surge. The termination at the final destination is the classical version, however. Having room for both can help, perhaps more than hinder.Article: 146779
On Mar 28, 3:38=A0pm, Symon <symon_bre...@hotmail.com> wrote: > On 3/26/2010 9:13 PM, radarman wrote: > > > > > I've only done one other "high speed" design, with a Gig-E PHY, but I > > was able to get all of the signals to within +/- 5 mils on that board. > > When you did this, you took into account the different flight times in > the packages themselves, I hope! For sure the leadframes don't have > matched lengths on the signals from the die to the PCB pad. > > In summary, what the other guys said, 6 inches a ns! > > Cheers, Syms. The flight times in the package shouldn't hit the timing budget at all. The timing for both the SRAM and FPGA will be worst case for any pin. And what's a few 10s of picoseconds?Article: 146780
On 3/28/2010 10:28 PM, John_H wrote: > On Mar 28, 3:38 pm, Symon<symon_bre...@hotmail.com> wrote: >> On 3/26/2010 9:13 PM, radarman wrote: >> >> >> >>> I've only done one other "high speed" design, with a Gig-E PHY, but I >>> was able to get all of the signals to within +/- 5 mils on that board. >> >> When you did this, you took into account the different flight times in >> the packages themselves, I hope! For sure the leadframes don't have >> matched lengths on the signals from the die to the PCB pad. >> >> In summary, what the other guys said, 6 inches a ns! >> >> Cheers, Syms. > > The flight times in the package shouldn't hit the timing budget at > all. The timing for both the SRAM and FPGA will be worst case for any > pin. And what's a few 10s of picoseconds? Well, I agree, but did you read his post? He's making trace lengths match to within 5 mils! That's what I'm trying to suggest may be a waste of effort. Cheers, Syms. p.s. FWIW, you can get the flight times of BGA packages from Xilinx, if you ask nicely.Article: 146781
On Mar 28, 9:27 pm, Symon <symon_bre...@hotmail.com> wrote: > On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yates<ya...@ieee.org> wrote: > >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator > >> that already has a high (baseband) sample rate - around 40-80 MHz. > > > That's a very bad idea. > > For your sort of application homemade delta-sigma DAC can't match > > combination of price, SNR, SFDR and power provided by something like > > AD9754. > > I'm pretty sure on price and power (I assume efficiency?) his solution > does match your suggested alternative given that, from details in his > previous postings on this newsgroup, the FPGA/CPLD device is a sunk > cost. I agree with your other acronyms though! > Cheers, Syms. At what rate do you have to generate pulses to build, say 12-bit 80 MSPS? I don't know the exact answer but pretty sure that the required rate is way above capabilities of CPLDs and likely above what's possible with smallest FPGAs. You would need FPGA with the serializer implemented in hardware So, still on the digital side, you are pushed from something like $4 up to something like $30 or more. The difference already pays for several AD9754s both in money and in power consumption. Now, consider all the analog parts that you need to filter you pulse train into nice analog signal. Since, even with mid-range FPGA you will have relatively modest oversampling (factor of 15 or something like that) the analog filter will have to be rather sharp and probably high order. It would cost you more money and more power. As I said above, implementing high speed DAC in programmable logic device is very bad idea. Implementing voice-grade (voice, not audio) DAC sounds less crazy but from point of view of economics, power and board real estate even that is more often than not a losing proposition.Article: 146782
On 28/03/10 21:24, whygee wrote: > Jason Thibodeau wrote: >> I'd like to bump this. Any word on how Ic an stop it from optimizing my >> required logic away? Why wouldn't Xilinx just allow me to turn off >> optimization? > ok in fact I have found the following : > http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir.htm > http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_keep.htm > http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_noprune.htm > http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_preserve.htm > just use these keywords to search in XST's docs. > _o/ > yg Hi Yg - I agree with your proposed solution - however I suggest Jason looks on the Xilinx website for the correct XST incantations :-; regards Alan -- Alan FitchArticle: 146783
On 29 Mar, 00:43, Alan Fitch <a...@invalid.invalid> wrote: > On 28/03/10 21:24, whygee wrote: > > > Jason Thibodeau wrote: > >> I'd like to bump this. Any word on how Ic an stop it from optimizing my > >> required logic away? Why wouldn't Xilinx just allow me to turn off > >> optimization? > > ok in fact I have found the following : > >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... > >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... > >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... > >http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... > > just use these keywords to search in XST's docs. > > _o/ > > yg > > Hi Yg - I agree with your proposed solution - however I suggest Jason > looks on the Xilinx website for the correct XST incantations :-; > > regards > Alan > > -- > Alan Fitch This should help: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf keep constraint regards ModimoArticle: 146784
Michael S <already5chosen@yahoo.com> writes: > On Mar 28, 9:27 pm, Symon <symon_bre...@hotmail.com> wrote: >> On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yates<ya...@ieee.org> wrote: >> >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modulator >> >> that already has a high (baseband) sample rate - around 40-80 MHz. >> >> > That's a very bad idea. >> > For your sort of application homemade delta-sigma DAC can't match >> > combination of price, SNR, SFDR and power provided by something like >> > AD9754. >> >> I'm pretty sure on price and power (I assume efficiency?) his solution >> does match your suggested alternative given that, from details in his >> previous postings on this newsgroup, the FPGA/CPLD device is a sunk >> cost. I agree with your other acronyms though! >> Cheers, Syms. > > At what rate do you have to generate pulses to build, say 12-bit 80 > MSPS? I don't know the exact answer but pretty sure that the required > rate is way above capabilities of CPLDs and likely above what's > possible with smallest FPGAs. > You would need FPGA with the serializer implemented in hardware So, > still on the digital side, you are pushed from something like $4 up to > something like $30 or more. The difference already pays for several > AD9754s both in money and in power consumption. Now, consider all the > analog parts that you need to filter you pulse train into nice analog > signal. Since, even with mid-range FPGA you will have relatively > modest oversampling (factor of 15 or something like that) the analog > filter will have to be rather sharp and probably high order. It would > cost you more money and more power. > > As I said above, implementing high speed DAC in programmable logic > device is very bad idea. > Implementing voice-grade (voice, not audio) DAC sounds less crazy but > from point of view of economics, power and board real estate even that > is more often than not a losing proposition. Michael, "Bad" is relative to your criteria. Hint: in my application, cost and power are not important. Size is very important. The AD9754 is 700 mils long, not a small part, and you'd need two of them. But I do agree it is not a good idea unless you really need it. By the way, I have designed a production-quality delta sigma D/A. It went in over 17M Sony Ericsson phones. But it was implemented in software on a TMS320C54x, not FPGA. You can see a presentation I made on it at the first comp.dsp conference here: http://www.digitalsignallabs.com/presentation.pdf -- Randy Yates % "I met someone who looks alot like you, Digital Signal Labs % she does the things you do, mailto://yates@ieee.org % but she is an IBM." http://www.digitalsignallabs.com % 'Yours Truly, 2095', *Time*, ELOArticle: 146785
On 03/28/2010 07:24 PM, modimo wrote: > On 29 Mar, 00:43, Alan Fitch<a...@invalid.invalid> wrote: >> On 28/03/10 21:24, whygee wrote: >> >>> Jason Thibodeau wrote: >>>> I'd like to bump this. Any word on how Ic an stop it from optimizing my >>>> required logic away? Why wouldn't Xilinx just allow me to turn off >>>> optimization? >>> ok in fact I have found the following : >>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... >>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... >>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... >>> http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_d... >>> just use these keywords to search in XST's docs. >>> _o/ >>> yg >> >> Hi Yg - I agree with your proposed solution - however I suggest Jason >> looks on the Xilinx website for the correct XST incantations :-; >> >> regards >> Alan >> >> -- >> Alan Fitc > This should help: > http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf > keep constraint > regards Modimo I should have mentioned that I have tried all the iterations of keep that I could think of, the gates are still being optimized out. I tried both placing the keep attribute in the code, and using the xcf file, neither have worked. I think part of the problem is I don't know hte exact name of the nets being optimized out, since XST doesn't tell me this information in the reports. I'm at a different machine right now, but I'll post up some code snippets in the morning. Thanks for the help, all. -- Jason ThibodeauArticle: 146786
Hi, From the first moment I learn how stack segment and stack pointer are used to link all subroutines in PC, I have been appreciating the hardware structure as I can and I think it is the the most beautiful and memorable hardware structure I have learn from the CPU structure. I want to know who invented the structure. Is an IBM engineer? And it is strange enough that after PC was created, no big new structure in CPU has ever invented. MESI protocol? No. Changing 1 core to 2 core, or even 8 cores is considered as a big invention? No. Oh, I forgot to mention the most important invention since then is the Mouse we use it every day. Any idea? WengArticle: 146787
Hey, Thank you for the answers. I might end up using Webpack because I have a Xilinx ISE 9.2. Aditi. On Mar 27, 11:36=A0am, John Adair <g...@enterpoint.co.uk> wrote: > Webpack supports up to and including the XC6SLX75 according tohttp://www.= xilinx.com/publications/matrix/Software_matrix.pdf. > > John Adair > Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Development Board. > > On 27 Mar, 00:05, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > On Mar 26, 4:26=A0pm, Aditi <aditi...@gmail.com> wrote: > > > > Hi, > > > > I am using the XC6SLX9 FPGA in my new design. > > > I would like to know what version of XILINX ISE is required for > > > Spartan-6 series? =A0Can Webpack work with > > > Spartan 6? > > > > Thank you, > > > Aditi. > > > The ISE 11.5 Webpack version supports most of the Spartan-6 devices > > including the XC6SLX9. > > > Ed McGettigan > > -- > > Xilinx Inc.Article: 146788
On Mar 28, 5:42=A0pm, Symon <symon_bre...@hotmail.com> wrote: > > Well, I agree, but did you read his post? He's making trace lengths > match to within 5 mils! That's what I'm trying to suggest may be a waste > of effort. I missed that. My recollection was the lengths were varied between 250 and 750 mils and he hadn't changed that decision yet. I need to pay more attention, I guess. TIMING BUDGET !!!! I had an engineer at my previous place of employ who quite literally "broke" a layout person with the outrageous constraints for the DDR2, mostly waaaay too tight and sometimes conflicting. Do the budget, know the needs, plan the clock, open your windows.Article: 146789
On Mar 28, 8:33=A0pm, Randy Yates <ya...@ieee.org> wrote: > Michael S <already5cho...@yahoo.com> writes: > > On Mar 28, 9:27 pm, Symon <symon_bre...@hotmail.com> wrote: > >> On 3/28/2010 5:51 PM, Michael S wrote:> On Mar 28, 2:31 pm, Randy Yate= s<ya...@ieee.org> =A0wrote: > >> >> I'm thinking of implementing a delta-sigma D/A for the SOQPSK modul= ator > >> >> that already has a high (baseband) sample rate - around 40-80 MHz. > > >> > That's a very bad idea. > >> > For your sort of application homemade delta-sigma DAC can't match > >> > combination of price, SNR, SFDR and power =A0provided by something l= ike > >> > AD9754. > > >> I'm pretty sure on price and power (I assume efficiency?) his solution > >> does match your suggested alternative given that, from details in his > >> previous postings on this newsgroup, the FPGA/CPLD device is a sunk > >> cost. I agree with your other acronyms though! > >> Cheers, Syms. > > > At what rate do you have to generate pulses to build, say 12-bit 80 > > MSPS? I don't know the exact answer but pretty sure that the required > > rate is way above capabilities of CPLDs and likely above what's > > possible with smallest FPGAs. > > You would need FPGA with the serializer implemented in hardware So, > > still on the digital side, you are pushed from something like $4 up to > > something like $30 or more. The difference already pays for several > > AD9754s both in money and in power consumption. Now, consider all the > > analog parts that you need to filter you pulse train into nice analog > > signal. Since, even with mid-range FPGA you will have relatively > > modest oversampling (factor of 15 or something like that) the analog > > filter will have to be rather sharp and probably high order. It would > > cost you more money and more power. > > > As I said above, implementing high speed DAC in programmable logic > > device is very bad idea. > > Implementing voice-grade (voice, not audio) DAC sounds less crazy but > > from point of view of economics, power and board real estate even that > > is more often than not a losing proposition. > > Michael, > > "Bad" is relative to your criteria. Hint: in my application, cost and > power are not important. Size is very important. The AD9754 is 700 mils > long, not a small part, and you'd need two of them. > > But I do agree it is not a good idea unless you really need it. > > By the way, I have designed a production-quality delta sigma D/A. It > went in over 17M Sony Ericsson phones. But it was implemented in > software on a TMS320C54x, not FPGA. You can see a presentation I > made on it at the first comp.dsp conference here: > > =A0http://www.digitalsignallabs.com/presentation.pdf > -- Nice presentation, thanks. Not a lot of meat but it looks like you're deep enough into the science that you have a good handle on the oversampling ratio you'll need to support the 2Msps IQ rates as well as the filter order you're targeting. You should know the pulse size for the SOQPSK method you're pursuing (-A, -B, -TK?) so you know how much history you'd need for a lookup of symbol to output data. Here's something I hadn't considered: since FPGAs are far from analog components, are there small serializers that have significantly better jitter and amplitude characteristics such that you could broad-load 10 or 20 bits at a time from the FPGA and shoot those out at multi- gigabit rates, replacing the retime and relevel circuit I was suggesting before? I still think the 1-bit oversampled lookups will be problematic if at least the first order residual isn't matched in the multi-order delta sigma modulator. Am I being paranoid? I like how this could come together (in my own mind): a few symbols of 2-bit I/Q history, simple lookups pushing data to external serializer, pre-calculated bandpass delta-sigma stream produces I/Q modulated carrier directly to high IF, single filter to recover a clean IF, simple mixer rather than I/Q modulators, SAW filter. And I'm not sure about the bandpass style delta sigma modulator but I think they're well developed.Article: 146790
On Mar 26, 8:32=A0pm, wojtek <wojtekpowiertow...@gmail.com> wrote: > On Mar 26, 1:58=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > well, USB 3.0 is the first one that needs NO PHY > > > as the MGT's in some newer FPGA's are USB 3.0 capable directly > > just wire MGT to usb 3.0 superspeed pins, and that about it > > > Antti > > That is the first time i hear abou MGT being compatible with USB 3.0 > PHY, but I haven't doing anything in USB 3.0 topic for almost a year. > I must say I find it hard to believe thought, because USB 3.0 besides > translating digital signal to differential analog signal also > transmits USB 3.0 specific LFPS (low frequency pulse signaling) and > from what I learned the USB 3.0 PHY was supposed to take care of that > (just like latest PCI express PHY, which has similar LFPS technology). > I believe the MGT doesn't support that. But as I've said I hadn't even > researched it for some time, so I might be wrong. USB 3.0 calls the "LFPS" now "OOB". Xilinx GTX transceivers have no problem supporting that. Matter of fact we have a fully working USB 3.0 device IP Core running on Xilinx FPGAs. One more note to the OP: In order to properly implement USB 3.0, you would most likely need a protocol analyser, roughly a $50K investment ... Cheers, rudiArticle: 146791
On Mar 26, 7:58=A0am, Antti <antti.luk...@googlemail.com> wrote: > well, USB 3.0 is the first one that needs NO PHY > > as the MGT's in some newer FPGA's are USB 3.0 capable directly > just wire MGT to usb 3.0 superspeed pins, and that about it I'm slightly confused by this statement. If 3.0 requires fallback capability, how could FPGA hardware be compatible with 3.0 without being compatible with an earlier version, and if FPGA hardware IS compatible with an earlier version, how can you call 3.0 the first?Article: 146792
I bought evaluation board form one american company. This boad was 2 month delayed. After I received it ,the contents is missing. Oh my good!. I'm extermly disappointed.Article: 146793
On 29/03/2010 06:00, Patrick Maupin wrote: > On Mar 26, 7:58 am, Antti<antti.luk...@googlemail.com> wrote: >> well, USB 3.0 is the first one that needs NO PHY >> >> as the MGT's in some newer FPGA's are USB 3.0 capable directly >> just wire MGT to usb 3.0 superspeed pins, and that about it > > I'm slightly confused by this statement. If 3.0 requires fallback > capability, how could FPGA hardware be compatible with 3.0 without > being compatible with an earlier version, and if FPGA hardware IS > compatible with an earlier version, how can you call 3.0 the first? The compatibility arises because USB 3.0 uses a new connector that has both USB 2.0 connections and the new (SuperSpeed) connections. AndrewArticle: 146794
What are some undergrad and grad schools out there that are under- recognized but still have great computer architecture, design automation, or Digital Integrated-Circuit Design programs? I'd like thread contributers to post names of universities/college programs, the country or state, private or public, and maybe a link to course offerings. I'll start off with one: Portland State Univesrity (Portland, OR) http://www.ece.pdx.edu/Graduate/areas_of_study.php areas of emphasis for their grad program: computer architecture, design automation, IC design, micro- and nano-electronics Also feel free to post some big name universities with an explanation of what you may find distinguishes them from other universities. From prenom.nom@gmail.com Mon Mar 29 00:37:36 2010 Path: unlimited.newshosting.com!s02-b41!npeersf02.iad.highwinds-media.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!news3.google.com!proxad.net!feeder1-2.proxad.net!212.27.60.64.MISMATCH!cleanfeed3-b.proxad.net!nnrp9-2.free.fr!not-for-mail Date: Mon, 29 Mar 2010 10:37:36 +0200 From: Matthieu Michon <prenom.nom@gmail.com> Newsgroups: comp.arch.fpga Subject: Re: XST optimization Message-Id: <20100329103736.1cab9804.prenom.nom@gmail.com> References: <hogc8a$bna$1@news.eternal-september.org> <ff82ce59-ba6b-4b9f-b13a-f16ea9857a01@p3g2000pra.googlegroups.com> <hoiln0$nb3$1@news.eternal-september.org> <hoo16s$7aj$1@news.eternal-september.org> <hoog3f$251$1@speranza.aioe.org> <LKOdndSyAObnRjLWnZ2dnUVZ8lVi4p2d@brightview.co.uk> <cc6ea746-862c-4352-9fa2-4006938b38a6@x12g2000yqx.googlegroups.com> <hoovpt$7ao$1@news.eternal-september.org> X-Newsreader: Sylpheed 2.7.1 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 20 Organization: Guest of ProXad - France NNTP-Posting-Date: 29 Mar 2010 10:37:37 MEST NNTP-Posting-Host: 213.215.9.6 X-Trace: 1269851857 news-3.free.fr 23878 213.215.9.6:49451 X-Complaints-To: abuse@proxad.net Xref: unlimited.newshosting.com comp.arch.fpga:99779 X-Received-Date: Mon, 29 Mar 2010 08:37:37 UTC (s02-b41) On Sun, 28 Mar 2010 21:29:31 -0400 Jason Thibodeau <jason.p.thibodeau@gmail.com> wrote: (...) > > I should have mentioned that I have tried all the iterations of keep > that I could think of, the gates are still being optimized out. I tried > both placing the keep attribute in the code, and using the xcf file, > neither have worked. I think part of the problem is I don't know hte > exact name of the nets being optimized out, since XST doesn't tell me > this information in the reports. Altough it is not universal, I use the "S" (save net flag) attribute for keeping signals from being optimized (typically for displaying them in Chipscope). The "S" attribute is described in the Constraint Guide (cgd.pdf). -- Matthieu Michon <prenom.nom@gmail.com>Article: 146795
On 3/29/2010 5:03 AM, John_H wrote: > > TIMING BUDGET !!!! > > I had an engineer at my previous place of employ who quite literally > "broke" a layout person with the outrageous constraints for the DDR2, > mostly waaaay too tight and sometimes conflicting. > > Do the budget, know the needs, plan the clock, open your windows. Amen!Article: 146796
On 3/29/2010 6:28 AM, life.is.best wrote: > I bought evaluation board form one american company. > This boad was 2 month delayed. > After I received it ,the contents is missing. > Oh my good!. > I'm extermly disappointed. > http://www.azlyrics.com/lyrics/neilyoung/pieceofcrap.htmlArticle: 146797
On Mar 29, 4:06=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > ... > From the first moment I learn how stack segment and stack pointer are > used to link all subroutines in PC, I have been appreciating the > hardware structure as I can and I think it is the the most beautiful > and memorable hardware structure I have learn from the CPU structure. > I want to know who invented the structure. Is an IBM engineer? > And it is strange enough that after PC was created, no big new > structure in CPU has ever invented. MESI protocol? No. Changing 1 core > to 2 core, or even 8 cores is considered as a big invention? No. > Oh, I forgot to mention the most important invention since then is the > Mouse we use it every day. > Any idea? > ... > Weng A little bit OT... anyway I think you mean the "von Neumann architecture" and the "Harvard architecture" both being maybe the most (but not the only) used CPU architectures. You can use as start point the followings: http://en.wikipedia.org/wiki/Von_Neumann_architecture http://en.wikipedia.org/wiki/Harvard_architecture Regards SandroArticle: 146798
Sandro wrote: > A little bit OT... Yes, this thread would better suit the comp.arch group. There are great CPU architecture specialists there :-) > Regards > Sandro yg -- http://ygdes.com / http://yasep.orgArticle: 146799
What version of ISE/EDK are you using? Are you using a core or did you write your own interface to the DDR?
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