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Philippe <philippe.faes@gmail.com> writes:
> In Eclipse, you can check out a project in any location at all, and
> then point your Eclipse to that location.
> While the conventional place to check out projects would be ${HOME}/
> workspace/projectname, you can use any other location on your file
> system.
But it's not a relative pathname, is it? If you copy it or use it on a
system where the filesystem is mounted elsehere it will fail to find
it.
Petter
--
.sig removed by request.
Article: 146576
On 23 Mar, 01:10, "Pete Fraser" <pfra...@covad.net> wrote:
> I'm trying to dump eight hex values per line
> into a file, and can't work out how to do it.
>
> =A0 =A0for index in 0 to 127 loop
> =A0 =A0 for sample_sel in 0 to 7 loop
> =A0 =A0 =A0sample_val :=3D integer(scale * sin(phase(sample_sel)));
> =A0 =A0 =A0write ( sample_line, sample_val, RIGHT, 10);
> =A0 =A0 =A0phase(sample_sel) :=3D phase(sample_sel) + phase_inc(sample_se=
l);
> =A0 =A0 end loop;
> =A0 =A0 writeline ( ip_dat, sample_line );
> =A0 =A0end loop;
>
> does what I want, but with decimal values.
>
> If I change to:
> hwrite ( sample_line, sample_val, RIGHT, 10);
> or:
> write ( sample_line, to_hstring(sample_val), RIGHT, 10);
> it doesn't compile.
>
> Any thoughts?
>
> Thanks
>
> Pete
why not create an integer to string function:
=20
---------------------------------------------------------------------------=
---------
--Returns the size of the given integer as if it were a string in
the given Radix
=20
---------------------------------------------------------------------------=
---------
function get_int_length(x : integer; radix : positive range 2 to
36 :=3D 10) return integer is
variable temp : integer :=3D abs x;
variable len : integer :=3D 0;
begin
if x =3D 0 then
len :=3D 1;
end if;
while temp > 0 loop
temp :=3D temp / radix;
len :=3D len + 1;
end loop;
if x < 0 then
len :=3D len + 1; --add extra character for -ve sign
end if;
return len;
end function get_int_length;
----------------------------------------------
--Converts an integer to a string
----------------------------------------------
function int_to_string( x : integer; radix : positive range 2 to
36 :=3D 10) return string is
constant STRING_LEN : integer :=3D get_int_length(x, radix);
variable ret_string : string(1 to STRING_LEN);
--internal variables
variable temp : integer :=3D abs x;
variable temp_rem : integer;
begin
--downto to make sure the string isnt the wrong way
round.
for i in STRING_LEN downto 1 loop
--add -ve sign
if i =3D 1 and x < 0 then
ret_string(i) :=3D '-';
else
temp_rem :=3D temp rem radix;
case temp_rem is
when 0 =3D> ret_string(i) :=3D '0';
when 1 =3D> ret_string(i) :=3D '1';
when 2 =3D> ret_string(i) :=3D '2';
when 3 =3D> ret_string(i) :=3D '3';
when 4 =3D> ret_string(i) :=3D '4';
when 5 =3D> ret_string(i) :=3D '5';
when 6 =3D> ret_string(i) :=3D '6';
when 7 =3D> ret_string(i) :=3D '7';
when 8 =3D> ret_string(i) :=3D '8';
when 9 =3D> ret_string(i) :=3D '9';
when 10 =3D> ret_string(i) :=3D 'A';
when 11 =3D> ret_string(i) :=3D 'B';
when 12 =3D> ret_string(i) :=3D 'C';
when 13 =3D> ret_string(i) :=3D 'D';
when 14 =3D> ret_string(i) :=3D 'E';
when 15 =3D> ret_string(i) :=3D 'F';
when 16 =3D> ret_string(i) :=3D 'G';
when 17 =3D> ret_string(i) :=3D 'H';
when 18 =3D> ret_string(i) :=3D 'I';
when 19 =3D> ret_string(i) :=3D 'J';
when 20 =3D> ret_string(i) :=3D 'K';
when 21 =3D> ret_string(i) :=3D 'L';
when 22 =3D> ret_string(i) :=3D 'M';
when 23 =3D> ret_string(i) :=3D 'N';
when 24 =3D> ret_string(i) :=3D 'O';
when 25 =3D> ret_string(i) :=3D 'P';
when 26 =3D> ret_string(i) :=3D 'Q';
when 27 =3D> ret_string(i) :=3D 'R';
when 28 =3D> ret_string(i) :=3D 'S';
when 29 =3D> ret_string(i) :=3D 'T';
when 30 =3D> ret_string(i) :=3D 'U';
when 31 =3D> ret_string(i) :=3D 'V';
when 32 =3D> ret_string(i) :=3D 'W';
when 33 =3D> ret_string(i) :=3D 'X';
when 34 =3D> ret_string(i) :=3D 'Y';
when 35 =3D> ret_string(i) :=3D 'Z';
--something has gone very wrong. Kill simulation
when others =3D> report "Illegal option chosen in converting
integer to string" severity failure;
end case;
temp :=3D temp / radix;
end if;
end loop;
return ret_string;
end function int_to_string;
Article: 146577On Mar 23, 2:07=A0pm, Magne Munkejord <magnem...@yahoo.no> wrote: > Hi, > > Each address designates a 64 bit word in memory. > Are you sure about the FIFO's width? As far as I remember this was 128 > bits for read and write data. The command FIFOs width is 36. > > The DDR2 controller transmits 64 bits at rising and 64 bits at falling > edge of the clock, 128 bits per clock cycle. > > A burst size of 8 means 8x64 bits words burst length which is 4x128 bits > words in your data FIFOs (read or write) per read/write command. > > HTH, > > Magne Thanks for the reply, You are right, the data FIFO is 128 bits wide. In case of a burst length of 4, every write command would have 2x128 bits write (4x64 bits). If each address designates a 64 bit word in memory (which is what I thought), the addresses should be generated with an offset of 4 (since there are 4 64 bit words, each 64 bits corresponds to a location in memory), the addresses should progress like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation generated from MIG progresses the addresses with an offset of 8? Is it just to show writing and reading of the memory? Seeker...Article: 146578
Moving files around within your project is a no-brainer. Sigasi will
even update your Makefile if you wish.
And it is also no problem to move 'projects' around on your computer
(or network). You just have to point Eclipse to the new location.
Hendrik.
On Mar 23, 10:27=A0am, Petter Gustad <newsmailco...@gustad.com> wrote:
> Philippe <philippe.f...@gmail.com> writes:
> > In Eclipse, you can check out a project in any location at all, and
> > then point your Eclipse to that location.
> > While the conventional place to check out projects would be ${HOME}/
> > workspace/projectname, you can use any other location on your file
> > system.
>
> But it's not a relative pathname, is it? If you copy it or use it on a
> system where the filesystem is mounted elsehere it will fail to find
> it.
>
> Petter
> --
> .sig removed by request.
Article: 146579> Generally I use nedit and a whole bunch of perl scripts/java apps I've written > over the years. I'm not totally against eclipse. I use it with the Lattice mico32 > environment for instance. Similary, I use Textpad with perl scripts and a lot of tool customisation. > Regarding the Sigasi tool, the price on the website is 'within reason'. What's not > within reason, IMHO, is the licensing model. If I don't fork out every year it > will stop working. I would never even look at a tool that I can't get a perpetual > license for. If I develop a project with it then I want to be able to come back to > it again in five years if I have to regenerate the project from my archives. I started looking at Sigasi but stopped experimenting when I found out the price/ licensing model. NialArticle: 146580
Seeker wrote: > On Mar 23, 2:07 pm, Magne Munkejord <magnem...@yahoo.no> wrote: >> Hi, >> >> Each address designates a 64 bit word in memory. >> Are you sure about the FIFO's width? As far as I remember this was 128 >> bits for read and write data. The command FIFOs width is 36. >> >> The DDR2 controller transmits 64 bits at rising and 64 bits at falling >> edge of the clock, 128 bits per clock cycle. >> >> A burst size of 8 means 8x64 bits words burst length which is 4x128 bits >> words in your data FIFOs (read or write) per read/write command. >> >> HTH, >> >> Magne > > Thanks for the reply, > You are right, the data FIFO is 128 bits wide. > In case of a burst length of 4, every write command would have 2x128 > bits write (4x64 bits). If each address designates a 64 bit word in > memory (which is what I thought), the addresses should be generated > with an offset of 4 (since there are 4 64 bit words, each 64 bits > corresponds to a location in memory), the addresses should progress > like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation > generated from MIG progresses the addresses with an offset of 8? Is it > just to show writing and reading of the memory? > > Seeker... Could be, but I remember that a burst length of 8 is also an option in the MIG so maybe they made the testbench so that it would work for both options (4 and 8 burst length) or maybe the testbench is confused which option is set? (by "offset of 8" I assume you mean increments of 8.) MagneArticle: 146581
Hendrik <hendrik.eeckhaut@gmail.com> writes: > (or network). You just have to point Eclipse to the new location. That's one of the things I don't like: absolute pathnames. In my typical makefile based environment I don't have to change anything to point to the new location if I should switch back and forth between computers where the directory is mounted at different mount points since the paths are all relative. Pettr -- .sig removed by request.Article: 146582
You misunderstood. The only absolute path is in the user interface. If you move your project, you will also have to change parameters to point Emacs to the new location, be it a command line parameter. The paths in Makefiles do NOT depend on the location of the project. Hendrik. On Mar 23, 11:24=A0am, Petter Gustad <newsmailco...@gustad.com> wrote: > Hendrik <hendrik.eeckh...@gmail.com> writes: > > (or network). You just have to point Eclipse to the new location. > > That's one of the things I don't like: absolute pathnames. > > In my typical makefile based environment I don't have to change > anything to point to the new location if I should switch back and > forth between computers where the directory is mounted at different > mount points since the paths are all relative. > > Pettr > -- > .sig removed by request.Article: 146583
"backhus" <goouse99@googlemail.com> wrote in message news:932a8e33-617d-4f84-928a-2f9729b09105@g28g2000yqh.googlegroups.com... > which simulator do you use? Active-HDL 8.2 > Probably the compile options are set to some old VHDL standard or you > are using wrong or outdated libraries for the functions you intend to > use. I'm compiling with -2008. Thanks PeteArticle: 146584
Philippe <philippe.faes@gmail.com> writes:
> In Eclipse, you can check out a project in any location at all, and
> then point your Eclipse to that location.
Problem is that in Eclipse you don't seem to be able to specify
*project relative* paths for resources (aka project files), except via
user variables which is annoying. All paths are either absolute or
relative to the workspace.
As for the speed, once started up, Eclipse/Win32 runs with decent
performance fast even on my old laptop. Even closing it an restarting
is not too bad. The startup delay is due to the JavaVM I suppose.
I know (former) passionate Eclipse haters who have just switched due
to the impressive speed improvements in recent versions.
Disclaimer: I use Eclipse for certain C development only, so my
opinion might be impacted by behaviour specific to ARM Embedded
Workbench/CDT plugin features.
Regards
Marcus
--
note that "property" can also be used as syntactic sugar to reference
a property, breaking the clean design of verilog; [...]
(seen on http://www.veripool.com/verilog-mode_news.html)
Article: 146585"he" <he_novalid_addresse@arcor.de> wrote in message news:4ba86240$0$7658$9b4e6d93@newsspool1.arcor-online.net... > which textio-library are you using? if i remember correctly, > hread/hwrite can only be used with ieee.std_logic_textio.all; I'm using std.textio.all. I'll give the other library a try, but sample_val is an integer, so I didn't think I'd have to mess with std_logic stuff. Thanks PeteArticle: 146586
"Magne Munkejord" <magnemunk@yahoo.no> wrote in message news:hoa188$2opp$1@toralf.uib.no... > From my experiences from modelsim : > * hwrite works on std_logic_vector but requires the vector to be of "even > length", that is the length must be a multiple of 4. > * to_hstring doesn't work for std_logic_vector, you'll have to convert it > to a bit_vector first. Probably my problem is that sample_val is an integer. How to I print an integer as hex? Thanks PeteArticle: 146587
"Tricky" <trickyhead@gmail.com> wrote in message news:1fc70f4e-cd42-49cc-8d65-2a4b8d1eb032@d37g2000yqn.googlegroups.com... > why not create an integer to string function: [code supplied] Thanks. I'll try that. It's my first time using textio, and I just assumed some formatting control was provided somewhere, but that I was too dumb to find it. PeteArticle: 146588
I'm sorry, Kal and Ed, I should have been more specific. I know what the gates are, but they are not defined in the code anywhere. I am figuring I need to include a library where they will be defined, but I don't know which I should be using, or if any are even available in the Xilinx flow. I import the (verilog) benchmark, instantiate it in my VHDL toplevel, and when it is synthesized, I have 614 errors since the gates are not defined. I was hoping it would be something as simple as including a library. On 03/23/2010 12:47 AM, Muzaffer Kal wrote: > On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > <ed.mcgettigan@xilinx.com> wrote: > >> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> >> wrote: >>> I'm having a terrible time finding a solution to a library problem. >>> >>> I am implementing some IWLS benchmarks on a Spartan3e, and I need some >>> standard cells such as: >>> >>> AOI21X1 >>> AND3X1 >>> AND2X1 >>> NAND2X1 >>> >>> etc. >>> >>> Does anyone have a suggestion? Am I overlooking something simple? >>> >>> Thanks in advance. >>> -- >>> Jason Thibodeau >> >> The standard cell library should document the function of each these >> cells. Likely guesses are. >> >> AOI21X1 - 2-Input AND-OR with Inversion on inputs? >> AND3X1 - 3-Input AND >> AND2X1 - 2-Input AND >> NAND2X1 - 2-Input NAND >> >> etc... = etc... :-) >> >> Ed McGettigan > > If we had more info, we can make better guesses. The ports are > extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which > is OR-inverted with the third ie y = !((a0&a1) | b0). > One more thing which is again very helpful is to get the simulation > model of the standard cell library and use it without any timing as > the behavioral model. Synthesis tools do a pretty decent job of doing > the mapping. -- Jason Thibodeau www.jayt.orgArticle: 146589
Newbie here. I'm running a program that invokes a tcl file. I'm trying to execute the xilinx tcl commands from that tcl script. In the tcl script, i only have the following code. source $env(XILINX)/bin/xilinx-init.tcl But i received the following error when the script gets invoked: error reading package index file C:/Xilinx/10.1/ISE/bin/pkgIndex.tcl: load: Cannot match with any static package. Try "load_unsupported" to load dynamic packages into statically wrapped applications. error reading package index file C:/Xilinx/10.1/ISE/bin/pkgIndex.tcl: load: Cannot match with any static package. Try "load_unsupported" to load dynamic packages into statically wrapped applications. can't find package xilinx while executing "package require xilinx" (file "C:\Xilinx\10.1\ISE/bin/xilinx-init.tcl" line 30) invoked from within "source $env(XILINX)/bin/xilinx-init.tcl" ........... .... Anyone here with experience dealing with xilinx tcl commands? Any idea how to solve this? Please advise.... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 146590
Pete Fraser wrote: > "Magne Munkejord" <magnemunk@yahoo.no> wrote in message > news:hoa188$2opp$1@toralf.uib.no... > >> From my experiences from modelsim : >> * hwrite works on std_logic_vector but requires the vector to be of "even >> length", that is the length must be a multiple of 4. >> * to_hstring doesn't work for std_logic_vector, you'll have to convert it >> to a bit_vector first. > > Probably my problem is that sample_val is an integer. > How to I print an integer as hex? > > Thanks > > Pete > > It was in the original post, if you missed it: std_logic_vector(to_unsigned(sample_val, <length>)) make sure <length> is multiple of 4 if you intend to use it with hwrite.Article: 146591
On Mar 23, 6:19=A0am, Magne Munkejord <magnem...@yahoo.no> wrote: > Seeker wrote: > > On Mar 23, 2:07 pm, Magne Munkejord <magnem...@yahoo.no> wrote: > >> Hi, > > >> Each address designates a 64 bit word in memory. > >> Are you sure about the FIFO's width? As far as I remember this was 128 > >> bits for read and write data. The command FIFOs width is 36. > > >> The DDR2 controller transmits 64 bits at rising and 64 bits at falling > >> edge of the clock, 128 bits per clock cycle. > > >> A burst size of 8 means 8x64 bits words burst length which is 4x128 bi= ts > >> words in your data FIFOs (read or write) per read/write command. > > >> HTH, > > >> Magne > > > Thanks for the reply, > > You are right, the data FIFO is 128 bits wide. > > In case of a burst length of 4, every write command would have 2x128 > > bits write (4x64 bits). If each address designates a 64 bit word in > > memory (which is what I thought), the addresses should be generated > > with an offset of 4 (since there are 4 64 bit words, each 64 bits > > corresponds to a location in memory), the addresses should progress > > like 0x000000, 0x000004, 0x00008 and so on. Then why the simulation > > generated from MIG progresses the addresses with an offset of 8? Is it > > just to show writing and reading of the memory? > > > Seeker... > > Could be, but I remember that a burst length of 8 is also an option in > the MIG so maybe they made the testbench so that it would work for both > options (4 and 8 burst length) or maybe the testbench is confused which > option is set? > (by "offset of 8" I assume you mean increments of 8.) > > Magne Maybe the testbench writer was just lazy and an offset of 8 would "work" for either case because you never overwrite any data even though in the burst of 4 case you skip over half the available memory? - GaborArticle: 146592
On Mar 21, 4:36=A0pm, Patrick Maupin <pmau...@gmail.com> wrote: > On Mar 20, 3:17=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > On Mar 20, 2:52=A0am, modimo <g.mod...@gmail.com> wrote: > > > > On 20 Mar, 04:28, Mawa_fugo <cco...@netscape.net> wrote: > > > > > On Mar 19, 10:05=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > > > On Mar 19, 3:55=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > > > On Mar 19, 2:17=A0pm, John_H <newsgr...@johnhandwork.com> wrote= : > > > > > > > > On Mar 19, 3:01=A0pm, Mawa_fugo <cco...@netscape.net> wrote: > > > > > > > > > Hi all, > > > > > > > > > There's an instance of BRAM in spartan3 device. =A0I used c= oregen with > > > > > > > > *.coe file to init the data for the memory module > > > > > > > > > My question, is there anyway to edit the mcs file (we use f= latform > > > > > > > > flash for config) to change the content of init data ..."wi= thout spend > > > > > > > > 20 minutes to re-run the whole ISE processes > > > > > > > > > Thanks, > > > > > > > > "There's an app for that." > > > > > > > >http://www.xilinx.com/products/ipcenter/dr_dt_data2mem.htm > > > > > > > Thanks for the link, I do search around and all route to that p= age.. > > > > > > But I'm not sure I can get anything, > > > > > > Is there any download-able thing ? > > > > > > > Thanks > > > > > > Have you looked in your Xilinx directories for your installed ISE= ? > > > > > > From a random sell sheet: > > > > > > ISE=99 WebPack FPGA Design Tool Suite > > > > > =95 Timing driven FPGA hardware implementation tools > > > > > =95 Design entry, synthesis and verification capabilities > > > > > =95 Data2MEM =96 application for loading on-chip memory > > > > > > It looks like it's included standard. > > > > > Yes, I see that execute file data2mem, look like old day command > > > > line. =A0Guessing it's just another non-user-friendly Xilnx apps ;-= ) > > > > > Thanks > > > > Console apps are user-friendly matter of who their friends are ;) > > > > Some examples should be helpfulhttp://home.mnet-online.de/al/BRAM_Bit= streams.html > > > > There is also app for updating picoblaze code through jtag that also > > > could be useful after some modifications.http://forums.xilinx.com/xln= x/board/message?board.id=3DPicoBlaze&messag... > > > In my app, the data width is 1 bit, with 128k depth, that means I have > > 8 BRAM16 inst > > > ---------below is my bmm file > > > ADDRESS_SPACE mem_module RAMB16 [0x00000000:0x00001FFFF] > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B76/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y12; > > END_BUS_BLOCK; > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B79/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y14; > > END_BUS_BLOCK; > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B82/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y13; > > END_BUS_BLOCK; > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B85/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y15; > > END_BUS_BLOCK; > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B88/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y17; > > END_BUS_BLOCK; > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B91/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y18; > > END_BUS_BLOCK; > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B94/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y19; > > END_BUS_BLOCK; > > > BUS_BLOCK > > XLXI_2/MEM_MODULE/BRAM_MODULE_INST/B97/RAMB16BWER [0:0] =A0PLACED =3D > > X2Y16; > > END_BUS_BLOCK; > > > END_ADDRESS_BLOCK; > > > ----below is the command line I try to see if I can extract the data > > from existing bit file > > > $ data2mem -bm mybmmfile.bmm -bt existingbitfile.bit > log.txt > > > -------- But it always gives the below error > > > ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE > > 'mem_module'. > > =A0 =A0 ADDRESS_SPACE was defined as 0x00020000 bytes, but the > > ADDRESS_RANGE total is 0x00004000 bytes. > > > ---Then I try to change the address space to > > > ADDRESS_SPACE mem_module RAMB16 [0x00000000:0x000003FFF], > > > ---It then gives no error but the log.txt file is just a blank, > > nothing show up > > > ---I wonder if this tool can't handle data width with 1 bit wide???? > > The tool doesn't have a clue. =A0Just lie to it and tell it your RAM is > 8 bits wide. Okie, I can lie it about the address, but how can I "lie" it about the data ? Let me guess, I will have to tell it in byte, by concatenate 8 bits together ? TIAArticle: 146593
"Magne Munkejord" <magnemunk@yahoo.no> wrote in message news:hoad0m$4g$1@toralf.uib.no... > It was in the original post, if you missed it: > std_logic_vector(to_unsigned(sample_val, <length>)) > > make sure <length> is multiple of 4 if you intend to use it with hwrite. That worked great. I shouldn't read / respond to posts at 4 am. Thanks PeteArticle: 146594
D Yuniskis <not.going.to.be@seen.com> wrote >I don;t recall yours as showing much age! :> Though it *has* been >a few years (and I am always amazed at just how *quick* things like >this can change ;-) You're very kind :) My new girl is looking after me well :) Another reason I don't do FPGA design anymore ;) >Wow! I wouldn't have thought them to still be available! I've >an XC4xxx in a design that I had abandoned figuring it would be >impossible to get... I think the 4k devices are pretty well available. Also there is a huge (vast) surplus component market out there. You could keep yourself stocked in 1990s parts for ever. They gradually get more expensive, and are rarely available right there when you want them (the stocks appear at random times) and you can't get real production volumes, but "low cost" and "Xilinx" was never said in the same sentence :) The top end 4k devices were about $1500 when I looked at using one for building a replacement for a UART (one of the TMS9900 family) which TI stopped making but there were many 1000s in the field and for some bizzare reason they had defective silicon which made them all fail after some years. I lined-up an FPGA designer for the customer on that job... That would have been a fun project - building a drop-in replacement for a fairly complex uP peripheral chip. Obviously one would not be implementing stuff like SDLC... >So, your attitude is "move on to new tools *if* the need arises"? Actually, my attitude would be to bit-bang it with an Atmel uC. Every single FPGA design I ever did could have been done with a fast simple uC, with a bit of imagination - except the ASIC prototyping projects, obviously. Might need a few chips on the outside but the learning curve of assembler programming is maybe 1% of the l.c. on FPGA design. And you don't have to re-learn everything every time the FPGA vendor turns everything upside down in trying to keep ahead of the competition. I decided long ago that FPGAs are a technology for "must get there now before the competition no matter what the long term cost is" and the long term cost is that after a few years you cannot maintain the design because after the original designer has left nobody will want to touch it. And the later tools will not import the original designs, which is really great.... in fact that happened right after Xilinx dropped Viewlogic as schematic entry. I had loads of correspondence with them at the time but their view was "tough... move on". All schematics had to be re-drawn in the new tool. You could keep VL running somewhere but if the dongle broke, everything was orphaned. Luckily, as I said, the dongle got cracked ;)Article: 146595
On Mar 22, 6:36=A0pm, Eric Smith <space...@gmail.com> wrote: > On Mar 22, 2:36=A0pm, "M. Norton" <remill...@gmail.com> wrote: > > > On whole I agree with you, however let's be realistic, the learning > > curve for Emacs is incredibly steep. > > A steep learning curve is a Good Thing. =A0If it was shallow, it would > take you a very long time to learn it. Alright, you got me. :-) I used the phrase in a vernacular way without being terribly precise. Let me be specific. With emacs, coming at it with little to no prior knowledge, there are a great many skills that need to be acquired to become proficient with merely editing text, let alone achieving the productivity required to achieve success in a reasonable amount of time for a complex HDL project, in particular compared to a text editor whose interface that, through use of various other common text editing utilities and applications, might be relatively intuitive. With Sigasi, at least upon light inspection, I thought it had a great many features that might be useful for the casual HDL designer without the necessity of becoming fully proficient with emacs. I believe emacs is probably the superior environment, not the least of which is the FOSS nature of the software compared with the Sigasi, but it is not a trivial task to learn it. I didn't try Sigasi with anything very large, and I did not try to customize it. I stepped through the tutorial/feature list, thought "hey that's interesting" and went back to my development in emacs. I would hope that the Sigasi developers are reading this thread and noticing all the complaints from others and considering ways to mitigate those experiences. Still simply because I do not need the features at the price doesn't mean no one would find value with it, which is all I was trying to express originally. As for the "steep learning curve" comment, I did a little research on Google and it's an interestingly common mis-use of the concept so I'll have to find some other way of saying what I intended to say :-). Mark NortonArticle: 146596
On Mar 23, 8:17=A0am, Jason Thibodeau <jason.p.thibod...@gmail.com> wrote: > I'm sorry, Kal and Ed, I should have been more specific. > > I know what the gates are, but they are not defined in the code > anywhere. I am figuring I need to include a library where they will be > defined, but I don't know which I should be using, or if any are even > available in the Xilinx flow. > > I import the (verilog) benchmark, instantiate it in my VHDL toplevel, > and when it is synthesized, I have 614 errors since the gates are not > defined. > > I was hoping it would be something as simple as including a library. > > On 03/23/2010 12:47 AM, Muzaffer Kal wrote: > > > > > On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > > <ed.mcgetti...@xilinx.com> =A0wrote: > > >> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> > >> wrote: > >>> I'm having a terrible time finding a solution to a library problem. > > >>> I am implementing some IWLS benchmarks on a Spartan3e, and I need som= e > >>> standard cells such as: > > >>> AOI21X1 > >>> AND3X1 > >>> AND2X1 > >>> NAND2X1 > > >>> etc. > > >>> Does anyone have a suggestion? Am I overlooking something simple? > > >>> Thanks in advance. > >>> -- > >>> Jason Thibodeau > > >> The standard cell library should document the function of each these > >> cells. =A0Likely guesses are. > > >> AOI21X1 - 2-Input AND-OR with Inversion on inputs? > >> AND3X1 - 3-Input AND > >> AND2X1 - 2-Input AND > >> NAND2X1 - 2-Input NAND > > >> etc... =3D etc... :-) > > >> Ed McGettigan > > > If we had more info, we can make better guesses. The ports are > > extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which > > is OR-inverted =A0with the third ie y =3D !((a0&a1) | b0). > > One more thing which is again very helpful is to get the simulation > > model of the standard cell library and use it without any timing as > > the behavioral model. Synthesis tools do a pretty decent job of doing > > the mapping. > > -- > Jason Thibodeauwww.jayt.org Why don't you create a standard cell library yourself? In verilog it should be pretty straightforward.Article: 146597
On Mar 23, 1:44=A0am, Eric Smith <space...@gmail.com> wrote: > Think about it. =A0When you graph the learning curve, what are the axes? uhhh.... "steep learning curve" is a bad thing. The axis aren't knowledge gained versus time but knowledge required versus competence. It's not like a "quantum improvement" where a quanta is the lowest measurable unit. Learning curves haven't been misused in this engineer's opinion. Perhaps until now.Article: 146598
On Mar 22, 3:43=A0pm, Philippe <philippe.f...@gmail.com> wrote: > Integrated Development Environments (IDEs) have long been the primary > tool for software engineers. Like an airplane cockpit, an IDE is the > control center from which the engineer accesses all of the data and > tools that he needs. IDEs, and especially Eclipse, have proven to be > extensible, open, high quality platforms. > > However, until now, IDEs have not been popular in hardware development > circles. This is partly because many of the available IDEs for > hardware development have not lived up to the potential of IDEs that > is typical in the software world. Instead, IDEs tend to be overly > complex, closed, and they lock the customer in. > > Today, though, Eclipse is finally gaining traction among EDA > (electronic design automation) and FPGA companies. One such EDA > company, Sigasi, has just released the first commercial VHDL plugin > for Eclipse. Now, at last, hardware design teams can use Eclipse as a > basis for their own customized IDEs, based on the commercial and open- > source plugins that they need in their central cockpit for hardware > design. > > I've published a white paper on this subject.http://www.sigasi.com/conten= t/why-hardware-designers-should-switch-ec... > I'd be interested to know what you guys think. > > kind regards > > Philippe Faes > Founding CEO Sigasihttp://www.sigasi.com Any plans to support the other half of hardware developers in the Verilog camp? Most of my projects are either all Verilog or mixed VHDL / Verilog. For just code entry I either use the chip-vendors brain-dead editor, which at least highlights known device primitive names so I don't need the Libraries Guide every time I instantiate them, or I use MED with my own language customizations. Regards, GaborArticle: 146599
On 03/23/2010 09:47 AM, jkljljklk wrote: > On Mar 23, 8:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com> > wrote: >> I'm sorry, Kal and Ed, I should have been more specific. >> >> I know what the gates are, but they are not defined in the code >> anywhere. I am figuring I need to include a library where they will be >> defined, but I don't know which I should be using, or if any are even >> available in the Xilinx flow. >> >> I import the (verilog) benchmark, instantiate it in my VHDL toplevel, >> and when it is synthesized, I have 614 errors since the gates are not >> defined. >> >> I was hoping it would be something as simple as including a library. >> >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote: >> >> >> >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan >>> <ed.mcgetti...@xilinx.com> wrote: >> >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> >>>> wrote: >>>>> I'm having a terrible time finding a solution to a library problem. >> >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and I need some >>>>> standard cells such as: >> >>>>> AOI21X1 >>>>> AND3X1 >>>>> AND2X1 >>>>> NAND2X1 >> >>>>> etc. >> >>>>> Does anyone have a suggestion? Am I overlooking something simple? >> >>>>> Thanks in advance. >>>>> -- >>>>> Jason Thibodeau >> >>>> The standard cell library should document the function of each these >>>> cells. Likely guesses are. >> >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs? >>>> AND3X1 - 3-Input AND >>>> AND2X1 - 2-Input AND >>>> NAND2X1 - 2-Input NAND >> >>>> etc... = etc... :-) >> >>>> Ed McGettigan >> >>> If we had more info, we can make better guesses. The ports are >>> extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which >>> is OR-inverted with the third ie y = !((a0&a1) | b0). >>> One more thing which is again very helpful is to get the simulation >>> model of the standard cell library and use it without any timing as >>> the behavioral model. Synthesis tools do a pretty decent job of doing >>> the mapping. >> >> -- >> Jason Thibodeauwww.jayt.org > > Why don't you create a standard cell library yourself? In verilog it > should be pretty straightforward. That's what I will do if I can't find a solution, but I'm hoping there is a less time-consuming approach. -- Jason Thibodeau
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