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Pete Fraser wrote: > I have an evaluation copy of Active-HDL, and am having > some (presumably) newbie issues with it. > > I went through their VHDL tutorial, but it has all sorts > of visual editors in the flow that I'm not interested in. > I tried importing my Modelsim XE project, and that > sort of worked, but it didn't convert my "do" file. > > Could anybody point me to a simple "do" file that will > compile a vhdl test bench, the UUT and a few supporting > files, open a waveform window and add the signal > configuration to the window, fire up the sim, and run > for a period specified in the file. Can I do this without > messing about with workspaces and projects? > Try something like this alib lib amap work lib acom -dbg file.vhd acom -dbg file_tb.vhd asim tb run -all #or of course run 100 ns If you want to run the commands stand-alone, then you need to put the above commands in a tcl file and do: vsimsa -tcl commands.tcl vsimsa doesn't allow a gui. In theory you can launch a similar script with vsim -gui -tcl "script" but I can't get that to work. regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated.Article: 146201
Hi Pete,
here's my personal methodology. I don't use workspaces either. Well, I
just use them to set up a reference point, allowing all other source
files, scripts etc. to use relative paths. This way my customers can
install the deliverables anywhere they want. It just works.
1)
In the workspace directory I have a file called 'setup.do' which
contains just this one line.
do ..\..\..\scripts\active_hdl\setup.do
2)
In the above mentioned setup.do file in the scripts directory, I have
something like this
setenv TEST_CASE_ROOT "$DSN\..\..\..\verify\scenarios\vhdl"
setenv TEST_CASE "short_n_long.vhd"
alias compile_test_case {acom -quiet -dbg -work pcie_stimgen_lib
$TEST_CASE_ROOT\$TEST_CASE;echo "$TEST_CASE compiled"}
alias load_sim {asim -advdataflow pcie_wb_01_tb bhv}
alias make_project {do $DSN\..\..\..\scripts\active_hdl\make_project.do}
alias run_sim {asim -advdataflow +notimingchecks pcie_wb_01_tb bhv;
do $DSN\..\..\..\scripts\active_hdl\core_waves.do;run -all}
$DSN is a useful variable. It refers to the work-space directory.
3)
core_waves.do looks something like this:
add wave -noreg -logic {/DUT/U2/i_clk_pcie}
add wave -noreg -logic {/DUT/U2/i_rst_n}
add wave -noreg -hexadecimal -literal -unsigned {/DUT/U2/i_cfg_bus_num}
add wave -noreg -hexadecimal -literal -unsigned {/DUT/U2/i_cfg_dev_num}
add wave -noreg -hexadecimal -literal -unsigned {/DUT/U2/i_cfg_func_num}
add wave -noreg -logic {/DUT/U2/i_ctl_en_no_snoop}
add wave -noreg -logic {/DUT/U2/i_ctl_link_disable}
4)
The make_project.do file (aliased to 'make_project' from the console
window) has lines like:
alias VHDL_CC "acom -quiet -dbg -work $WORKLIB"
alias VLOG_CC "vlog -quiet -l ovi_ecp2 -l pmi_work -work $WORKLIB"
setenv PROJECT_ROOT "$DSN\..\..\.."
VLOG_CC -f $PROJECT_ROOT/scripts/active_hdl/verilog.lst
VHDL_CC $PROJECT_ROOT/verify/testbench/packages/vhdl/util_tb-p.vhd
VHDL_CC $PROJECT_ROOT/verify/testbench/packages/vhdl/util_tb-pb.vhd
VHDL_CC $PROJECT_ROOT/impl/top/vhdl/pcie_wb_01-p.vhd
VHDL_CC $PROJECT_ROOT/impl/units/pcie_x1_top/vhdl/pcie_x1_top_sim.vhd
VHDL_CC $PROJECT_ROOT/impl/memories/vhdl/ram_64kx8.vhd
. . . . .
echo "...done"
5)
In the console, I do the following
- load the workspace
- type in 'do setup.do'
- type in the aliases from 2) as required
I'm not really an activeHDL user. I have their Riviera tool instead. But
some of my customers use activeHDL and need an activeHDL delivery at
project hand-over. I have a few perl/java scripts that automatically
generate most of the above out of my riviera design flow.
I haven't tried the analogue view you are referring to. Try selecting
the menu with right-mouse-button. I think you can set up font size etc.
here.
Pete Fraser schrieb:
> I have an evaluation copy of Active-HDL, and am having
> some (presumably) newbie issues with it.
>
> I went through their VHDL tutorial, but it has all sorts
> of visual editors in the flow that I'm not interested in.
> I tried importing my Modelsim XE project, and that
> sort of worked, but it didn't convert my "do" file.
>
> Could anybody point me to a simple "do" file that will
> compile a vhdl test bench, the UUT and a few supporting
> files, open a waveform window and add the signal
> configuration to the window, fire up the sim, and run
> for a period specified in the file. Can I do this without
> messing about with workspaces and projects?
>
> I really like the looks of the interface, and the speed,
> but I seem to have a minor issue with analog displays.
> I can select a single bus, and allow the software to
> determine the range for analog display, but when I try
> doing this on multiple busses, the software comes up
> with a ridiculously high gain and clips the waveforms.
> It does this even if all the busses have the same range.
>
> Any suggestions?
>
> Also, is there a more appropriate forum to ask these
> sorts of questions? I couldn't find an Active-HDL forum.
> I'll try phoning the FAE, but I thought I'd get a head
> start by asking here.
>
> Thanks
>
> Pete
>
>
>
Article: 146202On Mar 8, 4:40=A0am, pinkisntwell <pinkisntw...@gmail.com> wrote: > I'm using Quartus and I'm trying to compile a SignalTap Logic Analyzer > file with my project. No matter what I do the only indication I get is > "Please compile the project to continue". I have tried compiling and > recompiling to no avail. Any help? You might be downloading incorrect sof. If you are using the sof programmer built into the signaltap gui, it doesn't change the filename when you create a new rev.Article: 146203
In article <20100308094342.f7fa8e54.steveo@eircom.net>, Ahem A Rivet's Shot <steveo@eircom.net> wrote: >On Mon, 8 Mar 2010 07:45:53 +0000 (UTC) >johnf@panix.com (John Francis) wrote: > >> In article <20100307214004.5b5fc8b4.steveo@eircom.net>, >> Ahem A Rivet's Shot <steveo@eircom.net> wrote: >> >On Sun, 7 Mar 2010 18:59:43 +0000 (UTC) >> >johnf@panix.com (John Francis) wrote: >> > >> >> have come across the practice in other languages). In fact C has to >> >> perform different calculations to evaluate the address of an element >> >> a[i][j], depending on how a was defined (int a[4][5], or int** a). >> >> The sizeof operator also knows something about array types. >> > >> > If a is defined as int **a then a[i][j] is not valid at all. >> >> Rubbish. a[i][j] is a perfectly legal term in both cases I supplied, >> and has a well-defined way of calculating the address. > > Er OK - you're right int **a is a pointer to a pointer to integers >so the first offset works in terms of sizeof(int *) and the second in terms >of sizeof(int). True iff a is defined as int**. Note that sizeof(a[n]) returns different values for the two declarations; for the two-dimensional array the elements of a are not of type (int *); they are of an anonymous datatype (a vector of 5 ints).Article: 146204
-jg wrote: > On Mar 3, 12:22 am, Symon <symon_bre...@hotmail.com> wrote: >> This lot seems to be revealing a bit more about their stuff. >> >> http://www.mercurynews.com/breaking-news/ci_14493616 >> > > A better overview is here > http://www.eetasia.com/ART_8800599499_499495_NT_b33fb563_2.HTM > > Some of what Tabula say, reads more like a patent dance, than any > technical explanation. > > So, it is locally 1.6GHz, with time-sliced threads. > It might save Logic and routing, but it will have no config-memory > saving, and it ADDS the complexity of > rapid config multiplex. (not to mention power impacts) > Yeah. If you have a very linear procedure to perform, a processor (CPU) can save an enormous amount of hardware, but at a severe time penalty. But, the basic idea is kind of the same, share hardware and do the task in smaller pieces, sequentially. maybe this Tabula concept is trying to make a finer-grain move in that direction. > We already have Achronix climing 1.5GHz PLDs since 2008, and XMOS > have 400-500Mhz hard-time-sliced cores shipping also. > This sounds more interesting, and may be a more solid shift in technology. > Tabula have some rather quaint terminology, as they try to spin what > they do, but designers have always tried to do more serially & > pipeline, to save resource, if they can. > > It seems their SW will do the 'thread slice & dice' for you, and that > may be the critical point. > > If that works, and you can debug it, it could be useful. If it fails, > it will fail in a tangle. Definitely. I don't understand what they are trying to do well enough to even know how hard this will be, but the debugging does sound quite messy. Also, I suspect there are a variety of tasks where the Tabula would be so totally a poor fit. I make a line of products that have multiple quadrature encoder counters in FPGAs. I've been thinking that due to the digital filtering of the inputs that is required, I could time multiplex the logic of these counters pretty easily and save a bunch of space. The filtering runs at 1 MHz! But, I could just as easily figure out how to do this in the HDL of my choice, with just a little thinking. JonArticle: 146205
On Mar 6, 9:41=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Mar 5, 4:53=A0pm, Andy Peters <goo...@latke.net> wrote: > > > > > It turns out that it is reasonable to create one workspace for an FPGA > > project and within this workspace create a "design" for the > > subentities and the top level. If you let it use the design name as > > the working library for the design, then as long as you "use" the > > library in a higher-level source, that source can see those other > > libraries. > > Why do you think that you need to segregate the library that the > source files get compiled into? =A0In other words, what is wrong with > compiling everything into 'work'? =A0That's not a source file, it's an > intermediate folder(s) that gets created along the way to doing what > you need to have done. =A0What do you gain by trying to have tidy > intermediate folders? As I said, I have always just dumped everything into 'work' without thinking too much about it, mainly because it always just worked. I thought about using separate libraries as a sop to how Active-HDL organizes its workspaces. > Having a separate library helps you avoid name clashes, but for things > that you're developing yourself this is more easily avoided by > considering some of the following points: > - Question the validity of why you have two things named the same > (presumably doing the same thing) No issues with namespaces here. I've adopted a simple prefix nomenclature for things that hopefully mitigates any potential clashes. > > Now I'm thinking that the usual method of doing: > > > =A0 =A0 u_foo : entity work.foo port map (bar =3D> bar, bletch =3D> ble= tch); > > > might be better as: > > > =A0 =A0 u_foo : entity foo.foo port map (bar =3D> bar, bletch =3D> blet= ch); > > > The other option is to create a package with a component definition > > for foo, and analyze that package into the foo library, so the > > instantiation can be: > > > =A0 =A0 u_foo : foo port map (bar =3D> bar, bletch =3D> bletch); > > > I really don't know which is "better." > > Neither one is particularly good in my opinion. =A0The reasons against > the first approach I've mentioned above (i.e. what do you really get > for not simply compiling everything into 'work'?). =A0The only place > I've found a component declaration to be useful is when you would like > to use a configuration to swap things out and about. =A0The only time > I've found configurations to be useful really is when the VHDL source > is not really under my control (such as when a PCBA model is generated > by a CAD tool). I agree: I never use component declarations except to work around other tool issues (like with the Xilinx EDK and how it apparently analyzes things into particular non-work libraries). > With a component declaration, you still have to decide where to put > that declaration. =A0The best place is in the source file with the > entity so that changes to one are more likely to get changed in both > places. =A0Given that, I don't see how components will help you manage > anything better....my two or three cents Those component declarations I've described are in a package that's in the same source file as the entity. I think I need to simply stop using the Active-HDL GUI and do the command-line thing. -aArticle: 146206
On Mar 9, 7:25=A0am, Jon Elson <jmel...@wustl.edu> wrote: > -jg wrote: > I make a line of products that have multiple quadrature encoder counters > in FPGAs. =A0I've been thinking that due to the digital filtering of the > inputs that is required, I could time multiplex the logic of these > counters pretty easily and save a bunch of space. =A0The filtering runs a= t > 1 MHz! =A0But, I could just as easily figure out how to do this in the HD= L > of my choice, with just a little thinking. If you have spare BRAM, that can easily create many time-sliced counters, with a simple add/subt. At a guess, a Xmos part could likely manage ~32 x 32 bit quad counters, at 1MHz poll rates. -jgArticle: 146207
On Mar 8, 6:53=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > rickman <gnu...@gmail.com> writes: > > I find the GUI will save me a lot of typing when instantiating > > modules. =A0I use the "generate test bench" feature to build a file > > with the meat and potatoes in it and I copy that to the higher level > > module. > > Ahh, I use VHDL-mode in Emacs for that, which is why I haven't missed > it :) Are you saying that Emacs understands VHDL well enough to build a test bench for you? Will it also build a component declaration or instantiation automatically? These three things could be automated, but I have never taken the time to do it. Making it part of the editor makes perfect sense. RickArticle: 146208
On Mar 8, 7:04=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > KJ <kkjenni...@sbcglobal.net> writes: > > I guess that's a point in its favour (assuming I can't "convert" the > incomers to Emacs :) You can convert me. I just need to know that it is an advantage to switch. RickArticle: 146209
On Mar 8, 1:25=A0pm, Jon Elson <jmel...@wustl.edu> wrote: > -jg wrote: > > On Mar 3, 12:22 am, Symon <symon_bre...@hotmail.com> wrote: > >> This lot seems to be revealing a bit more about their stuff. > > >>http://www.mercurynews.com/breaking-news/ci_14493616 > > > A better overview is here > >http://www.eetasia.com/ART_8800599499_499495_NT_b33fb563_2.HTM > > > =A0Some of what Tabula say, reads more like a patent dance, than any > > technical explanation. > > > =A0So, it is locally 1.6GHz, with time-sliced threads. > > It might save Logic and routing, but it will have no config-memory > > saving, and it ADDS the complexity of > > rapid config multiplex. (not to mention power impacts) > > Yeah. =A0If you have a very linear procedure to perform, a processor (CPU= ) > can save an enormous amount of hardware, but at a severe time penalty. > But, the basic idea is kind of the same, share hardware and do the task > in smaller pieces, sequentially. =A0maybe this Tabula concept is trying t= o > make a finer-grain move in that direction.> =A0We already have Achronix c= liming 1.5GHz PLDs since 2008, and XMOS > > have 400-500Mhz hard-time-sliced cores shipping also. > > This sounds more interesting, and may be a more solid shift in technology= .> =A0Tabula have some rather quaint terminology, as they try to spin what > > they do, but designers have always tried to do more serially & > > pipeline, to save resource, if they can. > > > =A0It seems their SW will do the 'thread slice & dice' for you, and tha= t > > may be the critical point. > > > =A0If that works, and you can debug it, it could be useful. If it fails= , > > it will fail in a tangle. > > Definitely. =A0I don't understand what they are trying to do well enough > to even know how hard this will be, but the debugging does sound quite > messy. =A0Also, I suspect there are a variety of tasks where the Tabula > would be so totally a poor fit. > > I make a line of products that have multiple quadrature encoder counters > in FPGAs. =A0I've been thinking that due to the digital filtering of the > inputs that is required, I could time multiplex the logic of these > counters pretty easily and save a bunch of space. =A0The filtering runs a= t > 1 MHz! =A0But, I could just as easily figure out how to do this in the HD= L > of my choice, with just a little thinking. Multiplexing things like counters is not very efficient because of the granularity. A counter is no more complex in an FPGA than a 2 input mux. If you add a mux to share a counter in two processes you gain nothing. If you share a larger logic block then you can start to see some gains. That is in essence what a CPU does. It multiplexes a huge number of logic and arithmetic operations using the enormous muxes built into a RAM (which are essentially free, unlike in FPGAs. More appropriate might be doing your calculations bit serially. Often the limiting constraint on a design is the number of LUTs while FFs are sitting around collecting dust. A counter can be done bit serially with only a few more FFs and fewer LUTs than the parallel approach... if you have the time. The tabula approach seems to be the opposite of this where they multiplex the logic between fixed registers. So you can use the same registers and replace the logic. My expectation is that they will develop a methodology of some sort to allow this to be debugged. But I expect this won't be that much different from regular logic in an FPGA. They will need to give clear examples of how to code an HDL for this and you follow the examples. Then your simulation should catch most issues. RickArticle: 146210
On Mar 8, 1:32=A0pm, rickman <gnu...@gmail.com> wrote: > On Mar 8, 6:53=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > rickman <gnu...@gmail.com> writes: > > > I find the GUI will save me a lot of typing when instantiating > > > modules. =A0I use the "generate test bench" feature to build a file > > > with the meat and potatoes in it and I copy that to the higher level > > > module. > > > Ahh, I use VHDL-mode in Emacs for that, which is why I haven't missed > > it :) > > Are you saying that Emacs understands VHDL well enough to build a test > bench for you? It will create a skeleton for you. >=A0Will it also build a component declaration or > instantiation automatically? =A0These three things could be automated, > but I have never taken the time to do it. =A0Making it part of the > editor makes perfect sense. The skeleton has a nice header, an instance of the DUT, signal declarations for all DUT I/O and a simple clock generator. Of course you have to create your own stimulus and add instantiations of other models as necessary. -aArticle: 146211
Thankyou everybody for your help so far. I seem to be confused by the waveform viewer now. My typical debug cycle in Modelsim XE uses wave.do. I will load the sim, run wave.do to bring up the waveforms I'm interested in, then run the sim. If the waveforms point to mistakes I've made, I'll often want to add a few more waveforms, save the updated wave.do file, then re-start the sim using the new wave.do. I can't work out how to do the equivalent in Active-HDL. My modesim wave.do seems to work in Aldec, but I can't see how to save it when I've added waveforms. I can't even work out how to add waveforms reliably; sometimes dragging signals from the structure pane to an existing waveform viewer opens a new viewer window. I'm also not sure which viewer I'm using (advanced or standard), or how I control that. Sometimes the title bar says "untitled.awc", and sometimes "untitled.asdb". Help, I haven't felt this clueless in a long time. TIA PeteArticle: 146212
Joe Pfeiffer wrote: > Charles Richmond <frizzle@tx.rr.com> writes: >> ... but do *not* forget that when an integer is added to a pointer, >> that integer is "scaled" by the length associated with that >> pointer. So if "a" is a pointer to a four byte integer, then "a+1" >> actually adds *four* to the pointer. The integer "1" is scaled by the >> length of the object pointed to by "a". > > That fact took me several painful days to learn. I had (in a project I > don't remember, for reasons I don't remember) used the + syntax > dereferencing a buffer of integers, and had scaled it myself. Which > meant, of course, that everything seemed fine for a ways into the > buffer, then mysteriously segfaulted. > > Hmmm... I've got quite a few like that, with vividly remembered bugs in > totally forgotten projects. This scaling of an integer when added to a pointer... is fundamental to the way C arrays and the array operator works. -- +----------------------------------------+ | Charles and Francis Richmond | | | | plano dot net at aquaporin4 dot com | +----------------------------------------+Article: 146213
Ahem A Rivet's Shot wrote:
> On Sun, 7 Mar 2010 18:59:43 +0000 (UTC)
> johnf@panix.com (John Francis) wrote:
>
>> In article <20100307143020.fcc7e3df.steveo@eircom.net>,
>> Ahem A Rivet's Shot <steveo@eircom.net> wrote:
>>> On Sun, 07 Mar 2010 07:48:01 -0500
>>> Greg Menke <gusenet@comcast.net> wrote:
>>>
>>>> Ahem A Rivet's Shot <steveo@eircom.net> writes:
>>>>> The C subscript operator does do nothing other than adding
>>>>> two numbers and dereferencing the result, that last action is rather
>>>>> important. The validity of constructs like 2[a] and *(2+a) make this
>>>>> clear - as does the equivalence of a and &(a[0]) or of *a and a[0]
>>>>> where a is a pointer.
>>>> Yet when dereferencing arrays of rank >= 2, dimensions are
>>>> automatically incorporated into the effective address, so its not
>>>> quite equivalent to a simple addition of pointer and offset.
>>> There is a way to regard it as such - consider a[x][y] as being
>>> equivalent to *(a[x] + y) where we regard a[x] as devolving into a
>>> pointer to a row of the array. But yes multidimensional array support is
>>> a little more involved than single dimensional array support. It's still
>>> not a proper type though.
>> That's all very well, but in fact no C implementation of which I am
>> aware uses dope vectors when allocating multidimensional arrays. (I
>
> Indeed they don't - it is simply a matter of how you interpret the
> partial construct a[x] when a is declared as a two dimensional array - one
> way of interpreting it is as a pointer to an array row even though it is
> not a valid construct on it's own.
>
> There is a clear extension of the one dimentsional case a declaration
> int a[5] leaves future references to a as being equivalent to &(a[0]) so
> it is reasonable to regard a declaration int a[4][5] as leaving future
> references like a[i] as equivalent to &(a[i][0]).
>
One important point is: a two-dimensional array is a double
indirection. The construct "x[5][8]" is equivalent to
"*(*(x+5)+8)". Each of those two "*" does a dereference.
>> have come across the practice in other languages). In fact C has to
>> perform different calculations to evaluate the address of an element
>> a[i][j], depending on how a was defined (int a[4][5], or int** a).
>> The sizeof operator also knows something about array types.
>
> If a is defined as int **a then a[i][j] is not valid at all.
>
*Not* completely true. If a is a pointer to a pointer, it can be
dereference with **a:
x = **a;
equivalently, this can be written:
x = a[0][0];
since it is equivalent to:
x = *(*(a+0)+0);
--
+----------------------------------------+
| Charles and Francis Richmond |
| |
| plano dot net at aquaporin4 dot com |
+----------------------------------------+
Article: 146214On Mar 8, 4:40=A0pm, Andy Peters <goo...@latke.net> wrote: > On Mar 8, 1:32=A0pm, rickman <gnu...@gmail.com> wrote: > > > On Mar 8, 6:53=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > rickman <gnu...@gmail.com> writes: > > > > I find the GUI will save me a lot of typing when instantiating > > > > modules. =A0I use the "generate test bench" feature to build a file > > > > with the meat and potatoes in it and I copy that to the higher leve= l > > > > module. > > > > Ahh, I use VHDL-mode in Emacs for that, which is why I haven't missed > > > it :) > > > Are you saying that Emacs understands VHDL well enough to build a test > > bench for you? > > It will create a skeleton for you. > > >=A0Will it also build a component declaration or > > instantiation automatically? =A0These three things could be automated, > > but I have never taken the time to do it. =A0Making it part of the > > editor makes perfect sense. > > The skeleton has a nice header, an instance of the DUT, signal > declarations for all DUT I/O and a simple clock generator. Of course > you have to create your own stimulus and add instantiations of other > models as necessary. Ok, that's what I get from the Aldec or Lattice ispLever tools. I'll have to look at EMACs sometime soon. Can it be used to do pretty print formatting on VHDL files? RickArticle: 146215
On Mar 8, 6:10=A0pm, "Pete Fraser" <pfra...@covad.net> wrote: > Thankyou everybody for your help so far. > > I seem to be confused by the waveform viewer now. > My typical debug cycle in Modelsim XE uses wave.do. > I will load the sim, run wave.do to bring up the waveforms > I'm interested in, then run the sim. > If the waveforms point to mistakes I've made, I'll often > want to add a few more waveforms, save the updated > wave.do file, then re-start the sim using the new wave.do. > > I can't work out how to do the equivalent in Active-HDL. > My modesim wave.do seems to work in Aldec, but I can't > see how to save it when I've added waveforms. > I can't even work out how to add waveforms reliably; > sometimes dragging signals from the structure pane to an > existing waveform viewer opens a new viewer window. > I'm also not sure which viewer I'm using (advanced or standard), > or how I control that. Sometimes the title bar says > "untitled.awc", and sometimes "untitled.asdb". > > Help, I haven't felt this clueless in a long time. I am told ActiveHDL will use the same .do files that Modelsim uses, but I don't know how to automatically create them. I don't know because I do it without a .do file. Once you open a waveform window, you can add whatever signals to it you want by click and drag from the structure window to the waveform window. Once you run your simulation and quit the program it will ask if you want to save the waveform window. If you say yes, it will save it with all the signals added and when you bring up this project again those signals will be there. This saves the signal names as well as the waveform in an .aws file. If you want to save disk space, you can erase the waveform before saving it. I've never had a new window open up from dragging a signal from the structures pane to the waveform pane. The title bar of my versions shows the path of the waveform as an .aws file. I'm not sure what the purpose of the .awf is compared to the .aws file. RickArticle: 146216
Hi, I have a question about when to generate a latch. In Example_1 and Exmaple_2, I don't think it will generate a latch. I don't know why. Example_1: process(RESET, CLK) Begin If RESET =3D =911=92 then StateA <=3D S0; Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then If SINI =3D =911=92 then StateA <=3D S0; Elsif E2 =3D =911=92 then null; -- missing a signal assignment statement -- I suppose it will not generate a latch, why? Elsif StateA =3D S1 then StateA <=3D S3; Else StateA <=3D StateA_NS; End if; End if; End process; Example_2: process(=85) Begin Case StateA is ...; -- no signal assignement statements are missing End case; End process; WengArticle: 146217
On Mar 8, 5:46=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > I have a question about when to generate a latch. > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I > don't know why. > > Example_1: process(RESET, CLK) > Begin > =A0 =A0 =A0 =A0 If RESET =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0; > =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 -- missing a signal assignment statement > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why? > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_NS; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if; > =A0 =A0 =A0 =A0 End if; > End process; > > Example_2: process(=85) > Begin > =A0 =A0 =A0 =A0 Case StateA is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signal = assignement statements are missing > =A0 =A0 =A0 =A0 End case; > End process; > > Weng It doesn't generate a latch because you have fully defined a positive edge triggered register with an asynchronous reset. The result of the "Elsif E2 =3D '1' " comparison is that StateA remains the same as it was in the previous clk'event and this takes precedence over the next Elsif and Else statements. Ed McGettigan -- Xilinx Inc.Article: 146218
rickman <gnuarm@gmail.com> writes: > Ok, that's what I get from the Aldec or Lattice ispLever tools. I'll > have to look at EMACs sometime soon. Can it be used to do pretty > print formatting on VHDL files? Yes, it will "beautify", either the entire buffer or the current region (using C-c C-b or C-c M-b). I'm also using Emacs/Gnus writing this message and reading this newsgroup. I'm using Emacs/Mew for writing E-mail, also writing Verilog, Common Lisp, Python, C, Java, LaTex, etc., as well as doing GIT commits, diffs, creating branches, merges, even surfing the web using w3m. Dired in Emacs provides a great file browser where I can to bulk editing etc. Whenever I want to perform tedious repetitive editing tasks I will usually make a small Emacs Lisp function to do it for me... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 146219
On 9 Mar, 01:46, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi, > I have a question about when to generate a latch. > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I > don't know why. > > Example_1: process(RESET, CLK) > Begin > =A0 =A0 =A0 =A0 If RESET =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0; > =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 =A0 -- missing a signal assignment statement > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why? > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_NS; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if; > =A0 =A0 =A0 =A0 End if; > End process; > > Example_2: process(=85) > Begin > =A0 =A0 =A0 =A0 Case StateA is > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signal = assignement statements are missing > =A0 =A0 =A0 =A0 End case; > End process; > > Weng In my mind, it generated a register with enable and async reset. Latches are only created when you dont have a clock in a process and you forget to assign something between process iterations.Article: 146220
rickman <gnuarm@gmail.com> writes:
> On Mar 8, 6:53 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>> rickman <gnu...@gmail.com> writes:
>> > I find the GUI will save me a lot of typing when instantiating
>> > modules. I use the "generate test bench" feature to build a file
>> > with the meat and potatoes in it and I copy that to the higher level
>> > module.
>>
>> Ahh, I use VHDL-mode in Emacs for that, which is why I haven't missed
>> it :)
>
> Are you saying that Emacs understands VHDL well enough to build a test
> bench for you? Will it also build a component declaration or
> instantiation automatically? These three things could be automated,
> but I have never taken the time to do it. Making it part of the
> editor makes perfect sense.
Here's an example:
Given this (for which I typed very few letters due to autocompletion
and other magic):
entity example is
generic (
blah : integer := 5);
port (
clk : in std_logic;
reset : in std_logic;
a : in integer;
b : out integer);
end entity example;
I can "copy-port" and "paste as testbench" to get this (I have done
nothing further to it at all):
< being vhdl paste >
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------------------------------------------------------------------
entity tb_example is
end entity tb_example;
----------------------------------------------------------------------------------------------------------------------------------
architecture test of tb_example is
-- component generics
constant blah : integer := 5;
-- component ports
signal clk : std_logic;
signal reset : std_logic;
signal a : integer;
signal b : integer;
-- clock
signal Clk : std_logic := '1';
-- finished?
signal finished : std_logic;
begin -- architecture test
-- component instantiation
DUT: entity work.example
generic map (
blah => blah)
port map (
clk => clk,
reset => reset,
a => a,
b => b);
-- clock generation
Clk <= not Clk after 10 ns when finished /= '1' else '0';
-- waveform generation
WaveGen_Proc: process
begin
finished <= '0';
-- insert signal assignments here
finished <= '1';
report (time'image(now) & " Finished");
wait;
end process WaveGen_Proc;
end architecture test;
----------------------------------------------------------------------------------------------------------------------------------
configuration tb_example_test_cfg of tb_example is
for test
end for;
end tb_example_test_cfg;
----------------------------------------------------------------------------------------------------------------------------------
< end vhdl paste >
I still need to update the vhdl-mode config so that clk doesn't get
defined twice - I broke that at some point, and haven't gone back to
fix it properly, I just delete the line. That feels very lazy, now
I'm admitting it :)
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 146221> Are you saying that Emacs understands VHDL well enough to build a test > bench for you? Will it also build a component declaration or > instantiation automatically? These three things could be automated, > but I have never taken the time to do it. Making it part of the > editor makes perfect sense. The problem with emacs is you need three knuckles in each finger to drive it. The following perl script builds a basic testbench from a *.vhd entity. http://www.nialstewartdevelopments.co.uk/download/tb_gen.pl It's not perfect (generics throw it I think, I keep meaning to fix that) but it's saved me a lot of time. Nial.Article: 146222
Charles Richmond <frizzle@tx.rr.com> writes:
> Yes, "2[c]" does work in C as well as "c[2]", and yields the same
> results. The definition of "c[x]" is "*(c+x)", where the array "c"
> becomes a pointer to the first element, and the integer value "x" is
> scaled by the length associated with the pointer "c". "*(c+x)" will
> give the same result as "*(x+c)", so it's logical.
Just curious, but why is it that "2[c]" doesn't seem to work as an
argument to printf? This simple example gives an error at compile, for
example:
#include <stdio.h>
int main()
{
char c[] = "12345678";
printf("%c\n", [2]c);
}
gcc says:
array_fun_mini_example.c: In function 'main':
array_fun_mini_example.c:6: error: expected expression before '[' token
I'm using gcc 4.3.2. Assignment like 2[c] = '1' and reading a value
like tmp = 2[c] seem to work fine, though.
Article: 146223
Anssi Saari <as@sci.fi> writes:
> Charles Richmond <frizzle@tx.rr.com> writes:
>
>> Yes, "2[c]" does work in C as well as "c[2]", and yields the same
>> results. The definition of "c[x]" is "*(c+x)", where the array "c"
>> becomes a pointer to the first element, and the integer value "x" is
>> scaled by the length associated with the pointer "c". "*(c+x)" will
>> give the same result as "*(x+c)", so it's logical.
>
> Just curious, but why is it that "2[c]" doesn't seem to work as an
> argument to printf? This simple example gives an error at compile, for
> example:
>
> #include <stdio.h>
>
> int main()
> {
> char c[] = "12345678";
> printf("%c\n", [2]c);
> }
>
> gcc says:
>
> array_fun_mini_example.c: In function 'main':
> array_fun_mini_example.c:6: error: expected expression before '[' token
>
> I'm using gcc 4.3.2. Assignment like 2[c] = '1' and reading a value
> like tmp = 2[c] seem to work fine, though.
Possibly because your program uses [2]c, not 2[c].
--
As we enjoy great advantages from the inventions of others, we should
be glad of an opportunity to serve others by any invention of ours;
and this we should do freely and generously. (Benjamin Franklin)
Article: 146224
On Mar 9, 12:32=A0am, Tricky <trickyh...@gmail.com> wrote:
> On 9 Mar, 01:46, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > Hi,
> > I have a question about when to generate a latch.
>
> > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
> > don't know why.
>
> > Example_1: process(RESET, CLK)
> > Begin
> > =A0 =A0 =A0 =A0 If RESET =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why?
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_NS;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if;
> > =A0 =A0 =A0 =A0 End if;
> > End process;
>
> > Example_2: process(=85)
> > Begin
> > =A0 =A0 =A0 =A0 Case StateA is
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signa=
l assignement statements are missing
> > =A0 =A0 =A0 =A0 End case;
> > End process;
>
> > Weng
>
> In my mind, it generated a register with enable and async reset.
> Latches are only created when you dont have a clock in a process and
> you forget to assign something between process iterations.
Example_1: process(RESET, CLK)
Begin
If RESET =3D =911=92 then
StateA <=3D S0;
Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
If SINI =3D =911=92 then
StateA <=3D S0;
Elsif E2 =3D =911=92 then
null; -- missing a signal assignment statement
-- I suppose it will not generate a latch, why?
Elsif StateA =3D S1 then
StateA <=3D S3;
Elsif C1 /=3D '1' then
StateA <=3D StateA_NS;
-- else -- missing a signal assignment statement
-- null; -- I suppose it will not generate a latch, why?
End if;
End if;
End process;
Example_2: process(=85)
Begin
Case StateA is
...; -- no signal assignement statements are missing
End case;
End process;
Weng
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