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On Sun, 17 Jan 2010 04:29:19 +0000, Giorgos Tzampanakis wrote: > On 2010-01-16, Michael S <already5chosen@yahoo.com> wrote: > >> Quartus on Ubuntu is one of requiring themes of Altera forum See here >> for example for one of the latest threads: >> http://alteraforums.org/forum/showthread.php?t=5163&highlight=ubuntu >> There was a wiki entry somewhere. I think they forgot to mention that >> on x64 before Quartus you have to install 32-bit libraries. >> >> Since Ubuntu is based on Debian I'd guess most things said about Ubuntu >> should be applicable to other Debian variants. More or less ;) > > I think I'll try it and see what happens. However, I'm not perfectly > clear on whether the Linux version is free or not. If it's not, I'm not > going to bother going through the pain of installing it, I'll just use > the Windows version. > > So, is it free? I'm talking about the Web Edition. Yes there is a free version of Quartus for Linux however it's 32 bit only.Article: 144951
General Schvantzkoph wrote: > On Sun, 17 Jan 2010 04:29:19 +0000, Giorgos Tzampanakis wrote: >> >> So, is it free? I'm talking about the Web Edition. > > Yes there is a free version of Quartus for Linux however it's 32 bit only. Oh there is a free/gratis Linux version of Quartus ? Last time I looked (recently) it was only free for ms-windows, and Linux users had to pay full price :-( When did the decision to treat Linux equally occur ? Where can I find informations about this ? are there forums, press releases or other discussions ? yg -- http://ygdes.com / http://yasep.orgArticle: 144952
On Sun, 17 Jan 2010 14:32:19 +0100, whygee wrote: > General Schvantzkoph wrote: >> On Sun, 17 Jan 2010 04:29:19 +0000, Giorgos Tzampanakis wrote: >>> >>> So, is it free? I'm talking about the Web Edition. >> >> Yes there is a free version of Quartus for Linux however it's 32 bit >> only. > > Oh there is a free/gratis Linux version of Quartus ? Last time I looked > (recently) it was only free for ms-windows, and Linux users had to pay > full price :-( > > When did the decision to treat Linux equally occur ? Where can I find > informations about this ? are there forums, press releases or other > discussions ? > > yg It's a beta. The feature list looks like it's missing a ton of features which they are promising in the future. I think the issue is that they are transitioning from a proprietary closed source GUI toolkit to a proper open source toolkit.Article: 144953
General Schvantzkoph wrote: > It's a beta. The feature list looks like it's missing a ton of features > which they are promising in the future. I think the issue is that they > are transitioning from a proprietary closed source GUI toolkit to a > proper open source toolkit. I heard (?) that Xilinx (or Actel ?) has the same troubles with Windows-based software, and they are forced to use proprietary Win-To-Lin solutions that make portability and/or efficiency difficult... I'll have to dig further in this subject. OTOH, I tried SiliconBlue's SW and it seems that it was designed with both Linux and Windows in mind from the very beginning, and the result is convincing. Some other technical sides are probably not what others expect, but at least they seem to manage cross-platform tools well :-) So I have hopes for the far future (at least the situation evolved in the right direction these last 10 years, not as much as expected but I can't deny the efforts). yg -- http://ygdes.com / http://yasep.orgArticle: 144954
On Sun, 17 Jan 2010 17:27:35 +0100, whygee wrote: > General Schvantzkoph wrote: >> It's a beta. The feature list looks like it's missing a ton of >> features which they are promising in the future. I think the issue is >> that they are transitioning from a proprietary closed source GUI >> toolkit to a proper open source toolkit. > > I heard (?) that Xilinx (or Actel ?) has the same troubles with > Windows-based software, and they are forced to use proprietary > Win-To-Lin solutions that make portability and/or efficiency > difficult... I'll have to dig further in this subject. > > OTOH, I tried SiliconBlue's SW and it seems that it was designed with > both Linux and Windows in mind from the very beginning, and the result > is convincing. Some other technical sides are probably not what others > expect, but at least they seem to manage cross-platform tools well :-) > So I have hopes for the far future (at least the situation evolved in > the right direction these last 10 years, not as much as expected but I > can't deny the efforts). > > yg I think Xilinx has already made the transition for most of their tools, the only things that will never be fixed are the legacy tools like fpga_editor.Article: 144955
Hi yg, "whygee" <yg@yg.yg> wrote in message news:hivfob$js9$1@speranza.aioe.org... > General Schvantzkoph wrote: >> It's a beta. The feature list looks like it's missing a ton of features >> which they are promising in the future. I think the issue is that they are >> transitioning from a proprietary closed source GUI toolkit to a proper open >> source toolkit. > > I heard (?) that Xilinx (or Actel ?) has the same troubles > with Windows-based software, and they are forced to use > proprietary Win-To-Lin solutions that make portability > and/or efficiency difficult... I'll have to dig > further in this subject. It might be mainwin which was popular many years ago. I remember Leonardo Spectrum using it for its GUI-less Linux port. Hans www.ht-lab.com > > OTOH, I tried SiliconBlue's SW and it seems that it was > designed with both Linux and Windows in mind from the very > beginning, and the result is convincing. Some other technical > sides are probably not what others expect, but at least > they seem to manage cross-platform tools well :-) > So I have hopes for the far future (at least the situation > evolved in the right direction these last 10 years, > not as much as expected but I can't deny the efforts). > > yg > -- > http://ygdes.com / http://yasep.orgArticle: 144956
> On Jan 16, 10:23=A0pm, Gabor <ga...@alacron.com> wrote: > to generate a testbench > template automatically. =A0That often saves the headache > of writing the signal declarations, instantiations and > initialization logic. > I never caught on to how this was ever much of a headache and why it gets touted by the tool vendors as something important. Copy/paste the entity that you create to make two copies. The first copy you add the word 'signal' at the begining of the line and then delete the 'in', 'out' and 'inout' modes from each line and 'presto' you have the signal definitions for the testbench. The second copy you edit the 'entity' line to make it an instantiation, change 'generic' and 'port' to 'generic map' and 'port map' and then use a macro to change all of the lines of the entity from this... xyz: in std_logic; ...to this... xyz =3D> xyz, Touch it up a bit if you want and you're done...depends on your preferred editor, but it never takes more than a minute or so. Not much of a time saver in my opinion. Now something to generate the actual stimulus and generate the assertion checking would be nice and would be a real timesaver... KJArticle: 144957
On Jan 17, 1:28=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > > On Jan 16, 10:23=A0pm, Gabor <ga...@alacron.com> wrote: > > to generate a testbench > > template automatically. =A0That often saves the headache > > of writing the signal declarations, instantiations and > > initialization logic. > > I never caught on to how this was ever much of a headache and why it > gets touted by the tool vendors as something important. =A0Copy/paste > the entity that you create to make two copies. > > The first copy you add the word 'signal' at the begining of the line > and then delete the 'in', 'out' and 'inout' modes from each line and > 'presto' you have the signal definitions for the testbench. > > The second copy you edit the 'entity' line to make it an > instantiation, change 'generic' and 'port' to 'generic map' and 'port > map' and then use a macro to change all of the lines of the entity > from this... > > =A0 =A0xyz: =A0in std_logic; > > ...to this... > > =A0 =A0xyz =3D> xyz, > > Touch it up a bit if you want and you're done...depends on your > preferred editor, but it never takes more than a minute or so. > > Not much of a time saver in my opinion. =A0Now something to generate the > actual stimulus and generate the assertion checking would be nice and > would be a real timesaver... > > KJ Well just your description is significanly longer than the buttons to generate the testbench in ISE. It's actually more of a timesaver if you use Verilog, where the instantiation and wires / regs don't resemble the source code like in VHDL. It's also great if you wanted to quickly make a Verilog testbench for your VHDL entity or vice versa. This goes doubly for a beginner, who may not know the basics required to start the testbench. Just my 2 cents, GaborArticle: 144958
Giorgos Tzampanakis <gt67@hw.ac.uk> writes: > I want to run Quartus on my Debian computer. I see that Altera doesn't > officially support Debian. Has anyone here managed to run Quartus on > Debian? What was your experience? I haven't used it on Debian, but I've used it on Gentoo for years. I also have some colleagues using Ubuntu. However, I always keep a Red Hat system at hand (previously I had a separate system, but now I have it running in VirtualBox). If I observe a problem I and if it's reproducible on the RedHat system I can call Altera support. The core of the Altera software seem to be very portable, however the little scripts to determine the platform type etc. are written in csh and seem quite strange to me. I've seen that the start-up script have got confused at times, but by manually setting PATH and LD_LIBRARY_PATH have made it work. I was disappointed when I started Quartus 9.1 on my Gentoo and observed this message: rpm: Command not found. It seems like the start-up script is using rpm to find packages, which will of course fail on systems not using rpm packages. However, it will still run fine. Many vendors seem to try to figure out what kind of system their software is running on rather than trying to check if the system provide the *features* they require. I've seen some software which will check /etc/redhat-release and if it does not contain what they expect it will fail. However, making an /etc/redhad-release with the right content will make the tool run. I understand that they only provide support using a single distro, but they should at least try to support multiple distros. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 144959
"jjlindula@hotmail.com" <jjlindula@hotmail.com> writes: > Thanks everyone for your input. My question is relating to the cost of > a simulator that supports SystemVerilog Verfication, just how much > should I expect to spend for one license? If its too expensive I'll > have to stick with sytem testbenches. If you have to ask you can't afford it... Anyway you should check with Mentor, maybe they can give you a deal. I've never used Questa myself, only Synopsys VCS. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 144960
On Jan 16, 10:23 pm, Gabor <ga...@alacron.com> wrote: > On Jan 16, 12:59 pm, KMS <kms34...@gmail.com> wrote: > > > Hi, > > > I recommend you change your BOOLEANs to STD_LOGIC. > > If you change the booleans to std_logic, you'll need > to change all the if statements to have a comparison > operator like > if (nickel_in) then . . . > becomes > if (nickel_in = '1') then . . . > > If you're not trying to synthesize this logic, I'm not really > clear why you shouldn't use booleans, but then I would > normally have used Verilog. I'll second that. There is nothing about Booleans that are evil. The two times I will replace a Boolean with a std_logic is when I know this is a signal that will be important in simulation or when it is at the top level of a synthesized design. I don't recall the exact issue having other than std_logic or slv at the top level, but it is not a big deal to work with that restriction. I replace a Boolean with std_logic for simulation only because a std_logic signal produces a wiggly line with levels that are easy to see while a Boolean has a state which must be read in the waveform viewer which can be difficult with small text. I like Booleans because they can be less typing when used in an IF statement or in the result of a comparison. In the end, it more a matter of preference than anything. If you like the format of your code using Booleans, go ahead. There are no real roadblocks to using them. > On the other hand, if you make the code synthesizable, > you can use the Xilinx webpack to generate a testbench > template automatically. That often saves the headache > of writing the signal declarations, instantiations and > initialization logic. I'll second that as well. But the template is only the signal declarations and the component instantiations. You still have to write the code to drive all the inputs to the UUT. Once you go a couple of simple test benches you will see how easy they are. When you need to test more complex code, you will find that your test bench needs to get a little more complex, but the same concepts apply. The main thing is to keep it simple and look at other coder's test benches to get ideas. There are a lot of good designers out there and it is always good to learn what you can from them. But don't be afraid to think for yourself too. RickArticle: 144961
On 17 Jan 2010 17:33:29 GMT, General Schvantzkoph <schvantzkoph@yahoo.com> wrote: >On Sun, 17 Jan 2010 17:27:35 +0100, whygee wrote: > >> General Schvantzkoph wrote: >>> It's a beta. The feature list looks like it's missing a ton of >>> features which they are promising in the future. I think the issue is >>> that they are transitioning from a proprietary closed source GUI >>> toolkit to a proper open source toolkit. >> >> I heard (?) that Xilinx (or Actel ?) has the same troubles with >> Windows-based software, and they are forced to use proprietary >> Win-To-Lin solutions that make portability and/or efficiency >> difficult... I'll have to dig further in this subject. >I think Xilinx has already made the transition for most of their tools, >the only things that will never be fixed are the legacy tools like >fpga_editor. And much of the demonstration software relating to AppNotes, board starter kits etc. The strangest is one of the PCIe DMA demonstration apps, (XAPP859 or XAPP1052) which is Windows-only, but with its GUI based on (open-source) GTK... - BrianArticle: 144962
General Schvantzkoph <schvantzkoph@yahoo.com> writes: > I think Xilinx has already made the transition for most of their tools, > the only things that will never be fixed are the legacy tools like > fpga_editor. Just out of curiosity, since you mentioned you run Xilinx tools in Fedora. Have you tried the 64-bit fpga_editor from ISE 11.1.04? I just get a segmentation fault.Article: 144963
"HT-Lab" <hans64@ht-lab.com> writes: > It might be mainwin which was popular many years ago. I remember Leonardo > Spectrum using it for its GUI-less Linux port. I dunno, Xilinx fpga_editor and Actel's Libero use Wind/U. I remember Mentor's Precision used Mainwin also, at least around 2005 when I last used it.Article: 144964
On Sun, 17 Jan 2010 12:43:20 -0800 (PST), rickman <gnuarm@gmail.com> wrote: >On Jan 16, 10:23 pm, Gabor <ga...@alacron.com> wrote: >> On Jan 16, 12:59 pm, KMS <kms34...@gmail.com> wrote: >> >> > Hi, >> >> > I recommend you change your BOOLEANs to STD_LOGIC. >> If you're not trying to synthesize this logic, I'm not really >> clear why you shouldn't use booleans, but then I would >> normally have used Verilog. > >I'll second that. There is nothing about Booleans that are evil. The >two times I will replace a Boolean with a std_logic is when I know >this is a signal that will be important in simulation or when it is at >the top level of a synthesized design. I don't recall the exact issue >having other than std_logic or slv at the top level, but it is not a >big deal to work with that restriction. I'll third that. The issue I see with std_logic[_vector] ports at the top level is that whatever you use at the top level will be translated to std_logic[_vector] by synthesis and/or the post-PAR netlist generator. Therefore if you ever need to run a timing simulation, the easiest thing is to use these types from the start. Then your testbench will work with either behavioural or netlist versions. Of course you could use other port types, and generate a wrapper to convert port types for the netlist, but that's more work. If the tools were actually designed to support VHDL users who want to design at the most appropriate level of abstraction, they would auto-generate such a wrapper; it would be trivial, and allow you to use any synthesisable type for your ports - even records. But they aren't... - BrianArticle: 144965
On Mon, 18 Jan 2010 01:09:17 +0200, Anssi Saari wrote: > General Schvantzkoph <schvantzkoph@yahoo.com> writes: > >> I think Xilinx has already made the transition for most of their tools, >> the only things that will never be fixed are the legacy tools like >> fpga_editor. > > Just out of curiosity, since you mentioned you run Xilinx tools in > Fedora. Have you tried the 64-bit fpga_editor from ISE 11.1.04? I just > get a segmentation fault. I run that in a CentOS 5 VM. I almost never use the GUI for Xilinx tools, I do everything with scripts. I have brought up the ISE GUI just to check which parts are supported and it does work in Fedora. I don't have scripts for the Altera tools so I run Quartus from it's GUI which crashes on Fedora but does work on 64 bit CentOS5. The Quartus 9.1 GUI is very buggy, at least it is the way I run it which is to ssh into a CentOS5.4 VM. You have to be extremely delicate when you select a file to open from Quartus, dragging the mouse over a file name will cause a modal box to appear which hangs the interface about 50% of the time. The only solution is to kill Quartus using the dead app widget or from the command line and then restart it. The close box on Quartus is useless when it gets into this state because it's hung in some mode box. The SignalTap application and Timequest work fine, it's just the basic GUI which is broken. BTW I've found that I can't run SignalTap reliably from a native CentOS5.4 machine, the Linux driver for the download cable is crap. The Linux driver for Chipscope is also a pain, it would be nice if Altera and Xilinx would provide proper GPLed drivers for their download cable so that they could be built into the kernel. Running SignalTap and ChipScope are the only things that I use Windows for. I put XP on an old single core machine which I access from rdesktop from my Linux machines.Article: 144966
> Well just your description is significanly longer than the buttons > to generate the testbench in ISE. =A0 OK, so I ramble on a bit... > It's actually more of a > timesaver if you use Verilog, where the instantiation and > wires / regs don't resemble the source code like in VHDL. Yeah, VHDL is better than Verilog any day of the week ;) > This goes > doubly for a beginner, who may not know the basics > required to start the testbench. > Not sure the beginer learns much just by clicking on a button though. > Just my 2 cents, I'll see your 2 cents, and raise you a penny KJArticle: 144967
> In the end, > it more a matter of preference than anything. =A0If you like the format > of your code using Booleans, go ahead. =A0There are no real roadblocks > to using them. > In the end, the main advantage of std_logic is with unknowns. Booleans will initialize themselves to 'False', std_logic to 'U'. Proving that your design does not depend on a lucky initialization value happens when you use std_logic not booleans. Kevin JenningsArticle: 144968
HELLO .. I AM DOING A PROJECT ON IMPLEMENTING "DSSS -- BASEBAND CDMA TRANSCIEVER " ON A SINGLE FPGA ........ ANY BODY WHO HAS DONE A SIMILAR PROJECT OR IS IN THIS FIELD ..... KINDLY HELP ... --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144969
Sir,
I am designing DLL using DCM on VERTEX4. But I am not gwtting
output for clk2x, clk2x180 I am giving my code below. I am not able to
find whetre is the fault. I have written this code in architecture
code, I didn't use coreIP where generates .xaw file .
I tried that too but not got expected result ?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_dll is
Port ( sys_clk,reset_in : in STD_LOGIC;
fpga_clk,fpga_clk2x,clk90_out,clk180_out,clk270_out,locked_out : out
STD_LOGIC);
end clk_dll;
architecture Behavioral of clk_dll is
signal
clk0_buf,clk90_buf ,clk180_buf,clk270_buf,clk_fb_in,clk0a,clk2x_buf:std_logic;
component IBUFG
port (
O : out std_logic;
I : in std_logic
);
end component;
Component BUFG
port (
O : out std_logic;
I : in std_logic );
end component;
component DCM_BASE
port (
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic );
end component;
begin
ibuf0:ibufg port map(i=>sys_clk,o=>clk0a);
buf1: bufg port map (i=> clk0_buf, o=> clk_fb_in);
dll: DCM_BASE port map (CLKIN => clk0a, CLKFB => Clk_FB_in, RST =>
Reset_in, CLK0 => Clk0_buf,
CLK90 => clk90_buf, CLK180 => clk180_buf, CLK270 =>
clk270_buf, CLK2X => clk2x_buf, CLK2X180 => OPEN,
CLKDV => open, CLKFX => OPEN, CLKFX180 => OPEN, LOCKED =>
locked_out);
fpga_clk<=clk_fb_in;
buf2:bufg port map(i=>clk90_buf,o=>clk90_out);
buf3:bufg port map(i=>clk180_buf,o=>clk180_out);
buf4:bufg port map(i=>clk270_buf,o=>clk270_out);
buf5:bufg port map(i=>clk2x_buf,o=>fpga_clk2x);
end Behavioral;
Article: 144970whygee wrote: > General Schvantzkoph wrote: >> It's a beta. The feature list looks like it's missing a ton of >> features which they are promising in the future. I think the issue is >> that they are transitioning from a proprietary closed source GUI >> toolkit to a proper open source toolkit. > > I heard (?) that Xilinx (or Actel ?) has the same troubles > with Windows-based software, and they are forced to use > proprietary Win-To-Lin solutions that make portability > and/or efficiency difficult... I'll have to dig > further in this subject. > I don't remember the details, but I believe that both Altera and Xilinx used the same windows-to-linux library originally for their Linux ports, and that that particular library was royalty based. Being royalty based, it is very difficult to make it available freely. I guess they had good reason for picking that library at the time, but it has always seemed strange to me that the software should be build so strongly on *nix style solutions (lots of perl and tcl, amongst other things) and yet be so difficult to move to Linux.Article: 144971
> Thanks everyone for your input. My question is relating to the cost of > a simulator that supports SystemVerilog Verfication, just how much > should I expect to spend for one license? If its too expensive I'll > have to stick with sytem testbenches. > > joe To put a ball park on it, about the price of a relatively well-equiped medium range car ;). If you get a great deal from Aldec / Cadence / Mentor / Synopsys, maybe the price of a well equiped small car.Article: 144972
David Brown <david@westcontrol.removethisbit.com> writes: > I don't remember the details, but I believe that both Altera and > Xilinx used the same windows-to-linux library originally for their I think Xilinx used WindU and Altera used (and still use) Mainwin originally, at least when I used the tools on SunOS/Solaris. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 144973
On Jan 17, 7:49=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > > In the end, > > it more a matter of preference than anything. =A0If you like the format > > of your code using Booleans, go ahead. =A0There are no real roadblocks > > to using them. > > In the end, the main advantage of std_logic is with unknowns. > Booleans will initialize themselves to 'False', std_logic to 'U'. > Proving that your design does not depend on a lucky initialization > value happens when you use std_logic not booleans. > > Kevin Jennings Interestingly enough, for FPGA synthesis, the boolean will more closely resemble the final hardware. "Uninitialized" logic in an FPGA generally defaults to zero, at least for Xilinx XST. There may be some architectures that don't initialize every register and memory bit in the configuration bitstream, but I haven't run across them yet. Regards, GaborArticle: 144974
On Jan 18, 1:15=A0am, abhishek kumar <abkv...@gmail.com> wrote: > Sir, > =A0 =A0 =A0 =A0I am designing DLL using DCM on VERTEX4. But I am not gwtt= ing > output for clk2x, clk2x180 I am giving my code below. I am not able to > find =A0whetre is the fault. I have written this code in architecture > code, I didn't use coreIP where generates .xaw file . > I tried that too but not got expected result ? > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > =A0library UNISIM; > =A0use UNISIM.VComponents.all; > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity clk_dll is > =A0 =A0 Port ( sys_clk,reset_in : in =A0STD_LOGIC; > > fpga_clk,fpga_clk2x,clk90_out,clk180_out,clk270_out,locked_out : out > STD_LOGIC); > end clk_dll; > > architecture Behavioral of clk_dll is > signal > clk0_buf,clk90_buf ,clk180_buf,clk270_buf,clk_fb_in,clk0a,clk2x_buf:std_l= ogic; > component IBUFG > =A0port ( > =A0 =A0O : out std_logic; > =A0 =A0I : in std_logic > =A0); > end component; > > Component BUFG > =A0port ( > =A0 =A0O : out std_logic; > =A0 =A0I : in std_logic ); > end component; > > component DCM_BASE > =A0port ( > =A0 =A0CLK0 : out std_logic; > =A0 =A0CLK90 : out std_logic; > =A0 =A0CLK180 : out std_logic; > =A0 =A0CLK270 : out std_logic; > =A0 =A0CLK2X : out std_logic; > =A0 =A0CLK2X180 : out std_logic; > =A0 =A0CLKDV : out std_logic; > =A0 =A0CLKFX : out std_logic; > =A0 =A0CLKFX180 : out std_logic; > =A0 =A0LOCKED : out std_logic; > =A0 =A0CLKIN : in std_logic; > =A0 =A0CLKFB : in std_logic; > =A0 =A0RST : in std_logic ); > end component; > > begin > ibuf0:ibufg port map(i=3D>sys_clk,o=3D>clk0a); > buf1: bufg port map (i=3D> clk0_buf, o=3D> clk_fb_in); > > dll: DCM_BASE port map (CLKIN =3D> clk0a, CLKFB =3D> Clk_FB_in, RST =3D> > Reset_in, CLK0 =3D> Clk0_buf, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK90 =3D> clk90_buf, CLK= 180 =3D> clk180_buf, CLK270 =3D> > clk270_buf, CLK2X =3D> clk2x_buf, CLK2X180 =3D> OPEN, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKDV =3D> open, CLKFX = =3D> OPEN, CLKFX180 =3D> OPEN, LOCKED =3D> > locked_out); > > fpga_clk<=3Dclk_fb_in; > buf2:bufg port map(i=3D>clk90_buf,o=3D>clk90_out); > buf3:bufg port map(i=3D>clk180_buf,o=3D>clk180_out); > buf4:bufg port map(i=3D>clk270_buf,o=3D>clk270_out); > buf5:bufg port map(i=3D>clk2x_buf,o=3D>fpga_clk2x); > end Behavioral; There are a number of generics required to set up the DCM in the correct operating mode, not the least of which is DLL_FREQUENCY_MODE, which must be "LOW" in order to get the 2x outputs. Look in the Virtex-4 Libraries Guide for HDL Designs, available from the ISE help menu under "Software Manuals." There are instantiation templates in the manual which should help. Also refer to your Virtex 4 data sheet to make sure your part is spec'd to work in low frequency mode with your clock input frequency. HTH, Gabor
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