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On Jan 19, 7:10=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Mon, 18 Jan 2010 18:07:01 -0600, "akshayvreddy" <akshayvre...@gmail.co= m> > wrote: > > >Hello, > >I am implementing a processor design on the virtex 2 chip. The Design wa= s > >done using verilog with Xilinx 10.1 and modelsim. I have a compiler of t= he > >design. > > >My question is:is there a way to integrate the compiler output with the > >FPGA using modelsim simulator without actually programming the fpga. I a= m > >using a windows system and the complier is C based. > > >Thank you > >Akshay > > Yes. > > Where is the program memory for the processor? > > If external memory, you can modify a memory model to load (and save) its > contents from a file. I have done this by adding extra "load", "save" and > "filename" ports to a memory model I originally downloaded from a memory > manufacturer (Cypress), and driving them from the testbench. > > Actually loading an object code file is then a simple matter of programmi= ng. > > If you are using BRAMs, you can instantiate them and translate your objec= t code > into their INIT_nn generics. > > But it is much better and easier to infer a ROM as a constant array, init= ialised > by a function (which is called during elaboration). That function could r= ead > your object file into the ROM. Or you could write another program to tran= slate > the object format into a VHDL package containing your constant array. > > (I don't know Verilog but I expect it can do these things too) > > - Brian For Verilog, you can generate ASCII hex files for initialization using $readmemh. If you place the $readmemh in an initial block in the module where the memory is inferred, it will also work for synthesis, at least in XST 10.1Article: 145001
On Tue, 19 Jan 2010 06:27:03 -0800 (PST), Gabor wrote: >For Verilog, you can generate ASCII hex files for initialization using >$readmemh. If you place the $readmemh in an initial block in the >module where the memory is inferred, it will also work for synthesis, >at least in XST 10.1 If you're a VHDL user, you can get a simulation-only VHDL implementation of $readmem (reads exactly the same input text files) here: http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip One day, when there's less work to do, I intend to add a few more file formats to its capabilities - but for now it only knows how to mimic Verilog $readmemb/h. -- Jonathan BromleyArticle: 145002
On 19 Jan, 11:29, "Roger" <rogerwil...@hotmail.com> wrote: > Due to a bug in the Easy PC software tool from Numberone Systems, I've just > had a very time consuming and costly incident. Despite their faulty software > costing me a lot of money, the company have so far taken the "hard luck" > approach. > > Has anyone else had any experience of Easy PC? > > TIA, > > Rog. Roger Our CAD department uses Mentor. We probably pay 50 times per seat the cost of Easy PC. We ship the netlist with the gerbers and the PCB manufacturers recently reported on one of my designs that the netlist automatically generated from the gerbers showed power shorted directly to ground. Software is provided "as is", if you need to rely on its output you need to be able to check it via such a third party. Sorry to be blunt, I'm also trying to go self employed somehow and hopefully I will then be able to feel your pain more accurately. ColinArticle: 145003
On Jan 18, 4:33=A0pm, "mlajevar" <mahsa_lajevardi@n_o_s_p_a_m.yahoo.com> wrote: > Hello > > I have the vhdl code for both amplifier-ADC and DAC of spartan3E,now I wa= nt > to combine them together.Actually the purpose is to get an analog avlue > from oscilloscope send it to FPGA(through my vhdl code for ADC ,it is > converted to digital,and via the code for DAC, it will be converted to > analog voltage)and check the analog output to see if it is similar ti the > analog input we applied to ADC =A0at first. > > I am going to consider two different states for DAC and ADC, and just to > turn around these two states.I know that SPI bus will be shared between > them ,so I konw I have to disable DAC ,while working with ADC and vice > versa. > > my question is how much I have to wait(in MHz) to go from ADC state to DA= C > and vice versa. > > I appreciate alot if you let me know about your ideas. > > thanks in advance =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Are you saying you want to sample an analog input with the ADC, and then recreate a quantized, time delayed version with the DAC? (digital voltage follower) That's not difficult, but you need to look at the data sheets for the parts. Specifically, how fast can you clock data on their SPI interfaces. This is usually specified as Tcyc. Since you mention that both parts share the same SPI interface, it would be wise to settle on the slower of the two. In that case, it would be a good idea to leave a dead SPI clock when switching the chip selects, to ensure that there isn't any contention. If your SPI clock is fairly slow, and you don't want to incur a full Tcyc penalty, you need to determine how fast the output is tri-stated once you deselect the chip selects for both parts, and make sure you wait long enough to ensure there isn't contention. You will need to look at the read timing diagram, and find the figure that shows SDO (output) being deasserted as CSn is deasserted. That parameter sets the absolute floor of how fast you can switch between devices, and should be the greater of the two. If you ever implement any kind of digital filtering, you will probably burn enough clocks in latency to ignore this, but be sure to check regardless.Article: 145004
rickman wrote:
>>> That is the common default for bits.
>> ?
>>> The *only* advantage is it covers tristate signals.
>> sure. But I don't have/need tristates.
Neither do I.
My default for I/0 bits is std_ulogic.
But this is not common.
I don't know why.
-- Mike Treseler
Article: 145005Mike Treseler wrote: > rickman wrote: >>>> That is the common default for bits. >>> ? >>>> The *only* advantage is it covers tristate signals. >>> sure. But I don't have/need tristates. > Neither do I. > My default for I/0 bits is std_ulogic. it was too, for me. I may have found that some parts of my code used std_logic and others used std_ulogic, but then why take the risk of not detecting conflicts with multiple drivers AND simulating slower ? > But this is not common. > I don't know why. I'm puzzled. However I'll try to implement a small set of libraries that implement a "common" type for all my bits and vectors, so it's easier to switch between different types and subtypes and watch the difference. > -- Mike Treseler yg -- http://ygdes.com / http://yasep.orgArticle: 145006
Hello, I am seeing a problem using ISE. I have a verilog top level with pins including N0, N1, N2, N3, N4 (similar for PX, SX and MX) I add a LOC constraint in the UCF file for all pins. For some reason, the tool seems to be confused by N1, N2, N3 and N4 (but not N0, or any of PX, SX, MX) WARNING:NgdBuild:483 - Attribute "LOC" on "N1" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. When I report the pinout at the end of the P&R, pins N1..N4 have disappeared, and I have some new pins (N31, N18, N21, N18) My *guess* is that Xilinx uses Nx (x>0) for internal netnames, and it is getting confused. Can anyone confirm and suggest a workaround? (I don't want to change the pin names) Thanks, StevenArticle: 145007
whygee wrote:
> I may have found that some parts of my code used
> std_logic and others used std_ulogic, but then
> why take the risk of not detecting conflicts
> with multiple drivers AND simulating slower ?
I expect there is no logical reason.
Just tradition.
-- Mike Treseler
Article: 145008On Jan 19, 12:20=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Mon, 18 Jan 2010 23:50:01 -0800 (PST), "jmi...@pop.net" wrote: > >> =A0 =A0 =A0 =A0 =A0if (|DCM_Delay) begin > >What character is in front of DCM_Delay in that if statement? > > I hope it's a vertical bar, the reduction-OR operator; > that would make the test effectively "if (DCM_Delay !=3D 0)" > (which would have been more readable anyway). > > The code looks OK to me. =A0The counter DCM_Delay should > reset to 4'hf, count down to zero and then remain stuck at > zero until the next reset. =A0DCM_Reset should go to zero > one clock after DCM_Delay reaches zero. > > Is there any chance that (a) the clock is not ticking, or > (b) reset is stuck high? > -- > Jonathan Bromley I take both clock and reset to debug pins. They are working as expected. More investigation reveals that none of the clocked processes are running. It's as if there's some big global signal that is holding every flop in reset. I've tried 10.1.3 and 11.1.4 - both behave badly. I'm running in Linux64 (ubuntu 9.10), and can't find the 'enable global reset' option to turn it off. I got here trying to debug a DCM power-on reset. I've gone as far as stripping the code down to this counter and a couple of latches. The clock is the input to the DCM, but I've removed the DCM completely to debug this counter. I've noticed two more strange XST things: 1) If I use 'reset' as an async reset _anywhere_, XST assumes that it's OK to use it everywhere. Including on instance where I coded it (reset) as the input to a d-flop, and XST wired it to an async preset. 2) If I connect the counter to debug pins without a name translation or an OBUF, XST will disconnect the counter from the net. Looking at the RTL (or technology) schematic shows the output of the counter dangling. Frustrated, Gary. Comment on #1 above: The code is always @ (posedge fpga_clock) reset_d <=3D reset; XST ties the D input to '0', and connects reset to the async preset!Article: 145009
rickman wrote:
> After struggling with VHDL type casting for some time, I finally
> settled on using signed/unsigned for the majority of the vectors I
> use. I seldom use integers other than perhaps memory where it
> simulates much faster with a lot less memory. But nothing is
> absolute. I just try to be consistent within a given design.
I use integer/natural ranges for small numbers
and signed/unsigned for large.
> I have
> never used bit types, but the discussion here about the advantages of
> ulogic over logic is interesting. I certainly like to speed up my
> simulations. But it is such a PITA to get away from std_logic.
Vectors, require some compromise.
I only use std_logic_vector for non-numeric variables
and for the device pins.
For std_ulogic bits, there is no pain.
However the advantages are not overwhelming either.
Simulators are now very well optimized for standard types,
and I would not expect much run-time speed up.
Detecting multiple drivers at compile time is very useful
for new users using many processes,
but these errors can also be found at elaboration time.
-- Mike Treseler
Article: 145010Hi all, I created a project which contains some xilinx IP CORES. I have successfully tested the behavioral simulation but I'm unable to get the post route simulation. Is there a way to get a post route simulation for projects containing IP CORES? Thanks --------------------------------------- Sent through http://www.FPGARelated.comArticle: 145011
Mike Treseler wrote: > whygee wrote: > >> I may have found that some parts of my code used >> std_logic and others used std_ulogic, but then >> why take the risk of not detecting conflicts >> with multiple drivers AND simulating slower ? > I expect there is no logical reason. Just tradition. There is probably a little of that, but knowing VHDL as I know it, it is certainly backed by an excellent, compelling reason. It becomes tradition when we forget it :-/ Furthermore, my code was primarily meant for synthesis (and works), so the ulogic vs logic choice was not an issue, being a one-time, few seconds of synthesis cost. OK now I should stop ranting and start coding ;-) > -- Mike Treseler yg -- http://ygdes.com / http://yasep.orgArticle: 145012
"colin" <colin_toogood@yahoo.com> wrote in message news:ab339519-5373-4065-9afb-c8ccfd14f011@p8g2000yqb.googlegroups.com... > On 19 Jan, 11:29, "Roger" <rogerwil...@hotmail.com> wrote: >> Due to a bug in the Easy PC software tool from Numberone Systems, I've >> just >> had a very time consuming and costly incident. Despite their faulty >> software >> costing me a lot of money, the company have so far taken the "hard luck" >> approach. >> >> Has anyone else had any experience of Easy PC? >> >> TIA, >> >> Rog. > > Roger > > Our CAD department uses Mentor. We probably pay 50 times per seat the > cost of Easy PC. We ship the netlist with the gerbers and the PCB > manufacturers recently reported on one of my designs that the netlist > automatically generated from the gerbers showed power shorted directly > to ground. > Software is provided "as is", if you need to rely on its output you > need to be able to check it via such a third party. > > Sorry to be blunt, I'm also trying to go self employed somehow and > hopefully I will then be able to feel your pain more accurately. > > Colin Hi Colin, If only it were so simple! I appreciate that software is supplied "as is" which is why I had to shrug my shoulders when the bug caused me hassle the first time it occurred in July 09. When it re-appeared in my next design in November 09 after allegedly being fixed and caused the PCBs to be written off, that's when I started to feel somewhat aggrieved! Number One have said it's a different fault - just one with exactly the same symptoms (!!) so I shouldn't complain. I've approached them for some form of recompense or at least a good will gesture but they won't even answer my e-mails now. The thread about this saga on their forum shows basic gist if you can be bothered: http://www.numberone.com/forum/topic.asp?TOPIC_ID=385 I hear what you say about checking everything i.e. basically trust nothing! Good luck if you go self-employed. Choose your tools supplier well though, not like me! Rog.Article: 145013
"MK" <mk@nospam.please> wrote in message news:NqidnSNgov_3BsjWnZ2dnUVZ8oudnZ2d@bt.com... > > "Roger" <rogerwilson@hotmail.com> wrote in message > news:7LGdnRZPy6owCsjWnZ2dnUVZ8r-dnZ2d@brightview.co.uk... >> Due to a bug in the Easy PC software tool from Numberone Systems, I've >> just had a very time consuming and costly incident. Despite their faulty >> software costing me a lot of money, the company have so far taken the >> "hard luck" approach. >> >> Has anyone else had any experience of Easy PC? >> >> TIA, >> >> Rog. > > I've been using EasyPC for some years now - never had any problems at all. > What was your problem (and what version were you using) - if there is a > hole you can describe I might be able to avoid it !! > > Michael Kellett > Michael, I too have been using EPC for some years (about 5) and hadn't had any problems until now. In July 09 (using version 12.0.5) I had a PCB which suffered from a signal via also shorting a power and ground Cu pour area. I reported this and a bug was found and allegedly fixed (up issue to 12.0.6). Software bugs crop up and I didn't make a big deal of it. In November 09 I had another design due for manufacture so I checked with Support that I had the required software fix and submitted the design for manufacture. This design had 3 vias that were again shorting Cu pour areas within the board. As far as I can see the fault wasn't fixed despite being told it was. The result to me was £1500 worth of PCBs being scrapped and an unhappy customer due to a missed delivery deadline. I was told that it was actually 2 faults that have exactly the same consequence - one was fixed in July but the second wasn't detected until my design came along in November. From the customer POV i.e. the important POV, the same fault re-occurred. I've approached them for some form of recompense or at least a good will gesture but they won't even answer my e-mails now. The vast majority of discussion has been via the user forum http://www.numberone.com/forum/topic.asp?TOPIC_ID=385 i.e. the Manufacturing Outputs, Gerber file corruption thread if you want to see more of this. Good luck. Rog.Article: 145014
Jonathan Bromley wrote: > http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip > One day, when there's less work to do, I intend to add a > few more file formats to its capabilities - but for now it > only knows how to mimic Verilog $readmemb/h. It seems to be enough for simple stuff so I could use it. It is licenced under Apache2.0, is it compatible with other Free Software licences ? (and which ?) yg -- http://ygdes.com / http://yasep.orgArticle: 145015
Hi, I was wondering why this declaration in my code: use IEEE.fixed_pkg.all; spits out this error when I try to synthesize in ISE 11.1 Library unit fixed_pkg is not available in library IEEE. It works in Active HDL simulation. Any idea why? Thanks, AmishArticle: 145016
On Jan 19, 5:35=A0pm, axr0284 <axr0...@yahoo.com> wrote: > Hi, > =A0I was wondering why this declaration in my code: > use IEEE.fixed_pkg.all; > > spits out this error when I try to synthesize in ISE 11.1 > Library unit fixed_pkg is not available in library IEEE. > > It works in Active HDL simulation. > > Any idea why? > Thanks, > Amish Vendors are starting to support VHDL 2008. ModelSim already supplies these. For synthesis, you might need to add a few translate_off/ translate_on for the version supplied by ModelSim. You can get a copy (not sure if it s up to date or not) from: http://www.eda-stds.org/vhdl-200x/vhdl-200x-ft/packages_old/vhdl-200x-pkgs_= 18.zip -- AmalArticle: 145017
On Jan 19, 7:12=A0pm, Amal <akhailt...@gmail.com> wrote: > On Jan 19, 5:35=A0pm, axr0284 <axr0...@yahoo.com> wrote: > > > Hi, > > =A0I was wondering why this declaration in my code: > > use IEEE.fixed_pkg.all; > > > spits out this error when I try to synthesize in ISE 11.1 > > Library unit fixed_pkg is not available in library IEEE. > > > It works in Active HDL simulation. > > > Any idea why? > > Thanks, > > Amish > > Vendors are starting to support VHDL 2008. =A0ModelSim already supplies > these. =A0For synthesis, you might need to add a few translate_off/ > translate_on for the version supplied by ModelSim. > > You can get a copy (not sure if it s up to date or not) from: > > http://www.eda-stds.org/vhdl-200x/vhdl-200x-ft/packages_old/vhdl-200x... > > -- Amal I guess Mike answered this here: http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/805c3397= b1fec45a -- AmalArticle: 145018
"Amal" <akhailtash@gmail.com> wrote in message news:927d246a-e4fd-4448-8683-643365d58b50@e16g2000yqc.googlegroups.com... On Jan 19, 5:35 pm, axr0284 <axr0...@yahoo.com> wrote: > Hi, > I was wondering why this declaration in my code: > use IEEE.fixed_pkg.all; > > spits out this error when I try to synthesize in ISE 11.1 > Library unit fixed_pkg is not available in library IEEE. > > It works in Active HDL simulation. > > Any idea why? > Thanks, > Amish > Vendors are starting to support VHDL 2008. Yes you are right, I just got Mentor's Precision beta program email and going through the features I noticed some VHDL2008 support including support for the fixed point, numeric_signed and numeric_unsigned packages. They next release will also support expressions in port maps which I assume they needed for the above packages since they don't seem to support any other VHDL2008 language constructs. Hans www.ht-lab.comArticle: 145019
HELLO .. I want to test my transmitter for AWGN .. i have coded my transmitter and receiver using VERILOG hdl .... kindly if anybody has verilog code for AWGN .. where i can change SNR values .. and calculate BER for each SNR.....any suggestions for simulating AWGN and calculate BER..... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145020
On Jan 20, 10:01=A0am, "Roger" <rogerwil...@hotmail.com> wrote: > This design had 3 vias that were again shorting Cu pour areas > within the board. Does it not have a Post-pour clearance/connectivity check ? I've also seen a PCB FAB's tool set (CAM350) drop the ball : if you give them Gerber FILL codes, CAM350 does not always quite get it right... That's why you should NOT use too much intelligence in your Gerber data, and use your PCB tools checks.... (and a Mk1 eyeball helps too )Article: 145021
On Tue, 19 Jan 2010 22:02:56 +0100, whygee <yg@yg.yg> wrote:
>Jonathan Bromley wrote:
>> http://www.oxfordbromley.plus.com/files/readmem/readmem_0.2a.zip
>> One day, when there's less work to do, I intend to add a
>> few more file formats to its capabilities - but for now it
>> only knows how to mimic Verilog $readmemb/h.
>
>It seems to be enough for simple stuff so I could use it.
Nice of you to say so - it kept the Verilog community happy
for nearly two decades, so perhaps it ain't so bad :-)
>It is licenced under Apache2.0, is it compatible with
>other Free Software licences ? (and which ?)
The point of the Apache licence, as I understand it, is
to say "do what the blazes you like with this, but don't
blame me if it doesn't do what you want". Unlike GPL
it permits you to include the code in closed-source
commercial products if you so choose (I think) but
does not allow you to claim it as your own, or to
restrict its use by others.
Legal experts may dispute this. If so, perhaps they
could be kind enough to tell me what I should do to
get the effect I describe in the previous paragraph.
I really, really don't want to be sued because there's
a bug in a piece of code I posted via Usenet; but if
I give away some code, I really want to give it away -
no strings [*] attached. Not even the manic-obsessive
doctrinaire-libertarian strings that are attached
by GPL.
[*] Puppet-style strings, that is. Arrays of ASCII
characters are OK :-)
--
Jonathan Bromley
Article: 145022"-jg" <jim.granville@gmail.com> wrote in message news:31d31451-4bcb-4f26-93ce-49c9346403a8@k19g2000yqc.googlegroups.com... > On Jan 20, 10:01 am, "Roger" <rogerwil...@hotmail.com> wrote: >> This design had 3 vias that were again shorting Cu pour areas >> within the board. > > Does it not have a Post-pour clearance/connectivity check ? > > I've also seen a PCB FAB's tool set (CAM350) drop the ball : if you > give them Gerber FILL codes, CAM350 does not always quite get it > right... > > That's why you should NOT use too much intelligence in your Gerber > data, and use your PCB tools checks.... > (and a Mk1 eyeball helps too ) > Jim, The DRC tool checks the clearances and connectivity of the design within the EPC environment. The fault appears when the Gerber files are generated i.e. the Gerbers had the Cu touching the vias whereas this wasn't the case when still in the design environment. The DRC obviously reports no problems as it works within the EPC environment. Interesting what you say about the FILL codes, I've not heard of that before. Rog.Article: 145023
Hello All, I am a beginner and want to get an idea how to construct actual FPGA- based design (a PCB) after this was developed and tested using development board (I use Xilinx Microblaze 1600E development board). My understanding is that as my particular project uses just some of the features available on the development board (in my design these are RS232 port, FPGA chip, ADC, DAC, BNC connector for radiofrequency signal output) only these have to be constructed on my PCB - is this correct. I also will need to accomodate on my PCB a ROM where hardware configuration (which will be downloaded to FPGA chip each time when it is powered on) is saved. And I do not understand one thing here - this ROM obviously has to be programmed in advance in order to keep hardware configuration - is this programming normally done on a development board? Thank you. Please feel free to comment on my questions and tell more (whatever you find relevant) about construction of FPGA-based designs for beginners - I am a beginner and interested to learn about any aspect of this.Article: 145024
HI everyone, I'm trying to send 16 byte data block through DE2 board. Does anyone have experience on this? I do modify the ReadEndpoint, WriteEndpoint and SetEndpointConfiguration coding. But I still can’t get the bulk transfer for 16 byte data. What had I miss? Help me...... please. Thanks, summer --------------------------------------- Posted through http://www.FPGARelated.com
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